2020-10-10 00:41:21 +08:00
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add_llvm_component_group(ARM HAS_JIT)
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2008-09-26 12:40:32 +08:00
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set(LLVM_TARGET_DEFINITIONS ARM.td)
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2018-04-04 20:37:44 +08:00
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tablegen(LLVM ARMGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM ARMGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
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2017-08-04 05:52:25 +08:00
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tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
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2011-11-05 03:04:23 +08:00
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tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
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2014-09-03 06:28:02 +08:00
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tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
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2011-11-05 03:04:23 +08:00
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tablegen(LLVM ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
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2018-04-04 20:37:44 +08:00
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tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
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tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info)
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2011-11-05 03:04:23 +08:00
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tablegen(LLVM ARMGenSubtargetInfo.inc -gen-subtarget)
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2017-07-19 20:57:16 +08:00
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tablegen(LLVM ARMGenSystemRegister.inc -gen-searchable-tables)
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2018-04-04 20:37:44 +08:00
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Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.
These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.
To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.
This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.
Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.
llvm-svn: 136023
2011-07-26 08:09:08 +08:00
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add_public_tablegen_target(ARMCommonTableGen)
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2008-09-26 12:40:32 +08:00
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2008-10-22 10:51:53 +08:00
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add_llvm_target(ARMCodeGen
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2013-03-16 02:28:25 +08:00
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A15SDOptimizer.cpp
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2010-07-20 08:08:13 +08:00
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ARMAsmPrinter.cpp
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2009-07-09 00:09:28 +08:00
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ARMBaseInstrInfo.cpp
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2009-07-09 04:13:41 +08:00
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ARMBaseRegisterInfo.cpp
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2019-06-17 16:49:09 +08:00
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ARMBasicBlockInfo.cpp
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2019-01-29 05:28:43 +08:00
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ARMCallingConv.cpp
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2017-08-04 05:52:25 +08:00
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ARMCallLowering.cpp
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2008-09-26 12:40:32 +08:00
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ARMConstantIslandPass.cpp
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ARMConstantPoolValue.cpp
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2009-11-07 11:26:59 +08:00
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ARMExpandPseudoInsts.cpp
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2010-07-22 14:00:01 +08:00
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ARMFastISel.cpp
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2011-01-10 20:39:23 +08:00
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ARMFrameLowering.cpp
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2010-12-06 06:04:16 +08:00
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ARMHazardRecognizer.cpp
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2017-08-04 05:52:25 +08:00
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ARMInstructionSelector.cpp
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2008-09-26 12:40:32 +08:00
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ARMISelDAGToDAG.cpp
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ARMISelLowering.cpp
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2009-11-03 12:14:12 +08:00
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ARMInstrInfo.cpp
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2017-08-04 05:52:25 +08:00
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ARMLegalizerInfo.cpp
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2018-06-28 20:55:29 +08:00
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ARMParallelDSP.cpp
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2008-09-26 12:40:32 +08:00
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ARMLoadStoreOptimizer.cpp
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2019-06-25 18:45:51 +08:00
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ARMLowOverheadLoops.cpp
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2010-07-20 08:08:13 +08:00
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ARMMCInstLower.cpp
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2011-12-20 16:42:11 +08:00
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ARMMachineFunctionInfo.cpp
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2017-06-22 17:39:36 +08:00
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ARMMacroFusion.cpp
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2008-09-26 12:40:32 +08:00
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ARMRegisterInfo.cpp
|
2014-04-02 17:03:43 +08:00
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ARMOptimizeBarriersPass.cpp
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2017-08-04 05:52:25 +08:00
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ARMRegisterBankInfo.cpp
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2010-07-20 08:08:13 +08:00
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ARMSelectionDAGInfo.cpp
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2008-09-26 12:40:32 +08:00
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ARMSubtarget.cpp
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ARMTargetMachine.cpp
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2010-03-10 02:31:07 +08:00
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ARMTargetObjectFile.cpp
|
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
llvm-svn: 171681
2013-01-07 09:37:14 +08:00
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|
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ARMTargetTransformInfo.cpp
|
2010-12-06 07:08:57 +08:00
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MLxExpansionPass.cpp
|
2020-01-08 21:08:27 +08:00
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MVEGatherScatterLowering.cpp
|
[ARM] MVE Tail Predication
The MVE and LOB extensions of Armv8.1m can be combined to enable
'tail predication' which removes the need for a scalar remainder
loop after vectorization. Lane predication is performed implicitly
via a system register. The effects of predication is described in
Section B5.6.3 of the Armv8.1-m Arch Reference Manual, the key points
being:
- For vector operations that perform reduction across the vector and
produce a scalar result, whether the value is accumulated or not.
- For non-load instructions, the predicate flags determine if the
destination register byte is updated with the new value or if the
previous value is preserved.
- For vector store instructions, whether the store occurs or not.
- For vector load instructions, whether the value that is loaded or
whether zeros are written to that element of the destination
register.
This patch implements a pass that takes a hardware loop, containing
masked vector instructions, and converts it something that resembles
an MVE tail predicated loop. Currently, if we had code generation,
we'd generate a loop in which the VCTP would generate the predicate
and VPST would then setup the value of VPR.PO. The loads and stores
would be placed in VPT blocks so this is not tail predication, but
normal VPT predication with the predicate based upon a element
counting induction variable. Further work needs to be done to finally
produce a true tail predicated loop.
Because only the loads and stores are predicated, in both the LLVM IR
and MIR level, we will restrict support to only lane-wise operations
(no horizontal reductions). We will perform a final check on MIR
during loop finalisation too.
Another restriction, specific to MVE, is that all the vector
instructions need operate on the same number of elements. This is
because predication is performed at the byte level and this is set
on entry to the loop, or by the VCTP instead.
Differential Revision: https://reviews.llvm.org/D65884
llvm-svn: 371179
2019-09-06 16:24:41 +08:00
|
|
|
MVETailPredication.cpp
|
2019-08-28 19:37:31 +08:00
|
|
|
MVEVPTBlockPass.cpp
|
2020-03-18 23:23:17 +08:00
|
|
|
MVEVPTOptimisationsPass.cpp
|
2011-01-10 20:39:23 +08:00
|
|
|
Thumb1FrameLowering.cpp
|
2011-09-28 07:29:59 +08:00
|
|
|
Thumb1InstrInfo.cpp
|
2015-03-13 06:48:50 +08:00
|
|
|
ThumbRegisterInfo.cpp
|
2009-07-10 16:31:50 +08:00
|
|
|
Thumb2ITBlockPass.cpp
|
2009-07-03 06:18:33 +08:00
|
|
|
Thumb2InstrInfo.cpp
|
2009-08-09 01:03:13 +08:00
|
|
|
Thumb2SizeReduction.cpp
|
2020-10-10 00:41:21 +08:00
|
|
|
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|
|
|
LINK_COMPONENTS
|
|
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|
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ARMDesc
|
|
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ARMInfo
|
|
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Analysis
|
|
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AsmPrinter
|
|
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|
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CodeGen
|
|
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|
Core
|
|
|
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MC
|
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Scalar
|
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SelectionDAG
|
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Support
|
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Target
|
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GlobalISel
|
|
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|
|
ARMUtils
|
|
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|
TransformUtils
|
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CFGuard
|
|
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ADD_TO_COMPONENT
|
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|
ARM
|
2008-09-26 12:40:32 +08:00
|
|
|
)
|
2010-12-29 11:59:27 +08:00
|
|
|
|
2011-02-20 10:55:27 +08:00
|
|
|
add_subdirectory(AsmParser)
|
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add_subdirectory(Disassembler)
|
2011-07-07 06:02:34 +08:00
|
|
|
add_subdirectory(MCTargetDesc)
|
2018-04-23 20:49:34 +08:00
|
|
|
add_subdirectory(TargetInfo)
|
2017-07-19 20:57:16 +08:00
|
|
|
add_subdirectory(Utils)
|