2007-05-16 10:00:57 +08:00
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//===-- IfConversion.cpp - Machine code if conversion pass. ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-05-16 10:00:57 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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2016-04-01 09:09:03 +08:00
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// This file implements the machine instruction level if-conversion pass, which
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// tries to convert conditional branches into predicated instructions.
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2007-05-16 10:00:57 +08:00
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/Passes.h"
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2012-12-04 00:50:05 +08:00
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#include "BranchFolding.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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2014-01-07 19:48:04 +08:00
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#include "llvm/CodeGen/LivePhysRegs.h"
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2014-08-08 03:30:13 +08:00
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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2011-08-04 06:53:41 +08:00
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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2007-05-16 10:00:57 +08:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2012-12-21 02:08:06 +08:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/CodeGen/MachineModuleInfo.h"
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2012-06-09 05:53:50 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2013-09-30 23:28:56 +08:00
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#include "llvm/CodeGen/TargetSchedule.h"
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2007-06-09 03:10:51 +08:00
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#include "llvm/Support/CommandLine.h"
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2007-05-16 10:00:57 +08:00
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#include "llvm/Support/Debug.h"
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2009-07-11 21:10:19 +08:00
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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2013-09-30 23:28:56 +08:00
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#include "llvm/Target/TargetSubtargetInfo.h"
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2015-12-01 13:29:22 +08:00
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#include <algorithm>
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2016-05-27 22:27:24 +08:00
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#include <utility>
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2013-09-30 23:28:56 +08:00
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2007-05-16 10:00:57 +08:00
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using namespace llvm;
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2014-04-22 10:02:50 +08:00
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#define DEBUG_TYPE "ifcvt"
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2008-01-07 13:40:58 +08:00
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// Hidden options for help debugging.
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static cl::opt<int> IfCvtFnStart("ifcvt-fn-start", cl::init(-1), cl::Hidden);
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static cl::opt<int> IfCvtFnStop("ifcvt-fn-stop", cl::init(-1), cl::Hidden);
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static cl::opt<int> IfCvtLimit("ifcvt-limit", cl::init(-1), cl::Hidden);
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2010-06-16 06:18:54 +08:00
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static cl::opt<bool> DisableSimple("disable-ifcvt-simple",
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2008-01-07 13:40:58 +08:00
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cl::init(false), cl::Hidden);
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2010-06-16 06:18:54 +08:00
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static cl::opt<bool> DisableSimpleF("disable-ifcvt-simple-false",
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2008-01-07 13:40:58 +08:00
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cl::init(false), cl::Hidden);
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2010-06-16 06:18:54 +08:00
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static cl::opt<bool> DisableTriangle("disable-ifcvt-triangle",
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2008-01-07 13:40:58 +08:00
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cl::init(false), cl::Hidden);
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2010-06-16 06:18:54 +08:00
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static cl::opt<bool> DisableTriangleR("disable-ifcvt-triangle-rev",
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2008-01-07 13:40:58 +08:00
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cl::init(false), cl::Hidden);
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2010-06-16 06:18:54 +08:00
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static cl::opt<bool> DisableTriangleF("disable-ifcvt-triangle-false",
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2008-01-07 13:40:58 +08:00
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cl::init(false), cl::Hidden);
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2010-06-16 06:18:54 +08:00
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static cl::opt<bool> DisableTriangleFR("disable-ifcvt-triangle-false-rev",
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2008-01-07 13:40:58 +08:00
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cl::init(false), cl::Hidden);
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2010-06-16 06:18:54 +08:00
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static cl::opt<bool> DisableDiamond("disable-ifcvt-diamond",
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2008-01-07 13:40:58 +08:00
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cl::init(false), cl::Hidden);
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2010-06-16 15:35:02 +08:00
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static cl::opt<bool> IfCvtBranchFold("ifcvt-branch-fold",
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cl::init(true), cl::Hidden);
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2007-06-09 03:10:51 +08:00
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2007-06-09 09:03:43 +08:00
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STATISTIC(NumSimple, "Number of simple if-conversions performed");
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STATISTIC(NumSimpleFalse, "Number of simple (F) if-conversions performed");
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STATISTIC(NumTriangle, "Number of triangle if-conversions performed");
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2007-06-13 07:54:05 +08:00
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STATISTIC(NumTriangleRev, "Number of triangle (R) if-conversions performed");
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2007-06-09 09:03:43 +08:00
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STATISTIC(NumTriangleFalse,"Number of triangle (F) if-conversions performed");
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STATISTIC(NumTriangleFRev, "Number of triangle (F/R) if-conversions performed");
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STATISTIC(NumDiamonds, "Number of diamond if-conversions performed");
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STATISTIC(NumIfConvBBs, "Number of if-converted blocks");
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2007-06-15 15:36:12 +08:00
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STATISTIC(NumDupBBs, "Number of duplicated blocks");
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Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
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STATISTIC(NumUnpred, "Number of true blocks of diamonds unpredicated");
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2007-05-16 10:00:57 +08:00
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namespace {
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2009-10-25 14:33:48 +08:00
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class IfConverter : public MachineFunctionPass {
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2007-06-16 17:34:52 +08:00
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enum IfcvtKind {
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2007-05-16 10:00:57 +08:00
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ICNotClassfied, // BB data valid, but not classified.
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2007-06-04 14:47:22 +08:00
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ICSimpleFalse, // Same as ICSimple, but on the false path.
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2007-06-16 17:34:52 +08:00
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ICSimple, // BB is entry of an one split, no rejoin sub-CFG.
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ICTriangleFRev, // Same as ICTriangleFalse, but false path rev condition.
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2007-06-13 07:54:05 +08:00
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ICTriangleRev, // Same as ICTriangle, but true path rev condition.
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2007-06-09 09:03:43 +08:00
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ICTriangleFalse, // Same as ICTriangle, but on the false path.
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2007-06-16 17:34:52 +08:00
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ICTriangle, // BB is entry of a triangle sub-CFG.
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2007-06-12 06:26:22 +08:00
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ICDiamond // BB is entry of a diamond sub-CFG.
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2007-05-16 10:00:57 +08:00
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};
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/// BBInfo - One per MachineBasicBlock, this is used to cache the result
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/// if-conversion feasibility analysis. This includes results from
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2016-07-15 22:41:04 +08:00
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/// TargetInstrInfo::analyzeBranch() (i.e. TBB, FBB, and Cond), and its
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2007-05-18 08:20:58 +08:00
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/// classification, and common tail block of its successors (if it's a
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2007-05-19 02:14:37 +08:00
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/// diamond shape), its size, whether it's predicable, and whether any
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/// instruction can clobber the 'would-be' predicate.
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2007-05-23 15:23:16 +08:00
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///
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2007-06-12 06:26:22 +08:00
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/// IsDone - True if BB is not to be considered for ifcvt.
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/// IsBeingAnalyzed - True if BB is currently being analyzed.
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/// IsAnalyzed - True if BB has been analyzed (info is still valid).
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/// IsEnqueued - True if BB has been enqueued to be ifcvt'ed.
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2016-07-15 22:41:04 +08:00
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/// IsBrAnalyzable - True if analyzeBranch() returns false.
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2007-06-12 06:26:22 +08:00
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/// HasFallThrough - True if BB may fallthrough to the following BB.
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/// IsUnpredicable - True if BB is known to be unpredicable.
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2007-07-11 01:50:43 +08:00
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/// ClobbersPred - True if BB could modify predicates (e.g. has
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2007-06-06 18:16:17 +08:00
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/// cmp, call, etc.)
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2007-06-12 06:26:22 +08:00
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/// NonPredSize - Number of non-predicated instructions.
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2010-11-03 08:45:17 +08:00
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/// ExtraCost - Extra cost for multi-cycle instructions.
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/// ExtraCost2 - Some instructions are slower when predicated
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2007-05-23 15:23:16 +08:00
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/// BB - Corresponding MachineBasicBlock.
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2016-07-15 22:41:04 +08:00
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/// TrueBB / FalseBB- See analyzeBranch().
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2007-05-23 15:23:16 +08:00
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/// BrCond - Conditions for end of block conditional branches.
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/// Predicate - Predicate used in the BB.
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2007-05-16 10:00:57 +08:00
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struct BBInfo {
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2007-06-12 06:26:22 +08:00
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bool IsDone : 1;
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bool IsBeingAnalyzed : 1;
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bool IsAnalyzed : 1;
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bool IsEnqueued : 1;
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bool IsBrAnalyzable : 1;
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bool HasFallThrough : 1;
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bool IsUnpredicable : 1;
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2007-06-16 05:18:05 +08:00
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bool CannotBeCopied : 1;
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2007-06-12 06:26:22 +08:00
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bool ClobbersPred : 1;
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2007-05-23 15:23:16 +08:00
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unsigned NonPredSize;
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2010-10-26 08:02:21 +08:00
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unsigned ExtraCost;
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2010-11-03 08:45:17 +08:00
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unsigned ExtraCost2;
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2007-05-18 08:20:58 +08:00
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MachineBasicBlock *BB;
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MachineBasicBlock *TrueBB;
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MachineBasicBlock *FalseBB;
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2008-08-15 06:49:33 +08:00
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SmallVector<MachineOperand, 4> BrCond;
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SmallVector<MachineOperand, 4> Predicate;
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2007-06-16 17:34:52 +08:00
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BBInfo() : IsDone(false), IsBeingAnalyzed(false),
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2007-06-12 06:26:22 +08:00
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IsAnalyzed(false), IsEnqueued(false), IsBrAnalyzable(false),
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HasFallThrough(false), IsUnpredicable(false),
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2007-06-16 05:18:05 +08:00
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CannotBeCopied(false), ClobbersPred(false), NonPredSize(0),
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2014-04-14 08:51:57 +08:00
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ExtraCost(0), ExtraCost2(0), BB(nullptr), TrueBB(nullptr),
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FalseBB(nullptr) {}
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2007-06-16 17:34:52 +08:00
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};
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2010-06-16 02:19:27 +08:00
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/// IfcvtToken - Record information about pending if-conversions to attempt:
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2007-06-16 17:34:52 +08:00
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/// BBI - Corresponding BBInfo.
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/// Kind - Type of block. See IfcvtKind.
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2009-05-14 07:25:24 +08:00
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/// NeedSubsumption - True if the to-be-predicated BB has already been
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2007-06-16 17:34:52 +08:00
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/// predicated.
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2007-06-18 16:37:25 +08:00
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/// NumDups - Number of instructions that would be duplicated due
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/// to this if-conversion. (For diamonds, the number of
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/// identical instructions at the beginnings of both
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/// paths).
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/// NumDups2 - For diamonds, the number of identical instructions
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/// at the ends of both paths.
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2007-06-16 17:34:52 +08:00
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struct IfcvtToken {
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BBInfo &BBI;
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IfcvtKind Kind;
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2009-05-14 07:25:24 +08:00
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bool NeedSubsumption;
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2007-06-18 16:37:25 +08:00
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unsigned NumDups;
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unsigned NumDups2;
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IfcvtToken(BBInfo &b, IfcvtKind k, bool s, unsigned d, unsigned d2 = 0)
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2009-05-14 07:25:24 +08:00
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: BBI(b), Kind(k), NeedSubsumption(s), NumDups(d), NumDups2(d2) {}
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2007-05-16 10:00:57 +08:00
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};
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/// BBAnalysis - Results of if-conversion feasibility analysis indexed by
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/// basic block number.
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std::vector<BBInfo> BBAnalysis;
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2013-09-30 23:28:56 +08:00
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TargetSchedModel SchedModel;
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2007-05-16 10:00:57 +08:00
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2013-01-12 04:05:37 +08:00
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const TargetLoweringBase *TLI;
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2007-05-16 10:00:57 +08:00
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const TargetInstrInfo *TII;
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2010-06-16 15:35:02 +08:00
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const TargetRegisterInfo *TRI;
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2011-08-04 06:34:43 +08:00
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const MachineBranchProbabilityInfo *MBPI;
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2012-06-09 05:53:50 +08:00
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MachineRegisterInfo *MRI;
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2011-08-04 06:34:43 +08:00
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2013-12-14 14:52:56 +08:00
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LivePhysRegs Redefs;
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LivePhysRegs DontKill;
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2013-10-15 04:45:17 +08:00
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2012-06-09 05:53:50 +08:00
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bool PreRegAlloc;
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2007-05-16 10:00:57 +08:00
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bool MadeChange;
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2009-06-25 07:41:44 +08:00
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int FnNum;
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2015-06-09 02:50:43 +08:00
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std::function<bool(const Function &)> PredicateFtor;
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2007-05-16 10:00:57 +08:00
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public:
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static char ID;
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2015-06-09 02:50:43 +08:00
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IfConverter(std::function<bool(const Function &)> Ftor = nullptr)
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2016-05-27 22:27:24 +08:00
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: MachineFunctionPass(ID), FnNum(-1), PredicateFtor(std::move(Ftor)) {
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2010-10-20 01:21:58 +08:00
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initializeIfConverterPass(*PassRegistry::getPassRegistry());
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}
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2011-08-04 06:34:43 +08:00
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2014-03-07 17:26:03 +08:00
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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2014-08-08 03:30:13 +08:00
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AU.addRequired<MachineBlockFrequencyInfo>();
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2011-08-04 06:34:43 +08:00
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AU.addRequired<MachineBranchProbabilityInfo>();
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2010-09-29 04:42:15 +08:00
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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2007-05-16 10:00:57 +08:00
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2014-03-07 17:26:03 +08:00
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bool runOnMachineFunction(MachineFunction &MF) override;
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2007-05-16 10:00:57 +08:00
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2016-04-05 01:09:25 +08:00
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::AllVRegsAllocated);
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}
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2007-05-16 10:00:57 +08:00
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private:
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2016-07-28 04:19:31 +08:00
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bool ReverseBranchCondition(BBInfo &BBI) const;
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2010-10-02 06:45:50 +08:00
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bool ValidSimple(BBInfo &TrueBBI, unsigned &Dups,
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2015-09-11 07:10:42 +08:00
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BranchProbability Prediction) const;
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2007-06-08 17:36:04 +08:00
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bool ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI,
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2010-10-02 06:45:50 +08:00
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bool FalseBranch, unsigned &Dups,
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2015-09-11 07:10:42 +08:00
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BranchProbability Prediction) const;
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2007-06-18 16:37:25 +08:00
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bool ValidDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,
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unsigned &Dups1, unsigned &Dups2) const;
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2007-06-08 17:36:04 +08:00
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void ScanInstructions(BBInfo &BBI);
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2016-02-23 01:51:28 +08:00
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void AnalyzeBlock(MachineBasicBlock *MBB,
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std::vector<std::unique_ptr<IfcvtToken>> &Tokens);
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2008-08-15 06:49:33 +08:00
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bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl<MachineOperand> &Cond,
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2007-06-08 17:36:04 +08:00
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bool isTriangle = false, bool RevBranch = false);
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2016-02-23 01:51:28 +08:00
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void AnalyzeBlocks(MachineFunction &MF,
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std::vector<std::unique_ptr<IfcvtToken>> &Tokens);
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2007-06-18 16:37:25 +08:00
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void InvalidatePreds(MachineBasicBlock *BB);
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2007-06-09 06:01:07 +08:00
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void RemoveExtraEdges(BBInfo &BBI);
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2007-06-16 17:34:52 +08:00
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bool IfConvertSimple(BBInfo &BBI, IfcvtKind Kind);
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bool IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind);
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2007-06-18 16:37:25 +08:00
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bool IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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unsigned NumDups1, unsigned NumDups2);
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2007-05-23 15:23:16 +08:00
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void PredicateBlock(BBInfo &BBI,
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2007-06-18 16:37:25 +08:00
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MachineBasicBlock::iterator E,
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2010-06-16 15:35:02 +08:00
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SmallVectorImpl<MachineOperand> &Cond,
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2014-04-14 08:51:57 +08:00
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|
SmallSet<unsigned, 4> *LaterRedefs = nullptr);
|
2007-06-15 15:36:12 +08:00
|
|
|
void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
|
2008-08-15 06:49:33 +08:00
|
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
2007-06-15 15:36:12 +08:00
|
|
|
bool IgnoreBr = false);
|
Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 08:55:23 +08:00
|
|
|
void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges = true);
|
2007-06-01 08:12:12 +08:00
|
|
|
|
2010-11-03 08:45:17 +08:00
|
|
|
bool MeetIfcvtSizeLimit(MachineBasicBlock &BB,
|
|
|
|
unsigned Cycle, unsigned Extra,
|
2015-09-11 07:10:42 +08:00
|
|
|
BranchProbability Prediction) const {
|
2010-11-03 08:45:17 +08:00
|
|
|
return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra,
|
2011-07-10 10:58:07 +08:00
|
|
|
Prediction);
|
2010-06-26 06:42:03 +08:00
|
|
|
}
|
|
|
|
|
2010-11-03 08:45:17 +08:00
|
|
|
bool MeetIfcvtSizeLimit(MachineBasicBlock &TBB,
|
|
|
|
unsigned TCycle, unsigned TExtra,
|
|
|
|
MachineBasicBlock &FBB,
|
|
|
|
unsigned FCycle, unsigned FExtra,
|
2015-09-11 07:10:42 +08:00
|
|
|
BranchProbability Prediction) const {
|
2010-11-03 08:45:17 +08:00
|
|
|
return TCycle > 0 && FCycle > 0 &&
|
|
|
|
TII->isProfitableToIfCvt(TBB, TCycle, TExtra, FBB, FCycle, FExtra,
|
2011-07-10 10:58:07 +08:00
|
|
|
Prediction);
|
2007-06-18 16:37:25 +08:00
|
|
|
}
|
|
|
|
|
2007-06-07 10:12:15 +08:00
|
|
|
// blockAlwaysFallThrough - Block ends without a terminator.
|
|
|
|
bool blockAlwaysFallThrough(BBInfo &BBI) const {
|
2014-04-14 08:51:57 +08:00
|
|
|
return BBI.IsBrAnalyzable && BBI.TrueBB == nullptr;
|
2007-06-06 18:16:17 +08:00
|
|
|
}
|
|
|
|
|
2007-06-16 17:34:52 +08:00
|
|
|
// IfcvtTokenCmp - Used to sort if-conversion candidates.
|
2016-02-23 01:51:28 +08:00
|
|
|
static bool IfcvtTokenCmp(const std::unique_ptr<IfcvtToken> &C1,
|
|
|
|
const std::unique_ptr<IfcvtToken> &C2) {
|
2007-06-18 16:37:25 +08:00
|
|
|
int Incr1 = (C1->Kind == ICDiamond)
|
|
|
|
? -(int)(C1->NumDups + C1->NumDups2) : (int)C1->NumDups;
|
|
|
|
int Incr2 = (C2->Kind == ICDiamond)
|
|
|
|
? -(int)(C2->NumDups + C2->NumDups2) : (int)C2->NumDups;
|
|
|
|
if (Incr1 > Incr2)
|
2007-06-16 17:34:52 +08:00
|
|
|
return true;
|
2007-06-18 16:37:25 +08:00
|
|
|
else if (Incr1 == Incr2) {
|
2009-05-14 07:25:24 +08:00
|
|
|
// Favors subsumption.
|
2015-03-09 09:57:13 +08:00
|
|
|
if (!C1->NeedSubsumption && C2->NeedSubsumption)
|
2007-06-16 17:34:52 +08:00
|
|
|
return true;
|
2009-05-14 07:25:24 +08:00
|
|
|
else if (C1->NeedSubsumption == C2->NeedSubsumption) {
|
2007-06-16 17:34:52 +08:00
|
|
|
// Favors diamond over triangle, etc.
|
|
|
|
if ((unsigned)C1->Kind < (unsigned)C2->Kind)
|
|
|
|
return true;
|
|
|
|
else if (C1->Kind == C2->Kind)
|
|
|
|
return C1->BBI.BB->getNumber() < C2->BBI.BB->getNumber();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
2007-06-01 08:12:12 +08:00
|
|
|
}
|
2007-05-16 10:00:57 +08:00
|
|
|
};
|
2007-06-16 17:34:52 +08:00
|
|
|
|
2007-05-16 10:00:57 +08:00
|
|
|
char IfConverter::ID = 0;
|
2015-06-23 17:49:53 +08:00
|
|
|
}
|
2007-05-16 10:00:57 +08:00
|
|
|
|
2012-02-09 05:23:13 +08:00
|
|
|
char &llvm::IfConverterID = IfConverter::ID;
|
|
|
|
|
2010-10-13 03:48:12 +08:00
|
|
|
INITIALIZE_PASS_BEGIN(IfConverter, "if-converter", "If Converter", false, false)
|
2011-08-04 06:34:43 +08:00
|
|
|
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
|
2010-10-13 03:48:12 +08:00
|
|
|
INITIALIZE_PASS_END(IfConverter, "if-converter", "If Converter", false, false)
|
2009-10-29 04:46:46 +08:00
|
|
|
|
2007-05-16 10:00:57 +08:00
|
|
|
bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
|
2016-05-04 06:32:30 +08:00
|
|
|
if (skipFunction(*MF.getFunction()) ||
|
|
|
|
(PredicateFtor && !PredicateFtor(*MF.getFunction())))
|
2015-06-09 02:50:43 +08:00
|
|
|
return false;
|
|
|
|
|
2015-01-27 15:31:29 +08:00
|
|
|
const TargetSubtargetInfo &ST = MF.getSubtarget();
|
|
|
|
TLI = ST.getTargetLowering();
|
|
|
|
TII = ST.getInstrInfo();
|
|
|
|
TRI = ST.getRegisterInfo();
|
2016-06-09 23:24:29 +08:00
|
|
|
BranchFolder::MBFIWrapper MBFI(getAnalysis<MachineBlockFrequencyInfo>());
|
2011-08-04 06:34:43 +08:00
|
|
|
MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
|
2012-06-09 05:53:50 +08:00
|
|
|
MRI = &MF.getRegInfo();
|
2014-09-03 01:43:54 +08:00
|
|
|
SchedModel.init(ST.getSchedModel(), &ST, TII);
|
2013-09-30 23:28:56 +08:00
|
|
|
|
2007-05-16 10:00:57 +08:00
|
|
|
if (!TII) return false;
|
|
|
|
|
2012-06-09 05:53:50 +08:00
|
|
|
PreRegAlloc = MRI->isSSA();
|
|
|
|
|
|
|
|
bool BFChange = false;
|
|
|
|
if (!PreRegAlloc) {
|
|
|
|
// Tail merge tend to expose more if-conversion opportunities.
|
2016-06-09 23:24:29 +08:00
|
|
|
BranchFolder BF(true, false, MBFI, *MBPI);
|
2015-01-27 15:31:29 +08:00
|
|
|
BFChange = BF.OptimizeFunction(MF, TII, ST.getRegisterInfo(),
|
2014-08-05 10:39:49 +08:00
|
|
|
getAnalysisIfAvailable<MachineModuleInfo>());
|
2012-06-09 05:53:50 +08:00
|
|
|
}
|
2010-06-19 07:09:54 +08:00
|
|
|
|
2010-01-05 06:02:01 +08:00
|
|
|
DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'"
|
2012-08-22 14:07:19 +08:00
|
|
|
<< MF.getName() << "\'");
|
2007-06-09 03:10:51 +08:00
|
|
|
|
|
|
|
if (FnNum < IfCvtFnStart || (IfCvtFnStop != -1 && FnNum > IfCvtFnStop)) {
|
2010-01-05 06:02:01 +08:00
|
|
|
DEBUG(dbgs() << " skipped\n");
|
2007-06-09 03:10:51 +08:00
|
|
|
return false;
|
|
|
|
}
|
2010-01-05 06:02:01 +08:00
|
|
|
DEBUG(dbgs() << "\n");
|
2007-06-01 08:12:12 +08:00
|
|
|
|
2007-05-16 10:00:57 +08:00
|
|
|
MF.RenumberBlocks();
|
2007-06-01 08:12:12 +08:00
|
|
|
BBAnalysis.resize(MF.getNumBlockIDs());
|
2007-05-16 10:00:57 +08:00
|
|
|
|
2016-02-23 01:51:28 +08:00
|
|
|
std::vector<std::unique_ptr<IfcvtToken>> Tokens;
|
2007-05-18 09:55:58 +08:00
|
|
|
MadeChange = false;
|
2007-06-15 15:36:12 +08:00
|
|
|
unsigned NumIfCvts = NumSimple + NumSimpleFalse + NumTriangle +
|
|
|
|
NumTriangleRev + NumTriangleFalse + NumTriangleFRev + NumDiamonds;
|
|
|
|
while (IfCvtLimit == -1 || (int)NumIfCvts < IfCvtLimit) {
|
2009-05-14 07:25:24 +08:00
|
|
|
// Do an initial analysis for each basic block and find all the potential
|
|
|
|
// candidates to perform if-conversion.
|
2010-06-16 02:57:15 +08:00
|
|
|
bool Change = false;
|
|
|
|
AnalyzeBlocks(MF, Tokens);
|
2007-06-16 17:34:52 +08:00
|
|
|
while (!Tokens.empty()) {
|
2016-02-23 01:51:28 +08:00
|
|
|
std::unique_ptr<IfcvtToken> Token = std::move(Tokens.back());
|
2007-06-16 17:34:52 +08:00
|
|
|
Tokens.pop_back();
|
|
|
|
BBInfo &BBI = Token->BBI;
|
|
|
|
IfcvtKind Kind = Token->Kind;
|
2008-11-04 21:02:59 +08:00
|
|
|
unsigned NumDups = Token->NumDups;
|
2008-11-05 02:05:30 +08:00
|
|
|
unsigned NumDups2 = Token->NumDups2;
|
2008-11-04 21:02:59 +08:00
|
|
|
|
2007-06-12 06:26:22 +08:00
|
|
|
// If the block has been evicted out of the queue or it has already been
|
|
|
|
// marked dead (due to it being predicated), then skip it.
|
2007-06-16 17:34:52 +08:00
|
|
|
if (BBI.IsDone)
|
|
|
|
BBI.IsEnqueued = false;
|
|
|
|
if (!BBI.IsEnqueued)
|
2007-06-12 06:26:22 +08:00
|
|
|
continue;
|
2007-06-16 17:34:52 +08:00
|
|
|
|
2007-06-15 04:28:52 +08:00
|
|
|
BBI.IsEnqueued = false;
|
2007-06-12 06:26:22 +08:00
|
|
|
|
2007-06-04 14:47:22 +08:00
|
|
|
bool RetVal = false;
|
2007-06-16 17:34:52 +08:00
|
|
|
switch (Kind) {
|
2012-02-05 16:31:47 +08:00
|
|
|
default: llvm_unreachable("Unexpected!");
|
2007-06-04 14:47:22 +08:00
|
|
|
case ICSimple:
|
2007-06-06 09:12:44 +08:00
|
|
|
case ICSimpleFalse: {
|
2007-06-16 17:34:52 +08:00
|
|
|
bool isFalse = Kind == ICSimpleFalse;
|
2007-06-09 09:03:43 +08:00
|
|
|
if ((isFalse && DisableSimpleF) || (!isFalse && DisableSimple)) break;
|
2010-06-16 06:18:54 +08:00
|
|
|
DEBUG(dbgs() << "Ifcvt (Simple" << (Kind == ICSimpleFalse ?
|
|
|
|
" false" : "")
|
2009-08-23 04:11:17 +08:00
|
|
|
<< "): BB#" << BBI.BB->getNumber() << " ("
|
|
|
|
<< ((Kind == ICSimpleFalse)
|
|
|
|
? BBI.FalseBB->getNumber()
|
|
|
|
: BBI.TrueBB->getNumber()) << ") ");
|
2007-06-16 17:34:52 +08:00
|
|
|
RetVal = IfConvertSimple(BBI, Kind);
|
2010-01-05 06:02:01 +08:00
|
|
|
DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
|
2008-02-20 19:10:28 +08:00
|
|
|
if (RetVal) {
|
2010-06-22 23:08:57 +08:00
|
|
|
if (isFalse) ++NumSimpleFalse;
|
|
|
|
else ++NumSimple;
|
2008-02-20 19:10:28 +08:00
|
|
|
}
|
2007-06-04 14:47:22 +08:00
|
|
|
break;
|
2007-06-06 09:12:44 +08:00
|
|
|
}
|
2007-05-23 15:23:16 +08:00
|
|
|
case ICTriangle:
|
2007-06-13 07:54:05 +08:00
|
|
|
case ICTriangleRev:
|
2007-06-09 09:03:43 +08:00
|
|
|
case ICTriangleFalse:
|
2007-06-10 08:19:17 +08:00
|
|
|
case ICTriangleFRev: {
|
2007-06-16 17:34:52 +08:00
|
|
|
bool isFalse = Kind == ICTriangleFalse;
|
|
|
|
bool isRev = (Kind == ICTriangleRev || Kind == ICTriangleFRev);
|
2007-06-13 07:54:05 +08:00
|
|
|
if (DisableTriangle && !isFalse && !isRev) break;
|
|
|
|
if (DisableTriangleR && !isFalse && isRev) break;
|
|
|
|
if (DisableTriangleF && isFalse && !isRev) break;
|
|
|
|
if (DisableTriangleFR && isFalse && isRev) break;
|
2010-01-05 06:02:01 +08:00
|
|
|
DEBUG(dbgs() << "Ifcvt (Triangle");
|
2007-06-09 09:03:43 +08:00
|
|
|
if (isFalse)
|
2010-01-05 06:02:01 +08:00
|
|
|
DEBUG(dbgs() << " false");
|
2007-06-13 07:54:05 +08:00
|
|
|
if (isRev)
|
2010-01-05 06:02:01 +08:00
|
|
|
DEBUG(dbgs() << " rev");
|
|
|
|
DEBUG(dbgs() << "): BB#" << BBI.BB->getNumber() << " (T:"
|
2009-08-23 04:11:17 +08:00
|
|
|
<< BBI.TrueBB->getNumber() << ",F:"
|
|
|
|
<< BBI.FalseBB->getNumber() << ") ");
|
2007-06-16 17:34:52 +08:00
|
|
|
RetVal = IfConvertTriangle(BBI, Kind);
|
2010-01-05 06:02:01 +08:00
|
|
|
DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
|
2007-06-09 09:03:43 +08:00
|
|
|
if (RetVal) {
|
2007-06-13 07:54:05 +08:00
|
|
|
if (isFalse) {
|
2010-06-22 23:08:57 +08:00
|
|
|
if (isRev) ++NumTriangleFRev;
|
|
|
|
else ++NumTriangleFalse;
|
2007-06-13 07:54:05 +08:00
|
|
|
} else {
|
2010-06-22 23:08:57 +08:00
|
|
|
if (isRev) ++NumTriangleRev;
|
|
|
|
else ++NumTriangle;
|
2007-06-13 07:54:05 +08:00
|
|
|
}
|
2007-06-09 09:03:43 +08:00
|
|
|
}
|
2007-05-23 15:23:16 +08:00
|
|
|
break;
|
2007-06-10 08:19:17 +08:00
|
|
|
}
|
2007-06-16 17:34:52 +08:00
|
|
|
case ICDiamond: {
|
2007-06-09 03:10:51 +08:00
|
|
|
if (DisableDiamond) break;
|
2010-01-05 06:02:01 +08:00
|
|
|
DEBUG(dbgs() << "Ifcvt (Diamond): BB#" << BBI.BB->getNumber() << " (T:"
|
2009-08-23 04:11:17 +08:00
|
|
|
<< BBI.TrueBB->getNumber() << ",F:"
|
|
|
|
<< BBI.FalseBB->getNumber() << ") ");
|
2008-11-04 21:02:59 +08:00
|
|
|
RetVal = IfConvertDiamond(BBI, Kind, NumDups, NumDups2);
|
2010-01-05 06:02:01 +08:00
|
|
|
DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
|
2010-06-22 23:08:57 +08:00
|
|
|
if (RetVal) ++NumDiamonds;
|
2007-05-23 15:23:16 +08:00
|
|
|
break;
|
|
|
|
}
|
2007-06-16 17:34:52 +08:00
|
|
|
}
|
|
|
|
|
2007-06-04 14:47:22 +08:00
|
|
|
Change |= RetVal;
|
2007-06-09 03:10:51 +08:00
|
|
|
|
2007-06-15 15:36:12 +08:00
|
|
|
NumIfCvts = NumSimple + NumSimpleFalse + NumTriangle + NumTriangleRev +
|
|
|
|
NumTriangleFalse + NumTriangleFRev + NumDiamonds;
|
|
|
|
if (IfCvtLimit != -1 && (int)NumIfCvts >= IfCvtLimit)
|
2007-06-09 03:10:51 +08:00
|
|
|
break;
|
2007-05-16 10:00:57 +08:00
|
|
|
}
|
2007-05-23 15:23:16 +08:00
|
|
|
|
|
|
|
if (!Change)
|
|
|
|
break;
|
2007-06-04 14:47:22 +08:00
|
|
|
MadeChange |= Change;
|
2007-05-16 10:00:57 +08:00
|
|
|
}
|
2007-05-18 09:55:58 +08:00
|
|
|
|
2007-06-16 17:34:52 +08:00
|
|
|
Tokens.clear();
|
2007-05-18 09:55:58 +08:00
|
|
|
BBAnalysis.clear();
|
|
|
|
|
2010-06-19 06:17:13 +08:00
|
|
|
if (MadeChange && IfCvtBranchFold) {
|
2016-06-09 23:24:29 +08:00
|
|
|
BranchFolder BF(false, false, MBFI, *MBPI);
|
2014-08-05 10:39:49 +08:00
|
|
|
BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(),
|
2009-09-04 15:47:40 +08:00
|
|
|
getAnalysisIfAvailable<MachineModuleInfo>());
|
|
|
|
}
|
|
|
|
|
2010-06-19 07:09:54 +08:00
|
|
|
MadeChange |= BFChange;
|
2007-05-16 10:00:57 +08:00
|
|
|
return MadeChange;
|
|
|
|
}
|
|
|
|
|
2007-06-16 17:34:52 +08:00
|
|
|
/// findFalseBlock - BB has a fallthrough. Find its 'false' successor given
|
|
|
|
/// its 'true' successor.
|
2007-05-16 10:00:57 +08:00
|
|
|
static MachineBasicBlock *findFalseBlock(MachineBasicBlock *BB,
|
2007-05-18 08:20:58 +08:00
|
|
|
MachineBasicBlock *TrueBB) {
|
2007-05-16 10:00:57 +08:00
|
|
|
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
|
|
|
|
E = BB->succ_end(); SI != E; ++SI) {
|
|
|
|
MachineBasicBlock *SuccBB = *SI;
|
2007-05-18 08:20:58 +08:00
|
|
|
if (SuccBB != TrueBB)
|
2007-05-16 10:00:57 +08:00
|
|
|
return SuccBB;
|
|
|
|
}
|
2014-04-14 08:51:57 +08:00
|
|
|
return nullptr;
|
2007-05-16 10:00:57 +08:00
|
|
|
}
|
|
|
|
|
2007-06-16 17:34:52 +08:00
|
|
|
/// ReverseBranchCondition - Reverse the condition of the end of the block
|
2009-05-14 07:25:24 +08:00
|
|
|
/// branch. Swap block's 'true' and 'false' successors.
|
2016-07-28 04:19:31 +08:00
|
|
|
bool IfConverter::ReverseBranchCondition(BBInfo &BBI) const {
|
2010-06-18 06:43:56 +08:00
|
|
|
DebugLoc dl; // FIXME: this is nowhere
|
2007-06-04 14:47:22 +08:00
|
|
|
if (!TII->ReverseBranchCondition(BBI.BrCond)) {
|
|
|
|
TII->RemoveBranch(*BBI.BB);
|
2010-06-18 06:43:56 +08:00
|
|
|
TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
|
2007-06-04 14:47:22 +08:00
|
|
|
std::swap(BBI.TrueBB, BBI.FalseBB);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2007-06-09 09:03:43 +08:00
|
|
|
/// getNextBlock - Returns the next block in the function blocks ordering. If
|
|
|
|
/// it is the end, returns NULL.
|
|
|
|
static inline MachineBasicBlock *getNextBlock(MachineBasicBlock *BB) {
|
2015-10-10 03:13:58 +08:00
|
|
|
MachineFunction::iterator I = BB->getIterator();
|
2007-06-09 09:03:43 +08:00
|
|
|
MachineFunction::iterator E = BB->getParent()->end();
|
|
|
|
if (++I == E)
|
2014-04-14 08:51:57 +08:00
|
|
|
return nullptr;
|
2015-10-10 03:13:58 +08:00
|
|
|
return &*I;
|
2007-06-09 09:03:43 +08:00
|
|
|
}
|
|
|
|
|
2007-06-08 17:36:04 +08:00
|
|
|
/// ValidSimple - Returns true if the 'true' block (along with its
|
2007-06-16 17:34:52 +08:00
|
|
|
/// predecessor) forms a valid simple shape for ifcvt. It also returns the
|
|
|
|
/// number of instructions that the ifcvt would need to duplicate if performed
|
|
|
|
/// in Dups.
|
2010-09-29 04:42:15 +08:00
|
|
|
bool IfConverter::ValidSimple(BBInfo &TrueBBI, unsigned &Dups,
|
2015-09-11 07:10:42 +08:00
|
|
|
BranchProbability Prediction) const {
|
2007-06-16 17:34:52 +08:00
|
|
|
Dups = 0;
|
2007-06-18 16:37:25 +08:00
|
|
|
if (TrueBBI.IsBeingAnalyzed || TrueBBI.IsDone)
|
2007-06-12 06:26:22 +08:00
|
|
|
return false;
|
|
|
|
|
2007-06-20 05:45:13 +08:00
|
|
|
if (TrueBBI.IsBrAnalyzable)
|
|
|
|
return false;
|
|
|
|
|
2007-06-16 05:18:05 +08:00
|
|
|
if (TrueBBI.BB->pred_size() > 1) {
|
|
|
|
if (TrueBBI.CannotBeCopied ||
|
2010-09-29 04:42:15 +08:00
|
|
|
!TII->isProfitableToDupForIfCvt(*TrueBBI.BB, TrueBBI.NonPredSize,
|
2011-07-10 10:58:07 +08:00
|
|
|
Prediction))
|
2007-06-15 15:36:12 +08:00
|
|
|
return false;
|
2007-06-16 17:34:52 +08:00
|
|
|
Dups = TrueBBI.NonPredSize;
|
2007-06-15 15:36:12 +08:00
|
|
|
}
|
|
|
|
|
2007-06-20 05:45:13 +08:00
|
|
|
return true;
|
2007-06-06 18:16:17 +08:00
|
|
|
}
|
|
|
|
|
2007-06-08 17:36:04 +08:00
|
|
|
/// ValidTriangle - Returns true if the 'true' and 'false' blocks (along
|
2007-06-07 10:12:15 +08:00
|
|
|
/// with their common predecessor) forms a valid triangle shape for ifcvt.
|
2007-06-16 17:34:52 +08:00
|
|
|
/// If 'FalseBranch' is true, it checks if 'true' block's false branch
|
2010-06-16 06:18:54 +08:00
|
|
|
/// branches to the 'false' block rather than the other way around. It also
|
2007-06-16 17:34:52 +08:00
|
|
|
/// returns the number of instructions that the ifcvt would need to duplicate
|
|
|
|
/// if performed in 'Dups'.
|
2007-06-08 17:36:04 +08:00
|
|
|
bool IfConverter::ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI,
|
2010-10-02 06:45:50 +08:00
|
|
|
bool FalseBranch, unsigned &Dups,
|
2015-09-11 07:10:42 +08:00
|
|
|
BranchProbability Prediction) const {
|
2007-06-16 17:34:52 +08:00
|
|
|
Dups = 0;
|
2007-06-18 16:37:25 +08:00
|
|
|
if (TrueBBI.IsBeingAnalyzed || TrueBBI.IsDone)
|
2007-06-12 06:26:22 +08:00
|
|
|
return false;
|
|
|
|
|
2007-06-16 05:18:05 +08:00
|
|
|
if (TrueBBI.BB->pred_size() > 1) {
|
|
|
|
if (TrueBBI.CannotBeCopied)
|
|
|
|
return false;
|
|
|
|
|
2007-06-15 15:36:12 +08:00
|
|
|
unsigned Size = TrueBBI.NonPredSize;
|
2007-06-16 17:34:52 +08:00
|
|
|
if (TrueBBI.IsBrAnalyzable) {
|
2008-01-29 21:02:09 +08:00
|
|
|
if (TrueBBI.TrueBB && TrueBBI.BrCond.empty())
|
2009-05-14 07:25:24 +08:00
|
|
|
// Ends with an unconditional branch. It will be removed.
|
2007-06-16 17:34:52 +08:00
|
|
|
--Size;
|
|
|
|
else {
|
|
|
|
MachineBasicBlock *FExit = FalseBranch
|
|
|
|
? TrueBBI.TrueBB : TrueBBI.FalseBB;
|
|
|
|
if (FExit)
|
|
|
|
// Require a conditional branch
|
|
|
|
++Size;
|
|
|
|
}
|
|
|
|
}
|
2011-07-10 10:58:07 +08:00
|
|
|
if (!TII->isProfitableToDupForIfCvt(*TrueBBI.BB, Size, Prediction))
|
2007-06-15 15:36:12 +08:00
|
|
|
return false;
|
2007-06-16 17:34:52 +08:00
|
|
|
Dups = Size;
|
2007-06-15 15:36:12 +08:00
|
|
|
}
|
2007-06-07 10:12:15 +08:00
|
|
|
|
2007-06-08 17:36:04 +08:00
|
|
|
MachineBasicBlock *TExit = FalseBranch ? TrueBBI.FalseBB : TrueBBI.TrueBB;
|
|
|
|
if (!TExit && blockAlwaysFallThrough(TrueBBI)) {
|
2015-10-10 03:13:58 +08:00
|
|
|
MachineFunction::iterator I = TrueBBI.BB->getIterator();
|
2007-06-07 10:12:15 +08:00
|
|
|
if (++I == TrueBBI.BB->getParent()->end())
|
|
|
|
return false;
|
2015-10-10 03:13:58 +08:00
|
|
|
TExit = &*I;
|
2007-06-07 10:12:15 +08:00
|
|
|
}
|
2007-06-08 17:36:04 +08:00
|
|
|
return TExit && TExit == FalseBBI.BB;
|
2007-06-07 10:12:15 +08:00
|
|
|
}
|
|
|
|
|
2016-07-28 04:19:33 +08:00
|
|
|
static void countDuplicatedInstructions(
|
|
|
|
MachineBasicBlock::iterator &TIB,
|
|
|
|
MachineBasicBlock::iterator &FIB,
|
|
|
|
MachineBasicBlock::iterator &TIE,
|
|
|
|
MachineBasicBlock::iterator &FIE,
|
|
|
|
unsigned &Dups1, unsigned &Dups2,
|
|
|
|
MachineBasicBlock &TBB, MachineBasicBlock &FBB,
|
|
|
|
bool SkipConditionalBranches) {
|
2007-06-18 16:37:25 +08:00
|
|
|
|
2010-10-26 08:02:24 +08:00
|
|
|
while (TIB != TIE && FIB != FIE) {
|
2010-06-19 05:52:57 +08:00
|
|
|
// Skip dbg_value instructions. These do not count.
|
2010-10-26 08:02:24 +08:00
|
|
|
if (TIB->isDebugValue()) {
|
|
|
|
while (TIB != TIE && TIB->isDebugValue())
|
|
|
|
++TIB;
|
|
|
|
if (TIB == TIE)
|
2010-06-19 05:52:57 +08:00
|
|
|
break;
|
|
|
|
}
|
2010-10-26 08:02:24 +08:00
|
|
|
if (FIB->isDebugValue()) {
|
|
|
|
while (FIB != FIE && FIB->isDebugValue())
|
|
|
|
++FIB;
|
|
|
|
if (FIB == FIE)
|
2010-06-19 05:52:57 +08:00
|
|
|
break;
|
|
|
|
}
|
2016-02-28 04:01:33 +08:00
|
|
|
if (!TIB->isIdenticalTo(*FIB))
|
2007-06-18 16:37:25 +08:00
|
|
|
break;
|
|
|
|
++Dups1;
|
2010-10-26 08:02:24 +08:00
|
|
|
++TIB;
|
|
|
|
++FIB;
|
2007-06-18 16:37:25 +08:00
|
|
|
}
|
|
|
|
|
2010-10-26 08:02:24 +08:00
|
|
|
// Now, in preparation for counting duplicate instructions at the ends of the
|
|
|
|
// blocks, move the end iterators up past any branch instructions.
|
2016-01-20 21:14:52 +08:00
|
|
|
// If both blocks are returning don't skip the branches, since they will
|
|
|
|
// likely be both identical return instructions. In such cases the return
|
|
|
|
// can be left unpredicated.
|
|
|
|
// Check for already containing all of the block.
|
|
|
|
if (TIB == TIE || FIB == FIE)
|
2016-07-28 04:19:33 +08:00
|
|
|
return;
|
2016-01-20 21:14:52 +08:00
|
|
|
--TIE;
|
|
|
|
--FIE;
|
2016-07-28 04:19:33 +08:00
|
|
|
if (!TBB.succ_empty() || !FBB.succ_empty()) {
|
|
|
|
if (SkipConditionalBranches) {
|
|
|
|
while (TIE != TIB && TIE->isBranch())
|
|
|
|
--TIE;
|
|
|
|
while (FIE != FIB && FIE->isBranch())
|
|
|
|
--FIE;
|
|
|
|
} else {
|
|
|
|
while (TIE != TIB && TIE->isUnconditionalBranch())
|
|
|
|
--TIE;
|
|
|
|
while (FIE != FIB && FIE->isUnconditionalBranch())
|
|
|
|
--FIE;
|
|
|
|
}
|
2010-10-26 08:02:24 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// If Dups1 includes all of a block, then don't count duplicate
|
|
|
|
// instructions at the end of the blocks.
|
|
|
|
if (TIB == TIE || FIB == FIE)
|
2016-07-28 04:19:33 +08:00
|
|
|
return;
|
2010-10-26 08:02:24 +08:00
|
|
|
|
|
|
|
// Count duplicate instructions at the ends of the blocks.
|
|
|
|
while (TIE != TIB && FIE != FIB) {
|
2010-06-19 05:52:57 +08:00
|
|
|
// Skip dbg_value instructions. These do not count.
|
2010-10-26 08:02:24 +08:00
|
|
|
if (TIE->isDebugValue()) {
|
|
|
|
while (TIE != TIB && TIE->isDebugValue())
|
|
|
|
--TIE;
|
|
|
|
if (TIE == TIB)
|
2010-06-19 05:52:57 +08:00
|
|
|
break;
|
|
|
|
}
|
2010-10-26 08:02:24 +08:00
|
|
|
if (FIE->isDebugValue()) {
|
|
|
|
while (FIE != FIB && FIE->isDebugValue())
|
|
|
|
--FIE;
|
|
|
|
if (FIE == FIB)
|
2010-06-19 05:52:57 +08:00
|
|
|
break;
|
|
|
|
}
|
2016-02-28 04:01:33 +08:00
|
|
|
if (!TIE->isIdenticalTo(*FIE))
|
2007-06-18 16:37:25 +08:00
|
|
|
break;
|
2016-07-28 04:19:33 +08:00
|
|
|
// If we are trying to make sure the conditional branches are the same, we
|
|
|
|
// still don't want to count them.
|
|
|
|
if (SkipConditionalBranches || !TIE->isBranch())
|
|
|
|
++Dups2;
|
2010-10-26 08:02:24 +08:00
|
|
|
--TIE;
|
|
|
|
--FIE;
|
2007-06-18 16:37:25 +08:00
|
|
|
}
|
2016-07-28 04:19:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// ValidDiamond - Returns true if the 'true' and 'false' blocks (along
|
|
|
|
/// with their common predecessor) forms a valid diamond shape for ifcvt.
|
|
|
|
bool IfConverter::ValidDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,
|
|
|
|
unsigned &Dups1, unsigned &Dups2) const {
|
|
|
|
Dups1 = Dups2 = 0;
|
|
|
|
if (TrueBBI.IsBeingAnalyzed || TrueBBI.IsDone ||
|
|
|
|
FalseBBI.IsBeingAnalyzed || FalseBBI.IsDone)
|
|
|
|
return false;
|
2007-06-18 16:37:25 +08:00
|
|
|
|
2016-07-28 04:19:33 +08:00
|
|
|
MachineBasicBlock *TT = TrueBBI.TrueBB;
|
|
|
|
MachineBasicBlock *FT = FalseBBI.TrueBB;
|
|
|
|
|
|
|
|
if (!TT && blockAlwaysFallThrough(TrueBBI))
|
|
|
|
TT = getNextBlock(TrueBBI.BB);
|
|
|
|
if (!FT && blockAlwaysFallThrough(FalseBBI))
|
|
|
|
FT = getNextBlock(FalseBBI.BB);
|
|
|
|
if (TT != FT)
|
|
|
|
return false;
|
|
|
|
if (!TT && (TrueBBI.IsBrAnalyzable || FalseBBI.IsBrAnalyzable))
|
|
|
|
return false;
|
|
|
|
if (TrueBBI.BB->pred_size() > 1 || FalseBBI.BB->pred_size() > 1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// FIXME: Allow true block to have an early exit?
|
|
|
|
if (TrueBBI.FalseBB || FalseBBI.FalseBB ||
|
|
|
|
(TrueBBI.ClobbersPred && FalseBBI.ClobbersPred))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Count duplicate instructions at the beginning and end of the true and
|
|
|
|
// false blocks.
|
|
|
|
MachineBasicBlock::iterator TIB = TrueBBI.BB->begin();
|
|
|
|
MachineBasicBlock::iterator FIB = FalseBBI.BB->begin();
|
|
|
|
MachineBasicBlock::iterator TIE = TrueBBI.BB->end();
|
|
|
|
MachineBasicBlock::iterator FIE = FalseBBI.BB->end();
|
|
|
|
countDuplicatedInstructions(TIB, FIB, TIE, FIE, Dups1, Dups2,
|
|
|
|
*TrueBBI.BB, *FalseBBI.BB,
|
|
|
|
/* SkipConditionalBranches */ true);
|
2007-06-18 16:37:25 +08:00
|
|
|
return true;
|
2007-06-07 10:12:15 +08:00
|
|
|
}
|
|
|
|
|
2007-06-12 06:26:22 +08:00
|
|
|
/// ScanInstructions - Scan all the instructions in the block to determine if
|
|
|
|
/// the block is predicable. In most cases, that means all the instructions
|
2008-01-07 09:56:04 +08:00
|
|
|
/// in the block are isPredicable(). Also checks if the block contains any
|
2007-06-12 06:26:22 +08:00
|
|
|
/// instruction which can clobber a predicate (e.g. condition code register).
|
|
|
|
/// If so, the block is not predicable unless it's the last instruction.
|
|
|
|
void IfConverter::ScanInstructions(BBInfo &BBI) {
|
|
|
|
if (BBI.IsDone)
|
|
|
|
return;
|
|
|
|
|
2012-06-09 05:53:50 +08:00
|
|
|
bool AlreadyPredicated = !BBI.Predicate.empty();
|
2007-06-12 06:26:22 +08:00
|
|
|
// First analyze the end of BB branches.
|
2014-04-14 08:51:57 +08:00
|
|
|
BBI.TrueBB = BBI.FalseBB = nullptr;
|
2007-06-12 06:26:22 +08:00
|
|
|
BBI.BrCond.clear();
|
|
|
|
BBI.IsBrAnalyzable =
|
2016-07-15 22:41:04 +08:00
|
|
|
!TII->analyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond);
|
2014-04-14 08:51:57 +08:00
|
|
|
BBI.HasFallThrough = BBI.IsBrAnalyzable && BBI.FalseBB == nullptr;
|
2007-06-12 06:26:22 +08:00
|
|
|
|
|
|
|
if (BBI.BrCond.size()) {
|
|
|
|
// No false branch. This BB must end with a conditional branch and a
|
|
|
|
// fallthrough.
|
|
|
|
if (!BBI.FalseBB)
|
2010-06-16 06:18:54 +08:00
|
|
|
BBI.FalseBB = findFalseBlock(BBI.BB, BBI.TrueBB);
|
2009-06-16 05:24:34 +08:00
|
|
|
if (!BBI.FalseBB) {
|
|
|
|
// Malformed bcc? True and false blocks are the same?
|
|
|
|
BBI.IsUnpredicable = true;
|
|
|
|
return;
|
|
|
|
}
|
2007-06-12 06:26:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Then scan all the instructions.
|
|
|
|
BBI.NonPredSize = 0;
|
2010-10-26 08:02:21 +08:00
|
|
|
BBI.ExtraCost = 0;
|
2010-11-03 08:45:17 +08:00
|
|
|
BBI.ExtraCost2 = 0;
|
2007-06-12 06:26:22 +08:00
|
|
|
BBI.ClobbersPred = false;
|
2016-02-23 10:46:52 +08:00
|
|
|
for (auto &MI : *BBI.BB) {
|
|
|
|
if (MI.isDebugValue())
|
2010-06-05 07:01:26 +08:00
|
|
|
continue;
|
|
|
|
|
2016-04-15 09:38:41 +08:00
|
|
|
// It's unsafe to duplicate convergent instructions in this context, so set
|
|
|
|
// BBI.CannotBeCopied to true if MI is convergent. To see why, consider the
|
|
|
|
// following CFG, which is subject to our "simple" transformation.
|
|
|
|
//
|
|
|
|
// BB0 // if (c1) goto BB1; else goto BB2;
|
|
|
|
// / \
|
|
|
|
// BB1 |
|
|
|
|
// | BB2 // if (c2) goto TBB; else goto FBB;
|
|
|
|
// | / |
|
|
|
|
// | / |
|
|
|
|
// TBB |
|
|
|
|
// | |
|
|
|
|
// | FBB
|
|
|
|
// |
|
|
|
|
// exit
|
|
|
|
//
|
|
|
|
// Suppose we want to move TBB's contents up into BB1 and BB2 (in BB1 they'd
|
|
|
|
// be unconditional, and in BB2, they'd be predicated upon c2), and suppose
|
|
|
|
// TBB contains a convergent instruction. This is safe iff doing so does
|
|
|
|
// not add a control-flow dependency to the convergent instruction -- i.e.,
|
|
|
|
// it's safe iff the set of control flows that leads us to the convergent
|
|
|
|
// instruction does not get smaller after the transformation.
|
|
|
|
//
|
|
|
|
// Originally we executed TBB if c1 || c2. After the transformation, there
|
|
|
|
// are two copies of TBB's instructions. We get to the first if c1, and we
|
|
|
|
// get to the second if !c1 && c2.
|
|
|
|
//
|
|
|
|
// There are clearly fewer ways to satisfy the condition "c1" than
|
|
|
|
// "c1 || c2". Since we've shrunk the set of control flows which lead to
|
|
|
|
// our convergent instruction, the transformation is unsafe.
|
|
|
|
if (MI.isNotDuplicable() || MI.isConvergent())
|
2007-06-16 05:18:05 +08:00
|
|
|
BBI.CannotBeCopied = true;
|
|
|
|
|
2016-02-23 10:46:52 +08:00
|
|
|
bool isPredicated = TII->isPredicated(MI);
|
|
|
|
bool isCondBr = BBI.IsBrAnalyzable && MI.isConditionalBranch();
|
2007-06-12 06:26:22 +08:00
|
|
|
|
2013-09-09 22:21:49 +08:00
|
|
|
// A conditional branch is not predicable, but it may be eliminated.
|
|
|
|
if (isCondBr)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!isPredicated) {
|
|
|
|
BBI.NonPredSize++;
|
2016-02-23 10:46:52 +08:00
|
|
|
unsigned ExtraPredCost = TII->getPredicationCost(MI);
|
|
|
|
unsigned NumCycles = SchedModel.computeInstrLatency(&MI, false);
|
2013-09-09 22:21:49 +08:00
|
|
|
if (NumCycles > 1)
|
|
|
|
BBI.ExtraCost += NumCycles-1;
|
|
|
|
BBI.ExtraCost2 += ExtraPredCost;
|
|
|
|
} else if (!AlreadyPredicated) {
|
|
|
|
// FIXME: This instruction is already predicated before the
|
|
|
|
// if-conversion pass. It's probably something like a conditional move.
|
|
|
|
// Mark this block unpredicable for now.
|
|
|
|
BBI.IsUnpredicable = true;
|
|
|
|
return;
|
2007-07-07 07:24:39 +08:00
|
|
|
}
|
2007-06-12 06:26:22 +08:00
|
|
|
|
|
|
|
if (BBI.ClobbersPred && !isPredicated) {
|
|
|
|
// Predicate modification instruction should end the block (except for
|
|
|
|
// already predicated instructions and end of block branches).
|
|
|
|
// Predicate may have been modified, the subsequent (currently)
|
2007-07-07 07:24:39 +08:00
|
|
|
// unpredicated instructions cannot be correctly predicated.
|
2007-06-12 06:26:22 +08:00
|
|
|
BBI.IsUnpredicable = true;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2007-07-11 01:50:43 +08:00
|
|
|
// FIXME: Make use of PredDefs? e.g. ADDC, SUBC sets predicates but are
|
|
|
|
// still potentially predicable.
|
|
|
|
std::vector<MachineOperand> PredDefs;
|
2016-02-23 10:46:52 +08:00
|
|
|
if (TII->DefinesPredicate(MI, PredDefs))
|
2007-06-12 06:26:22 +08:00
|
|
|
BBI.ClobbersPred = true;
|
|
|
|
|
2016-02-23 10:46:52 +08:00
|
|
|
if (!TII->isPredicable(MI)) {
|
2007-06-12 06:26:22 +08:00
|
|
|
BBI.IsUnpredicable = true;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// FeasibilityAnalysis - Determine if the block is a suitable candidate to be
|
|
|
|
/// predicated by the specified predicate.
|
|
|
|
bool IfConverter::FeasibilityAnalysis(BBInfo &BBI,
|
2008-08-15 06:49:33 +08:00
|
|
|
SmallVectorImpl<MachineOperand> &Pred,
|
2007-06-12 06:26:22 +08:00
|
|
|
bool isTriangle, bool RevBranch) {
|
2007-06-16 17:34:52 +08:00
|
|
|
// If the block is dead or unpredicable, then it cannot be predicated.
|
|
|
|
if (BBI.IsDone || BBI.IsUnpredicable)
|
2007-06-12 06:26:22 +08:00
|
|
|
return false;
|
|
|
|
|
[CodeGen][IfCvt] Don't re-ifcvt blocks with unanalyzable terminators.
If we couldn't analyze its terminator (i.e., it's an indirectbr, or some
other weirdness), we can't safely re-if-convert a predicated block,
because we can't tell whether the predicated terminator can
fallthrough (it does).
Currently, we would completely ignore the fallthrough successor. In
the added testcase, this means we used to generate:
...
@ %entry:
cmp r5, #21
ittt ne
@ %cc1f:
cmpne r7, #42
@ %cc2t:
strne.w r5, [r8]
movne pc, r10
@ %cc1t:
...
Whereas the successor of %cc1f was originally %bb1.
With the fix, we get the correct:
...
@ %entry:
cmp r5, #21
itt eq
@ %cc1t:
streq.w r5, [r11]
moveq pc, r0
@ %cc1f:
cmp r7, #42
itt ne
@ %cc2t:
strne.w r5, [r8]
movne pc, r10
@ %bb1:
...
rdar://20192768
Differential Revision: http://reviews.llvm.org/D8509
llvm-svn: 232872
2015-03-21 09:23:15 +08:00
|
|
|
// If it is already predicated but we couldn't analyze its terminator, the
|
|
|
|
// latter might fallthrough, but we can't determine where to.
|
|
|
|
// Conservatively avoid if-converting again.
|
|
|
|
if (BBI.Predicate.size() && !BBI.IsBrAnalyzable)
|
|
|
|
return false;
|
|
|
|
|
2013-07-25 04:20:37 +08:00
|
|
|
// If it is already predicated, check if the new predicate subsumes
|
|
|
|
// its predicate.
|
|
|
|
if (BBI.Predicate.size() && !TII->SubsumesPredicate(Pred, BBI.Predicate))
|
2007-06-12 06:26:22 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
if (BBI.BrCond.size()) {
|
|
|
|
if (!isTriangle)
|
|
|
|
return false;
|
|
|
|
|
2009-05-14 07:25:24 +08:00
|
|
|
// Test predicate subsumption.
|
2008-08-15 06:49:33 +08:00
|
|
|
SmallVector<MachineOperand, 4> RevPred(Pred.begin(), Pred.end());
|
|
|
|
SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
|
2007-06-12 06:26:22 +08:00
|
|
|
if (RevBranch) {
|
|
|
|
if (TII->ReverseBranchCondition(Cond))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (TII->ReverseBranchCondition(RevPred) ||
|
|
|
|
!TII->SubsumesPredicate(Cond, RevPred))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2007-06-08 17:36:04 +08:00
|
|
|
/// AnalyzeBlock - Analyze the structure of the sub-CFG starting from
|
2007-05-19 02:14:37 +08:00
|
|
|
/// the specified block. Record its successors and whether it looks like an
|
|
|
|
/// if-conversion candidate.
|
2016-02-23 01:51:28 +08:00
|
|
|
void IfConverter::AnalyzeBlock(
|
|
|
|
MachineBasicBlock *MBB, std::vector<std::unique_ptr<IfcvtToken>> &Tokens) {
|
2015-06-25 04:34:35 +08:00
|
|
|
struct BBState {
|
|
|
|
BBState(MachineBasicBlock *BB) : MBB(BB), SuccsAnalyzed(false) {}
|
|
|
|
MachineBasicBlock *MBB;
|
|
|
|
|
|
|
|
/// This flag is true if MBB's successors have been analyzed.
|
|
|
|
bool SuccsAnalyzed;
|
|
|
|
};
|
2007-05-16 10:00:57 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
// Push MBB to the stack.
|
|
|
|
SmallVector<BBState, 16> BBStack(1, MBB);
|
2007-05-18 08:20:58 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
while (!BBStack.empty()) {
|
|
|
|
BBState &State = BBStack.back();
|
|
|
|
MachineBasicBlock *BB = State.MBB;
|
|
|
|
BBInfo &BBI = BBAnalysis[BB->getNumber()];
|
2007-05-25 08:59:01 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
if (!State.SuccsAnalyzed) {
|
|
|
|
if (BBI.IsAnalyzed || BBI.IsBeingAnalyzed) {
|
|
|
|
BBStack.pop_back();
|
|
|
|
continue;
|
|
|
|
}
|
2007-06-12 06:26:22 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
BBI.BB = BB;
|
|
|
|
BBI.IsBeingAnalyzed = true;
|
2007-05-17 05:54:37 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
ScanInstructions(BBI);
|
2007-05-18 08:20:58 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
// Unanalyzable or ends with fallthrough or unconditional branch, or if is
|
|
|
|
// not considered for ifcvt anymore.
|
|
|
|
if (!BBI.IsBrAnalyzable || BBI.BrCond.empty() || BBI.IsDone) {
|
|
|
|
BBI.IsBeingAnalyzed = false;
|
|
|
|
BBI.IsAnalyzed = true;
|
|
|
|
BBStack.pop_back();
|
|
|
|
continue;
|
|
|
|
}
|
2009-06-16 05:24:34 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
// Do not ifcvt if either path is a back edge to the entry block.
|
|
|
|
if (BBI.TrueBB == BB || BBI.FalseBB == BB) {
|
|
|
|
BBI.IsBeingAnalyzed = false;
|
|
|
|
BBI.IsAnalyzed = true;
|
|
|
|
BBStack.pop_back();
|
|
|
|
continue;
|
|
|
|
}
|
2007-06-06 18:16:17 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
// Do not ifcvt if true and false fallthrough blocks are the same.
|
|
|
|
if (!BBI.FalseBB) {
|
|
|
|
BBI.IsBeingAnalyzed = false;
|
|
|
|
BBI.IsAnalyzed = true;
|
|
|
|
BBStack.pop_back();
|
|
|
|
continue;
|
|
|
|
}
|
2007-06-06 18:16:17 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
// Push the False and True blocks to the stack.
|
|
|
|
State.SuccsAnalyzed = true;
|
|
|
|
BBStack.push_back(BBI.FalseBB);
|
|
|
|
BBStack.push_back(BBI.TrueBB);
|
|
|
|
continue;
|
|
|
|
}
|
2007-06-08 17:36:04 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
BBInfo &TrueBBI = BBAnalysis[BBI.TrueBB->getNumber()];
|
|
|
|
BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];
|
2011-08-04 06:34:43 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
if (TrueBBI.IsDone && FalseBBI.IsDone) {
|
|
|
|
BBI.IsBeingAnalyzed = false;
|
|
|
|
BBI.IsAnalyzed = true;
|
|
|
|
BBStack.pop_back();
|
|
|
|
continue;
|
|
|
|
}
|
2011-08-04 06:34:43 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
SmallVector<MachineOperand, 4>
|
|
|
|
RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
|
|
|
|
bool CanRevCond = !TII->ReverseBranchCondition(RevCond);
|
2007-06-16 17:34:52 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
unsigned Dups = 0;
|
|
|
|
unsigned Dups2 = 0;
|
|
|
|
bool TNeedSub = !TrueBBI.Predicate.empty();
|
|
|
|
bool FNeedSub = !FalseBBI.Predicate.empty();
|
|
|
|
bool Enqueued = false;
|
2010-06-16 06:18:54 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
BranchProbability Prediction = MBPI->getEdgeProbability(BB, TrueBBI.BB);
|
2007-06-16 17:34:52 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
if (CanRevCond && ValidDiamond(TrueBBI, FalseBBI, Dups, Dups2) &&
|
|
|
|
MeetIfcvtSizeLimit(*TrueBBI.BB, (TrueBBI.NonPredSize - (Dups + Dups2) +
|
|
|
|
TrueBBI.ExtraCost), TrueBBI.ExtraCost2,
|
|
|
|
*FalseBBI.BB, (FalseBBI.NonPredSize - (Dups + Dups2) +
|
|
|
|
FalseBBI.ExtraCost),FalseBBI.ExtraCost2,
|
|
|
|
Prediction) &&
|
|
|
|
FeasibilityAnalysis(TrueBBI, BBI.BrCond) &&
|
|
|
|
FeasibilityAnalysis(FalseBBI, RevCond)) {
|
|
|
|
// Diamond:
|
|
|
|
// EBB
|
|
|
|
// / \_
|
|
|
|
// | |
|
|
|
|
// TBB FBB
|
|
|
|
// \ /
|
|
|
|
// TailBB
|
|
|
|
// Note TailBB can be empty.
|
2016-02-23 01:51:28 +08:00
|
|
|
Tokens.push_back(llvm::make_unique<IfcvtToken>(
|
|
|
|
BBI, ICDiamond, TNeedSub | FNeedSub, Dups, Dups2));
|
2015-06-25 04:34:35 +08:00
|
|
|
Enqueued = true;
|
|
|
|
}
|
2007-06-16 17:34:52 +08:00
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
if (ValidTriangle(TrueBBI, FalseBBI, false, Dups, Prediction) &&
|
|
|
|
MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost,
|
|
|
|
TrueBBI.ExtraCost2, Prediction) &&
|
|
|
|
FeasibilityAnalysis(TrueBBI, BBI.BrCond, true)) {
|
|
|
|
// Triangle:
|
|
|
|
// EBB
|
|
|
|
// | \_
|
|
|
|
// | |
|
|
|
|
// | TBB
|
|
|
|
// | /
|
|
|
|
// FBB
|
2016-02-23 01:51:28 +08:00
|
|
|
Tokens.push_back(
|
|
|
|
llvm::make_unique<IfcvtToken>(BBI, ICTriangle, TNeedSub, Dups));
|
2007-06-16 17:34:52 +08:00
|
|
|
Enqueued = true;
|
|
|
|
}
|
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
if (ValidTriangle(TrueBBI, FalseBBI, true, Dups, Prediction) &&
|
|
|
|
MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost,
|
|
|
|
TrueBBI.ExtraCost2, Prediction) &&
|
|
|
|
FeasibilityAnalysis(TrueBBI, BBI.BrCond, true, true)) {
|
2016-02-23 01:51:28 +08:00
|
|
|
Tokens.push_back(
|
|
|
|
llvm::make_unique<IfcvtToken>(BBI, ICTriangleRev, TNeedSub, Dups));
|
2007-06-16 17:34:52 +08:00
|
|
|
Enqueued = true;
|
|
|
|
}
|
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
if (ValidSimple(TrueBBI, Dups, Prediction) &&
|
|
|
|
MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost,
|
|
|
|
TrueBBI.ExtraCost2, Prediction) &&
|
|
|
|
FeasibilityAnalysis(TrueBBI, BBI.BrCond)) {
|
|
|
|
// Simple (split, no rejoin):
|
|
|
|
// EBB
|
|
|
|
// | \_
|
|
|
|
// | |
|
|
|
|
// | TBB---> exit
|
|
|
|
// |
|
|
|
|
// FBB
|
2016-02-23 01:51:28 +08:00
|
|
|
Tokens.push_back(
|
|
|
|
llvm::make_unique<IfcvtToken>(BBI, ICSimple, TNeedSub, Dups));
|
2007-06-16 17:34:52 +08:00
|
|
|
Enqueued = true;
|
2007-06-04 14:47:22 +08:00
|
|
|
}
|
|
|
|
|
2015-06-25 04:34:35 +08:00
|
|
|
if (CanRevCond) {
|
|
|
|
// Try the other path...
|
|
|
|
if (ValidTriangle(FalseBBI, TrueBBI, false, Dups,
|
|
|
|
Prediction.getCompl()) &&
|
|
|
|
MeetIfcvtSizeLimit(*FalseBBI.BB,
|
|
|
|
FalseBBI.NonPredSize + FalseBBI.ExtraCost,
|
|
|
|
FalseBBI.ExtraCost2, Prediction.getCompl()) &&
|
|
|
|
FeasibilityAnalysis(FalseBBI, RevCond, true)) {
|
2016-02-23 01:51:28 +08:00
|
|
|
Tokens.push_back(llvm::make_unique<IfcvtToken>(BBI, ICTriangleFalse,
|
|
|
|
FNeedSub, Dups));
|
2015-06-25 04:34:35 +08:00
|
|
|
Enqueued = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ValidTriangle(FalseBBI, TrueBBI, true, Dups,
|
|
|
|
Prediction.getCompl()) &&
|
|
|
|
MeetIfcvtSizeLimit(*FalseBBI.BB,
|
|
|
|
FalseBBI.NonPredSize + FalseBBI.ExtraCost,
|
|
|
|
FalseBBI.ExtraCost2, Prediction.getCompl()) &&
|
|
|
|
FeasibilityAnalysis(FalseBBI, RevCond, true, true)) {
|
2016-02-23 01:51:28 +08:00
|
|
|
Tokens.push_back(
|
|
|
|
llvm::make_unique<IfcvtToken>(BBI, ICTriangleFRev, FNeedSub, Dups));
|
2015-06-25 04:34:35 +08:00
|
|
|
Enqueued = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ValidSimple(FalseBBI, Dups, Prediction.getCompl()) &&
|
|
|
|
MeetIfcvtSizeLimit(*FalseBBI.BB,
|
|
|
|
FalseBBI.NonPredSize + FalseBBI.ExtraCost,
|
|
|
|
FalseBBI.ExtraCost2, Prediction.getCompl()) &&
|
|
|
|
FeasibilityAnalysis(FalseBBI, RevCond)) {
|
2016-02-23 01:51:28 +08:00
|
|
|
Tokens.push_back(
|
|
|
|
llvm::make_unique<IfcvtToken>(BBI, ICSimpleFalse, FNeedSub, Dups));
|
2015-06-25 04:34:35 +08:00
|
|
|
Enqueued = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
BBI.IsEnqueued = Enqueued;
|
|
|
|
BBI.IsBeingAnalyzed = false;
|
|
|
|
BBI.IsAnalyzed = true;
|
|
|
|
BBStack.pop_back();
|
|
|
|
}
|
2007-05-19 02:14:37 +08:00
|
|
|
}
|
|
|
|
|
2007-05-31 03:49:19 +08:00
|
|
|
/// AnalyzeBlocks - Analyze all blocks and find entries for all if-conversion
|
2010-06-16 02:57:15 +08:00
|
|
|
/// candidates.
|
2016-02-23 01:51:28 +08:00
|
|
|
void IfConverter::AnalyzeBlocks(
|
|
|
|
MachineFunction &MF, std::vector<std::unique_ptr<IfcvtToken>> &Tokens) {
|
2015-10-10 03:13:58 +08:00
|
|
|
for (auto &BB : MF)
|
|
|
|
AnalyzeBlock(&BB, Tokens);
|
2007-05-31 03:49:19 +08:00
|
|
|
|
2007-06-01 08:12:12 +08:00
|
|
|
// Sort to favor more complex ifcvt scheme.
|
2007-06-16 17:34:52 +08:00
|
|
|
std::stable_sort(Tokens.begin(), Tokens.end(), IfcvtTokenCmp);
|
2007-05-16 10:00:57 +08:00
|
|
|
}
|
|
|
|
|
2007-06-09 06:01:07 +08:00
|
|
|
/// canFallThroughTo - Returns true either if ToBB is the next block after BB or
|
|
|
|
/// that all the intervening blocks are empty (given BB can fall through to its
|
|
|
|
/// next block).
|
|
|
|
static bool canFallThroughTo(MachineBasicBlock *BB, MachineBasicBlock *ToBB) {
|
2015-10-10 03:13:58 +08:00
|
|
|
MachineFunction::iterator PI = BB->getIterator();
|
2014-03-02 20:27:27 +08:00
|
|
|
MachineFunction::iterator I = std::next(PI);
|
2015-10-10 03:13:58 +08:00
|
|
|
MachineFunction::iterator TI = ToBB->getIterator();
|
2007-06-05 15:05:25 +08:00
|
|
|
MachineFunction::iterator E = BB->getParent()->end();
|
2010-06-16 15:35:02 +08:00
|
|
|
while (I != TI) {
|
|
|
|
// Check isSuccessor to avoid case where the next block is empty, but
|
|
|
|
// it's not a successor.
|
2015-10-10 03:13:58 +08:00
|
|
|
if (I == E || !I->empty() || !PI->isSuccessor(&*I))
|
2007-06-04 14:47:22 +08:00
|
|
|
return false;
|
2010-06-16 15:35:02 +08:00
|
|
|
PI = I++;
|
|
|
|
}
|
2007-06-04 14:47:22 +08:00
|
|
|
return true;
|
2007-05-22 06:22:58 +08:00
|
|
|
}
|
|
|
|
|
2007-06-18 16:37:25 +08:00
|
|
|
/// InvalidatePreds - Invalidate predecessor BB info so it would be re-analyzed
|
|
|
|
/// to determine if it can be if-converted. If predecessor is already enqueued,
|
|
|
|
/// dequeue it!
|
|
|
|
void IfConverter::InvalidatePreds(MachineBasicBlock *BB) {
|
2014-08-10 01:21:29 +08:00
|
|
|
for (const auto &Predecessor : BB->predecessors()) {
|
|
|
|
BBInfo &PBBI = BBAnalysis[Predecessor->getNumber()];
|
2007-06-15 07:34:09 +08:00
|
|
|
if (PBBI.IsDone || PBBI.BB == BB)
|
2007-06-15 07:13:19 +08:00
|
|
|
continue;
|
2007-06-15 07:34:09 +08:00
|
|
|
PBBI.IsAnalyzed = false;
|
|
|
|
PBBI.IsEnqueued = false;
|
2007-05-23 15:23:16 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-05-30 06:31:16 +08:00
|
|
|
/// InsertUncondBranch - Inserts an unconditional branch from BB to ToBB.
|
|
|
|
///
|
|
|
|
static void InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB,
|
|
|
|
const TargetInstrInfo *TII) {
|
2010-06-18 06:43:56 +08:00
|
|
|
DebugLoc dl; // FIXME: this is nowhere
|
2008-08-23 00:07:55 +08:00
|
|
|
SmallVector<MachineOperand, 0> NoCond;
|
2014-04-14 08:51:57 +08:00
|
|
|
TII->InsertBranch(*BB, ToBB, nullptr, NoCond, dl);
|
2007-05-30 06:31:16 +08:00
|
|
|
}
|
|
|
|
|
2007-06-09 06:01:07 +08:00
|
|
|
/// RemoveExtraEdges - Remove true / false edges if either / both are no longer
|
|
|
|
/// successors.
|
|
|
|
void IfConverter::RemoveExtraEdges(BBInfo &BBI) {
|
2014-04-14 08:51:57 +08:00
|
|
|
MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
|
2008-08-15 06:49:33 +08:00
|
|
|
SmallVector<MachineOperand, 4> Cond;
|
2016-07-15 22:41:04 +08:00
|
|
|
if (!TII->analyzeBranch(*BBI.BB, TBB, FBB, Cond))
|
2007-06-19 06:44:57 +08:00
|
|
|
BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
|
2007-06-09 06:01:07 +08:00
|
|
|
}
|
|
|
|
|
2013-10-12 03:04:37 +08:00
|
|
|
/// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all
|
2016-06-25 02:57:29 +08:00
|
|
|
/// values defined in MI which are not live/used by MI.
|
2016-02-23 10:46:52 +08:00
|
|
|
static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) {
|
2015-05-06 04:14:22 +08:00
|
|
|
SmallVector<std::pair<unsigned, const MachineOperand*>, 4> Clobbers;
|
2016-02-23 10:46:52 +08:00
|
|
|
Redefs.stepForward(MI, Clobbers);
|
2015-05-06 04:14:22 +08:00
|
|
|
|
|
|
|
// Now add the implicit uses for each of the clobbered values.
|
|
|
|
for (auto Reg : Clobbers) {
|
|
|
|
// FIXME: Const cast here is nasty, but better than making StepForward
|
|
|
|
// take a mutable instruction instead of const.
|
2015-05-07 06:51:04 +08:00
|
|
|
MachineOperand &Op = const_cast<MachineOperand&>(*Reg.second);
|
|
|
|
MachineInstr *OpMI = Op.getParent();
|
2015-05-06 04:14:22 +08:00
|
|
|
MachineInstrBuilder MIB(*OpMI->getParent()->getParent(), OpMI);
|
2015-05-06 06:09:41 +08:00
|
|
|
if (Op.isRegMask()) {
|
|
|
|
// First handle regmasks. They clobber any entries in the mask which
|
|
|
|
// means that we need a def for those registers.
|
2016-06-25 02:57:29 +08:00
|
|
|
MIB.addReg(Reg.first, RegState::Implicit | RegState::Undef);
|
2015-05-06 06:09:41 +08:00
|
|
|
|
|
|
|
// We also need to add an implicit def of this register for the later
|
|
|
|
// use to read from.
|
|
|
|
// For the register allocator to have allocated a register clobbered
|
|
|
|
// by the call which is used later, it must be the case that
|
|
|
|
// the call doesn't return.
|
|
|
|
MIB.addReg(Reg.first, RegState::Implicit | RegState::Define);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
assert(Op.isReg() && "Register operand required");
|
2015-05-07 06:51:04 +08:00
|
|
|
if (Op.isDead()) {
|
|
|
|
// If we found a dead def, but it needs to be live, then remove the dead
|
|
|
|
// flag.
|
|
|
|
if (Redefs.contains(Op.getReg()))
|
|
|
|
Op.setIsDead(false);
|
|
|
|
}
|
2016-06-25 02:57:29 +08:00
|
|
|
MIB.addReg(Reg.first, RegState::Implicit | RegState::Undef);
|
2010-06-16 15:35:02 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-10-12 03:04:37 +08:00
|
|
|
/**
|
|
|
|
* Remove kill flags from operands with a registers in the @p DontKill set.
|
|
|
|
*/
|
2013-12-14 14:52:56 +08:00
|
|
|
static void RemoveKills(MachineInstr &MI, const LivePhysRegs &DontKill) {
|
2016-02-28 01:05:33 +08:00
|
|
|
for (MIBundleOperands O(MI); O.isValid(); ++O) {
|
2013-10-12 03:04:37 +08:00
|
|
|
if (!O->isReg() || !O->isKill())
|
|
|
|
continue;
|
2013-12-14 14:52:56 +08:00
|
|
|
if (DontKill.contains(O->getReg()))
|
2013-10-12 03:04:37 +08:00
|
|
|
O->setIsKill(false);
|
2010-06-16 15:35:02 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-10-12 03:04:37 +08:00
|
|
|
/**
|
|
|
|
* Walks a range of machine instructions and removes kill flags for registers
|
|
|
|
* in the @p DontKill set.
|
|
|
|
*/
|
|
|
|
static void RemoveKills(MachineBasicBlock::iterator I,
|
|
|
|
MachineBasicBlock::iterator E,
|
2013-12-14 14:52:56 +08:00
|
|
|
const LivePhysRegs &DontKill,
|
2013-10-12 03:04:37 +08:00
|
|
|
const MCRegisterInfo &MCRI) {
|
|
|
|
for ( ; I != E; ++I)
|
2013-12-14 14:52:56 +08:00
|
|
|
RemoveKills(*I, DontKill);
|
2013-10-12 03:04:37 +08:00
|
|
|
}
|
|
|
|
|
2007-06-04 14:47:22 +08:00
|
|
|
/// IfConvertSimple - If convert a simple (split, no rejoin) sub-CFG.
|
2007-05-22 06:22:58 +08:00
|
|
|
///
|
2007-06-16 17:34:52 +08:00
|
|
|
bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) {
|
2007-05-22 06:22:58 +08:00
|
|
|
BBInfo &TrueBBI = BBAnalysis[BBI.TrueBB->getNumber()];
|
|
|
|
BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];
|
|
|
|
BBInfo *CvtBBI = &TrueBBI;
|
|
|
|
BBInfo *NextBBI = &FalseBBI;
|
2007-05-23 15:23:16 +08:00
|
|
|
|
2008-08-15 06:49:33 +08:00
|
|
|
SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
|
2007-06-16 17:34:52 +08:00
|
|
|
if (Kind == ICSimpleFalse)
|
2007-06-02 04:29:21 +08:00
|
|
|
std::swap(CvtBBI, NextBBI);
|
2007-06-16 05:18:05 +08:00
|
|
|
|
2007-06-18 16:37:25 +08:00
|
|
|
if (CvtBBI->IsDone ||
|
|
|
|
(CvtBBI->CannotBeCopied && CvtBBI->BB->pred_size() > 1)) {
|
2007-06-16 05:18:05 +08:00
|
|
|
// Something has changed. It's no longer safe to predicate this block.
|
|
|
|
BBI.IsAnalyzed = false;
|
|
|
|
CvtBBI->IsAnalyzed = false;
|
|
|
|
return false;
|
2007-06-02 04:29:21 +08:00
|
|
|
}
|
2007-05-23 15:23:16 +08:00
|
|
|
|
2013-05-06 02:03:49 +08:00
|
|
|
if (CvtBBI->BB->hasAddressTaken())
|
|
|
|
// Conservatively abort if-conversion if BB's address is taken.
|
|
|
|
return false;
|
|
|
|
|
2007-06-16 17:34:52 +08:00
|
|
|
if (Kind == ICSimpleFalse)
|
Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:
ucomisd %xmm1, %xmm0
setne %al
setp %cl
orb %al, %cl
jne .LBB4_2
it now emits this:
ucomisd %xmm1, %xmm0
jne .LBB4_2
jp .LBB4_2
It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.
To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.
Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.
llvm-svn: 57873
2008-10-21 11:29:32 +08:00
|
|
|
if (TII->ReverseBranchCondition(Cond))
|
2012-02-05 16:31:47 +08:00
|
|
|
llvm_unreachable("Unable to reverse branch condition!");
|
2007-06-16 05:18:05 +08:00
|
|
|
|
2010-06-19 13:33:57 +08:00
|
|
|
// Initialize liveins to the first BB. These are potentiall redefined by
|
2010-06-16 15:35:02 +08:00
|
|
|
// predicated instructions.
|
2013-10-15 04:45:17 +08:00
|
|
|
Redefs.init(TRI);
|
2016-05-03 08:24:32 +08:00
|
|
|
Redefs.addLiveIns(*CvtBBI->BB);
|
|
|
|
Redefs.addLiveIns(*NextBBI->BB);
|
2013-10-12 03:04:37 +08:00
|
|
|
|
|
|
|
// Compute a set of registers which must not be killed by instructions in
|
|
|
|
// BB1: This is everything live-in to BB2.
|
2013-10-15 04:45:17 +08:00
|
|
|
DontKill.init(TRI);
|
2016-05-03 08:24:32 +08:00
|
|
|
DontKill.addLiveIns(*NextBBI->BB);
|
2010-06-16 15:35:02 +08:00
|
|
|
|
2007-06-15 15:36:12 +08:00
|
|
|
if (CvtBBI->BB->pred_size() > 1) {
|
|
|
|
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
|
2009-05-14 07:25:24 +08:00
|
|
|
// Copy instructions in the true block, predicate them, and add them to
|
2007-06-15 15:36:12 +08:00
|
|
|
// the entry block.
|
2013-10-15 04:45:17 +08:00
|
|
|
CopyAndPredicateBlock(BBI, *CvtBBI, Cond);
|
2013-04-11 06:05:25 +08:00
|
|
|
|
|
|
|
// RemoveExtraEdges won't work if the block has an unanalyzable branch, so
|
|
|
|
// explicitly remove CvtBBI as a successor.
|
2015-12-13 17:26:17 +08:00
|
|
|
BBI.BB->removeSuccessor(CvtBBI->BB, true);
|
2007-06-15 15:36:12 +08:00
|
|
|
} else {
|
2013-10-12 03:04:37 +08:00
|
|
|
RemoveKills(CvtBBI->BB->begin(), CvtBBI->BB->end(), DontKill, *TRI);
|
2013-10-15 04:45:17 +08:00
|
|
|
PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond);
|
2007-05-22 06:22:58 +08:00
|
|
|
|
2007-06-15 15:36:12 +08:00
|
|
|
// Merge converted block into entry block.
|
|
|
|
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
|
|
|
|
MergeBlocks(BBI, *CvtBBI);
|
|
|
|
}
|
2007-06-07 10:12:15 +08:00
|
|
|
|
2007-06-06 10:08:52 +08:00
|
|
|
bool IterIfcvt = true;
|
2007-06-09 06:01:07 +08:00
|
|
|
if (!canFallThroughTo(BBI.BB, NextBBI->BB)) {
|
2007-05-30 06:31:16 +08:00
|
|
|
InsertUncondBranch(BBI.BB, NextBBI->BB, TII);
|
2007-06-09 09:03:43 +08:00
|
|
|
BBI.HasFallThrough = false;
|
2007-06-08 17:36:04 +08:00
|
|
|
// Now ifcvt'd block will look like this:
|
|
|
|
// BB:
|
|
|
|
// ...
|
|
|
|
// t, f = cmp
|
|
|
|
// if t op
|
|
|
|
// b BBf
|
|
|
|
//
|
|
|
|
// We cannot further ifcvt this block because the unconditional branch
|
|
|
|
// will have to be predicated on the new condition, that will not be
|
|
|
|
// available if cmp executes.
|
|
|
|
IterIfcvt = false;
|
2007-06-06 10:08:52 +08:00
|
|
|
}
|
2007-05-23 15:23:16 +08:00
|
|
|
|
2007-06-09 06:01:07 +08:00
|
|
|
RemoveExtraEdges(BBI);
|
|
|
|
|
2007-05-23 15:23:16 +08:00
|
|
|
// Update block info. BB can be iteratively if-converted.
|
2007-06-12 06:26:22 +08:00
|
|
|
if (!IterIfcvt)
|
|
|
|
BBI.IsDone = true;
|
2007-06-18 16:37:25 +08:00
|
|
|
InvalidatePreds(BBI.BB);
|
2007-06-12 06:26:22 +08:00
|
|
|
CvtBBI->IsDone = true;
|
2007-05-22 06:22:58 +08:00
|
|
|
|
|
|
|
// FIXME: Must maintain LiveIns.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2007-05-17 05:54:37 +08:00
|
|
|
/// IfConvertTriangle - If convert a triangle sub-CFG.
|
|
|
|
///
|
2007-06-16 17:34:52 +08:00
|
|
|
bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
|
2007-05-23 15:23:16 +08:00
|
|
|
BBInfo &TrueBBI = BBAnalysis[BBI.TrueBB->getNumber()];
|
2007-06-09 09:03:43 +08:00
|
|
|
BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];
|
|
|
|
BBInfo *CvtBBI = &TrueBBI;
|
|
|
|
BBInfo *NextBBI = &FalseBBI;
|
2010-06-18 06:43:56 +08:00
|
|
|
DebugLoc dl; // FIXME: this is nowhere
|
2007-06-09 09:03:43 +08:00
|
|
|
|
2008-08-15 06:49:33 +08:00
|
|
|
SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
|
2007-06-16 17:34:52 +08:00
|
|
|
if (Kind == ICTriangleFalse || Kind == ICTriangleFRev)
|
2007-06-09 09:03:43 +08:00
|
|
|
std::swap(CvtBBI, NextBBI);
|
2007-06-16 05:18:05 +08:00
|
|
|
|
2007-06-18 16:37:25 +08:00
|
|
|
if (CvtBBI->IsDone ||
|
|
|
|
(CvtBBI->CannotBeCopied && CvtBBI->BB->pred_size() > 1)) {
|
2007-06-16 05:18:05 +08:00
|
|
|
// Something has changed. It's no longer safe to predicate this block.
|
|
|
|
BBI.IsAnalyzed = false;
|
|
|
|
CvtBBI->IsAnalyzed = false;
|
|
|
|
return false;
|
2007-06-09 09:03:43 +08:00
|
|
|
}
|
2007-06-16 05:18:05 +08:00
|
|
|
|
2013-05-06 02:03:49 +08:00
|
|
|
if (CvtBBI->BB->hasAddressTaken())
|
|
|
|
// Conservatively abort if-conversion if BB's address is taken.
|
|
|
|
return false;
|
|
|
|
|
2007-06-16 17:34:52 +08:00
|
|
|
if (Kind == ICTriangleFalse || Kind == ICTriangleFRev)
|
Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:
ucomisd %xmm1, %xmm0
setne %al
setp %cl
orb %al, %cl
jne .LBB4_2
it now emits this:
ucomisd %xmm1, %xmm0
jne .LBB4_2
jp .LBB4_2
It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.
To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.
Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.
llvm-svn: 57873
2008-10-21 11:29:32 +08:00
|
|
|
if (TII->ReverseBranchCondition(Cond))
|
2012-02-05 16:31:47 +08:00
|
|
|
llvm_unreachable("Unable to reverse branch condition!");
|
2007-06-16 05:18:05 +08:00
|
|
|
|
2007-06-16 17:34:52 +08:00
|
|
|
if (Kind == ICTriangleRev || Kind == ICTriangleFRev) {
|
Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:
ucomisd %xmm1, %xmm0
setne %al
setp %cl
orb %al, %cl
jne .LBB4_2
it now emits this:
ucomisd %xmm1, %xmm0
jne .LBB4_2
jp .LBB4_2
It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.
To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.
Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.
llvm-svn: 57873
2008-10-21 11:29:32 +08:00
|
|
|
if (ReverseBranchCondition(*CvtBBI)) {
|
|
|
|
// BB has been changed, modify its predecessors (except for this
|
|
|
|
// one) so they don't get ifcvt'ed based on bad intel.
|
|
|
|
for (MachineBasicBlock::pred_iterator PI = CvtBBI->BB->pred_begin(),
|
|
|
|
E = CvtBBI->BB->pred_end(); PI != E; ++PI) {
|
|
|
|
MachineBasicBlock *PBB = *PI;
|
|
|
|
if (PBB == BBI.BB)
|
|
|
|
continue;
|
|
|
|
BBInfo &PBBI = BBAnalysis[PBB->getNumber()];
|
|
|
|
if (PBBI.IsEnqueued) {
|
|
|
|
PBBI.IsAnalyzed = false;
|
|
|
|
PBBI.IsEnqueued = false;
|
|
|
|
}
|
2007-06-15 07:34:09 +08:00
|
|
|
}
|
2007-06-13 07:54:05 +08:00
|
|
|
}
|
|
|
|
}
|
2007-06-01 15:41:07 +08:00
|
|
|
|
2010-06-19 13:33:57 +08:00
|
|
|
// Initialize liveins to the first BB. These are potentially redefined by
|
2010-06-16 15:35:02 +08:00
|
|
|
// predicated instructions.
|
2013-10-15 04:45:17 +08:00
|
|
|
Redefs.init(TRI);
|
2016-05-03 08:24:32 +08:00
|
|
|
Redefs.addLiveIns(*CvtBBI->BB);
|
|
|
|
Redefs.addLiveIns(*NextBBI->BB);
|
2010-06-16 15:35:02 +08:00
|
|
|
|
2013-10-15 04:45:17 +08:00
|
|
|
DontKill.clear();
|
|
|
|
|
2014-04-14 08:51:57 +08:00
|
|
|
bool HasEarlyExit = CvtBBI->FalseBB != nullptr;
|
2015-12-01 13:29:22 +08:00
|
|
|
BranchProbability CvtNext, CvtFalse, BBNext, BBCvt;
|
2014-08-10 01:21:29 +08:00
|
|
|
|
2014-01-30 07:18:47 +08:00
|
|
|
if (HasEarlyExit) {
|
2015-12-01 13:29:22 +08:00
|
|
|
// Get probabilities before modifying CvtBBI->BB and BBI.BB.
|
|
|
|
CvtNext = MBPI->getEdgeProbability(CvtBBI->BB, NextBBI->BB);
|
|
|
|
CvtFalse = MBPI->getEdgeProbability(CvtBBI->BB, CvtBBI->FalseBB);
|
|
|
|
BBNext = MBPI->getEdgeProbability(BBI.BB, NextBBI->BB);
|
|
|
|
BBCvt = MBPI->getEdgeProbability(BBI.BB, CvtBBI->BB);
|
2014-01-30 07:18:47 +08:00
|
|
|
}
|
2014-08-10 01:21:29 +08:00
|
|
|
|
Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 08:55:23 +08:00
|
|
|
if (CvtBBI->BB->pred_size() > 1) {
|
2007-06-15 15:36:12 +08:00
|
|
|
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
|
2009-05-14 07:25:24 +08:00
|
|
|
// Copy instructions in the true block, predicate them, and add them to
|
2007-06-15 15:36:12 +08:00
|
|
|
// the entry block.
|
2013-10-15 04:45:17 +08:00
|
|
|
CopyAndPredicateBlock(BBI, *CvtBBI, Cond, true);
|
2013-04-11 06:05:25 +08:00
|
|
|
|
|
|
|
// RemoveExtraEdges won't work if the block has an unanalyzable branch, so
|
|
|
|
// explicitly remove CvtBBI as a successor.
|
2015-12-13 17:26:17 +08:00
|
|
|
BBI.BB->removeSuccessor(CvtBBI->BB, true);
|
2007-06-15 15:36:12 +08:00
|
|
|
} else {
|
|
|
|
// Predicate the 'true' block after removing its branch.
|
|
|
|
CvtBBI->NonPredSize -= TII->RemoveBranch(*CvtBBI->BB);
|
2013-10-15 04:45:17 +08:00
|
|
|
PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond);
|
2007-05-16 10:00:57 +08:00
|
|
|
|
2007-06-19 06:44:57 +08:00
|
|
|
// Now merge the entry of the triangle with the true block.
|
|
|
|
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
|
Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 08:55:23 +08:00
|
|
|
MergeBlocks(BBI, *CvtBBI, false);
|
2007-06-19 06:44:57 +08:00
|
|
|
}
|
|
|
|
|
2007-06-04 14:47:22 +08:00
|
|
|
// If 'true' block has a 'false' successor, add an exit branch to it.
|
2007-06-05 09:31:40 +08:00
|
|
|
if (HasEarlyExit) {
|
2008-08-15 06:49:33 +08:00
|
|
|
SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(),
|
|
|
|
CvtBBI->BrCond.end());
|
2007-06-01 15:41:07 +08:00
|
|
|
if (TII->ReverseBranchCondition(RevCond))
|
2012-02-05 16:31:47 +08:00
|
|
|
llvm_unreachable("Unable to reverse branch condition!");
|
2015-12-01 13:29:22 +08:00
|
|
|
|
|
|
|
// Update the edge probability for both CvtBBI->FalseBB and NextBBI.
|
|
|
|
// NewNext = New_Prob(BBI.BB, NextBBI->BB) =
|
|
|
|
// Prob(BBI.BB, NextBBI->BB) +
|
|
|
|
// Prob(BBI.BB, CvtBBI->BB) * Prob(CvtBBI->BB, NextBBI->BB)
|
|
|
|
// NewFalse = New_Prob(BBI.BB, CvtBBI->FalseBB) =
|
|
|
|
// Prob(BBI.BB, CvtBBI->BB) * Prob(CvtBBI->BB, CvtBBI->FalseBB)
|
|
|
|
auto NewTrueBB = getNextBlock(BBI.BB);
|
|
|
|
auto NewNext = BBNext + BBCvt * CvtNext;
|
|
|
|
auto NewTrueBBIter =
|
|
|
|
std::find(BBI.BB->succ_begin(), BBI.BB->succ_end(), NewTrueBB);
|
2015-12-02 05:50:20 +08:00
|
|
|
if (NewTrueBBIter != BBI.BB->succ_end())
|
|
|
|
BBI.BB->setSuccProbability(NewTrueBBIter, NewNext);
|
2015-12-01 13:29:22 +08:00
|
|
|
|
|
|
|
auto NewFalse = BBCvt * CvtFalse;
|
2014-04-14 08:51:57 +08:00
|
|
|
TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, nullptr, RevCond, dl);
|
2015-12-01 13:29:22 +08:00
|
|
|
BBI.BB->addSuccessor(CvtBBI->FalseBB, NewFalse);
|
2007-06-15 15:36:12 +08:00
|
|
|
}
|
2007-06-08 17:36:04 +08:00
|
|
|
|
|
|
|
// Merge in the 'false' block if the 'false' block has no other
|
2009-05-14 07:25:24 +08:00
|
|
|
// predecessors. Otherwise, add an unconditional branch to 'false'.
|
2007-06-05 08:07:37 +08:00
|
|
|
bool FalseBBDead = false;
|
2007-06-06 10:08:52 +08:00
|
|
|
bool IterIfcvt = true;
|
2007-06-09 09:03:43 +08:00
|
|
|
bool isFallThrough = canFallThroughTo(BBI.BB, NextBBI->BB);
|
2007-06-07 16:13:00 +08:00
|
|
|
if (!isFallThrough) {
|
|
|
|
// Only merge them if the true block does not fallthrough to the false
|
|
|
|
// block. By not merging them, we make it possible to iteratively
|
|
|
|
// ifcvt the blocks.
|
2007-06-18 16:37:25 +08:00
|
|
|
if (!HasEarlyExit &&
|
2013-05-06 02:03:49 +08:00
|
|
|
NextBBI->BB->pred_size() == 1 && !NextBBI->HasFallThrough &&
|
|
|
|
!NextBBI->BB->hasAddressTaken()) {
|
2007-06-09 09:03:43 +08:00
|
|
|
MergeBlocks(BBI, *NextBBI);
|
2007-06-07 16:13:00 +08:00
|
|
|
FalseBBDead = true;
|
|
|
|
} else {
|
2007-06-09 09:03:43 +08:00
|
|
|
InsertUncondBranch(BBI.BB, NextBBI->BB, TII);
|
|
|
|
BBI.HasFallThrough = false;
|
2007-06-07 16:13:00 +08:00
|
|
|
}
|
2007-06-08 17:36:04 +08:00
|
|
|
// Mixed predicated and unpredicated code. This cannot be iteratively
|
|
|
|
// predicated.
|
|
|
|
IterIfcvt = false;
|
2007-06-06 10:08:52 +08:00
|
|
|
}
|
2007-05-16 10:00:57 +08:00
|
|
|
|
2007-06-09 06:01:07 +08:00
|
|
|
RemoveExtraEdges(BBI);
|
2007-05-18 08:20:58 +08:00
|
|
|
|
2007-05-23 15:23:16 +08:00
|
|
|
// Update block info. BB can be iteratively if-converted.
|
2010-06-16 06:18:54 +08:00
|
|
|
if (!IterIfcvt)
|
2007-06-12 06:26:22 +08:00
|
|
|
BBI.IsDone = true;
|
2007-06-18 16:37:25 +08:00
|
|
|
InvalidatePreds(BBI.BB);
|
2007-06-12 06:26:22 +08:00
|
|
|
CvtBBI->IsDone = true;
|
2007-06-05 08:07:37 +08:00
|
|
|
if (FalseBBDead)
|
2007-06-12 06:26:22 +08:00
|
|
|
NextBBI->IsDone = true;
|
2007-05-16 10:00:57 +08:00
|
|
|
|
2007-05-22 06:22:58 +08:00
|
|
|
// FIXME: Must maintain LiveIns.
|
|
|
|
return true;
|
2007-05-16 10:00:57 +08:00
|
|
|
}
|
|
|
|
|
2007-05-17 05:54:37 +08:00
|
|
|
/// IfConvertDiamond - If convert a diamond sub-CFG.
|
|
|
|
///
|
2007-06-18 16:37:25 +08:00
|
|
|
bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
|
|
|
|
unsigned NumDups1, unsigned NumDups2) {
|
2007-06-04 14:47:22 +08:00
|
|
|
BBInfo &TrueBBI = BBAnalysis[BBI.TrueBB->getNumber()];
|
2007-05-19 02:14:37 +08:00
|
|
|
BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];
|
2007-06-16 17:34:52 +08:00
|
|
|
MachineBasicBlock *TailBB = TrueBBI.TrueBB;
|
2009-05-14 07:25:24 +08:00
|
|
|
// True block must fall through or end with an unanalyzable terminator.
|
2007-06-16 17:34:52 +08:00
|
|
|
if (!TailBB) {
|
2007-06-18 16:37:25 +08:00
|
|
|
if (blockAlwaysFallThrough(TrueBBI))
|
|
|
|
TailBB = FalseBBI.TrueBB;
|
|
|
|
assert((TailBB || !TrueBBI.IsBrAnalyzable) && "Unexpected!");
|
2007-05-22 06:22:58 +08:00
|
|
|
}
|
2007-05-16 10:00:57 +08:00
|
|
|
|
2007-06-18 16:37:25 +08:00
|
|
|
if (TrueBBI.IsDone || FalseBBI.IsDone ||
|
|
|
|
TrueBBI.BB->pred_size() > 1 ||
|
|
|
|
FalseBBI.BB->pred_size() > 1) {
|
|
|
|
// Something has changed. It's no longer safe to predicate these blocks.
|
|
|
|
BBI.IsAnalyzed = false;
|
|
|
|
TrueBBI.IsAnalyzed = false;
|
|
|
|
FalseBBI.IsAnalyzed = false;
|
|
|
|
return false;
|
2007-05-22 06:22:58 +08:00
|
|
|
}
|
2007-06-18 16:37:25 +08:00
|
|
|
|
2013-05-06 02:03:49 +08:00
|
|
|
if (TrueBBI.BB->hasAddressTaken() || FalseBBI.BB->hasAddressTaken())
|
|
|
|
// Conservatively abort if-conversion if either BB has its address taken.
|
|
|
|
return false;
|
|
|
|
|
Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 08:55:23 +08:00
|
|
|
// Put the predicated instructions from the 'true' block before the
|
|
|
|
// instructions from the 'false' block, unless the true block would clobber
|
|
|
|
// the predicate, in which case, do the opposite.
|
2007-06-06 07:46:14 +08:00
|
|
|
BBInfo *BBI1 = &TrueBBI;
|
|
|
|
BBInfo *BBI2 = &FalseBBI;
|
2008-08-15 06:49:33 +08:00
|
|
|
SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
|
Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:
ucomisd %xmm1, %xmm0
setne %al
setp %cl
orb %al, %cl
jne .LBB4_2
it now emits this:
ucomisd %xmm1, %xmm0
jne .LBB4_2
jp .LBB4_2
It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.
To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.
Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.
llvm-svn: 57873
2008-10-21 11:29:32 +08:00
|
|
|
if (TII->ReverseBranchCondition(RevCond))
|
2012-02-05 16:31:47 +08:00
|
|
|
llvm_unreachable("Unable to reverse branch condition!");
|
2008-08-15 06:49:33 +08:00
|
|
|
SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond;
|
|
|
|
SmallVector<MachineOperand, 4> *Cond2 = &RevCond;
|
2007-06-16 17:34:52 +08:00
|
|
|
|
|
|
|
// Figure out the more profitable ordering.
|
|
|
|
bool DoSwap = false;
|
|
|
|
if (TrueBBI.ClobbersPred && !FalseBBI.ClobbersPred)
|
|
|
|
DoSwap = true;
|
|
|
|
else if (TrueBBI.ClobbersPred == FalseBBI.ClobbersPred) {
|
2007-06-19 06:44:57 +08:00
|
|
|
if (TrueBBI.NonPredSize > FalseBBI.NonPredSize)
|
2007-06-16 17:34:52 +08:00
|
|
|
DoSwap = true;
|
|
|
|
}
|
|
|
|
if (DoSwap) {
|
2007-06-06 08:57:55 +08:00
|
|
|
std::swap(BBI1, BBI2);
|
|
|
|
std::swap(Cond1, Cond2);
|
|
|
|
}
|
2007-06-06 07:46:14 +08:00
|
|
|
|
2007-06-18 16:37:25 +08:00
|
|
|
// Remove the conditional branch from entry to the blocks.
|
|
|
|
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
|
|
|
|
|
2010-06-26 06:02:28 +08:00
|
|
|
// Initialize liveins to the first BB. These are potentially redefined by
|
2010-06-16 15:35:02 +08:00
|
|
|
// predicated instructions.
|
2013-10-15 04:45:17 +08:00
|
|
|
Redefs.init(TRI);
|
2016-05-03 08:24:32 +08:00
|
|
|
Redefs.addLiveIns(*BBI1->BB);
|
2010-06-16 15:35:02 +08:00
|
|
|
|
2007-06-18 16:37:25 +08:00
|
|
|
// Remove the duplicated instructions at the beginnings of both paths.
|
2010-06-15 05:30:32 +08:00
|
|
|
// Skip dbg_value instructions
|
2015-06-23 22:47:29 +08:00
|
|
|
MachineBasicBlock::iterator DI1 = BBI1->BB->getFirstNonDebugInstr();
|
|
|
|
MachineBasicBlock::iterator DI2 = BBI2->BB->getFirstNonDebugInstr();
|
2007-06-18 16:37:25 +08:00
|
|
|
BBI1->NonPredSize -= NumDups1;
|
|
|
|
BBI2->NonPredSize -= NumDups1;
|
2010-06-29 04:26:00 +08:00
|
|
|
|
|
|
|
// Skip past the dups on each side separately since there may be
|
|
|
|
// differing dbg_value entries.
|
|
|
|
for (unsigned i = 0; i < NumDups1; ++DI1) {
|
|
|
|
if (!DI1->isDebugValue())
|
|
|
|
++i;
|
|
|
|
}
|
2010-06-26 07:05:46 +08:00
|
|
|
while (NumDups1 != 0) {
|
2007-06-18 16:37:25 +08:00
|
|
|
++DI2;
|
2010-06-29 04:26:00 +08:00
|
|
|
if (!DI2->isDebugValue())
|
|
|
|
--NumDups1;
|
2007-06-18 16:37:25 +08:00
|
|
|
}
|
2010-06-16 15:35:02 +08:00
|
|
|
|
2013-10-12 03:04:37 +08:00
|
|
|
// Compute a set of registers which must not be killed by instructions in BB1:
|
|
|
|
// This is everything used+live in BB2 after the duplicated instructions. We
|
|
|
|
// can compute this set by simulating liveness backwards from the end of BB2.
|
2013-10-15 04:45:17 +08:00
|
|
|
DontKill.init(TRI);
|
2013-10-12 03:49:09 +08:00
|
|
|
for (MachineBasicBlock::reverse_iterator I = BBI2->BB->rbegin(),
|
|
|
|
E = MachineBasicBlock::reverse_iterator(DI2); I != E; ++I) {
|
2013-12-14 14:52:56 +08:00
|
|
|
DontKill.stepBackward(*I);
|
2013-10-12 03:04:37 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
for (MachineBasicBlock::const_iterator I = BBI1->BB->begin(), E = DI1; I != E;
|
|
|
|
++I) {
|
2015-05-06 04:14:22 +08:00
|
|
|
SmallVector<std::pair<unsigned, const MachineOperand*>, 4> IgnoredClobbers;
|
|
|
|
Redefs.stepForward(*I, IgnoredClobbers);
|
2013-10-12 03:04:37 +08:00
|
|
|
}
|
2007-06-18 16:37:25 +08:00
|
|
|
BBI.BB->splice(BBI.BB->end(), BBI1->BB, BBI1->BB->begin(), DI1);
|
|
|
|
BBI2->BB->erase(BBI2->BB->begin(), DI2);
|
|
|
|
|
2016-01-20 21:14:52 +08:00
|
|
|
// Remove branch from the 'true' block, unless it was not analyzable.
|
|
|
|
// Non-analyzable branches need to be preserved, since in such cases,
|
|
|
|
// the CFG structure is not an actual diamond (the join block may not
|
|
|
|
// be present).
|
|
|
|
if (BBI1->IsBrAnalyzable)
|
|
|
|
BBI1->NonPredSize -= TII->RemoveBranch(*BBI1->BB);
|
|
|
|
// Remove duplicated instructions.
|
2007-06-18 16:37:25 +08:00
|
|
|
DI1 = BBI1->BB->end();
|
2010-06-15 05:30:32 +08:00
|
|
|
for (unsigned i = 0; i != NumDups2; ) {
|
|
|
|
// NumDups2 only counted non-dbg_value instructions, so this won't
|
|
|
|
// run off the head of the list.
|
|
|
|
assert (DI1 != BBI1->BB->begin());
|
2007-06-18 16:37:25 +08:00
|
|
|
--DI1;
|
2010-06-15 05:30:32 +08:00
|
|
|
// skip dbg_value instructions
|
|
|
|
if (!DI1->isDebugValue())
|
|
|
|
++i;
|
|
|
|
}
|
2007-06-18 16:37:25 +08:00
|
|
|
BBI1->BB->erase(DI1, BBI1->BB->end());
|
2007-06-06 07:46:14 +08:00
|
|
|
|
2013-10-12 03:04:37 +08:00
|
|
|
// Kill flags in the true block for registers living into the false block
|
|
|
|
// must be removed.
|
|
|
|
RemoveKills(BBI1->BB->begin(), BBI1->BB->end(), DontKill, *TRI);
|
|
|
|
|
2016-01-20 21:14:52 +08:00
|
|
|
// Remove 'false' block branch (unless it was not analyzable), and find
|
|
|
|
// the last instruction to predicate.
|
|
|
|
if (BBI2->IsBrAnalyzable)
|
|
|
|
BBI2->NonPredSize -= TII->RemoveBranch(*BBI2->BB);
|
2007-06-18 16:37:25 +08:00
|
|
|
DI2 = BBI2->BB->end();
|
|
|
|
while (NumDups2 != 0) {
|
2010-06-15 05:30:32 +08:00
|
|
|
// NumDups2 only counted non-dbg_value instructions, so this won't
|
|
|
|
// run off the head of the list.
|
|
|
|
assert (DI2 != BBI2->BB->begin());
|
2007-06-18 16:37:25 +08:00
|
|
|
--DI2;
|
2010-06-15 05:30:32 +08:00
|
|
|
// skip dbg_value instructions
|
|
|
|
if (!DI2->isDebugValue())
|
|
|
|
--NumDups2;
|
2007-06-18 16:37:25 +08:00
|
|
|
}
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
|
|
|
|
// Remember which registers would later be defined by the false block.
|
|
|
|
// This allows us not to predicate instructions in the true block that would
|
|
|
|
// later be re-defined. That is, rather than
|
|
|
|
// subeq r0, r1, #1
|
|
|
|
// addne r0, r1, #1
|
|
|
|
// generate:
|
|
|
|
// sub r0, r1, #1
|
|
|
|
// addne r0, r1, #1
|
|
|
|
SmallSet<unsigned, 4> RedefsByFalse;
|
|
|
|
SmallSet<unsigned, 4> ExtUses;
|
|
|
|
if (TII->isProfitableToUnpredicate(*BBI1->BB, *BBI2->BB)) {
|
|
|
|
for (MachineBasicBlock::iterator FI = BBI2->BB->begin(); FI != DI2; ++FI) {
|
|
|
|
if (FI->isDebugValue())
|
|
|
|
continue;
|
|
|
|
SmallVector<unsigned, 4> Defs;
|
|
|
|
for (unsigned i = 0, e = FI->getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = FI->getOperand(i);
|
|
|
|
if (!MO.isReg())
|
|
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (!Reg)
|
|
|
|
continue;
|
|
|
|
if (MO.isDef()) {
|
|
|
|
Defs.push_back(Reg);
|
|
|
|
} else if (!RedefsByFalse.count(Reg)) {
|
|
|
|
// These are defined before ctrl flow reach the 'false' instructions.
|
|
|
|
// They cannot be modified by the 'true' instructions.
|
2013-05-23 07:17:36 +08:00
|
|
|
for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
|
|
|
|
SubRegs.isValid(); ++SubRegs)
|
2012-06-02 07:28:30 +08:00
|
|
|
ExtUses.insert(*SubRegs);
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
|
|
|
|
unsigned Reg = Defs[i];
|
|
|
|
if (!ExtUses.count(Reg)) {
|
2013-05-23 07:17:36 +08:00
|
|
|
for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
|
|
|
|
SubRegs.isValid(); ++SubRegs)
|
2012-06-02 07:28:30 +08:00
|
|
|
RedefsByFalse.insert(*SubRegs);
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Predicate the 'true' block.
|
2013-10-15 04:45:17 +08:00
|
|
|
PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1, &RedefsByFalse);
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
|
2016-01-20 21:14:52 +08:00
|
|
|
// After predicating BBI1, if there is a predicated terminator in BBI1 and
|
|
|
|
// a non-predicated in BBI2, then we don't want to predicate the one from
|
|
|
|
// BBI2. The reason is that if we merged these blocks, we would end up with
|
|
|
|
// two predicated terminators in the same block.
|
|
|
|
if (!BBI2->BB->empty() && (DI2 == BBI2->BB->end())) {
|
|
|
|
MachineBasicBlock::iterator BBI1T = BBI1->BB->getFirstTerminator();
|
|
|
|
MachineBasicBlock::iterator BBI2T = BBI2->BB->getFirstTerminator();
|
2016-02-23 10:46:52 +08:00
|
|
|
if (BBI1T != BBI1->BB->end() && TII->isPredicated(*BBI1T) &&
|
|
|
|
BBI2T != BBI2->BB->end() && !TII->isPredicated(*BBI2T))
|
2016-01-20 21:14:52 +08:00
|
|
|
--DI2;
|
|
|
|
}
|
|
|
|
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
// Predicate the 'false' block.
|
2013-10-15 04:45:17 +08:00
|
|
|
PredicateBlock(*BBI2, DI2, *Cond2);
|
2007-06-06 07:46:14 +08:00
|
|
|
|
2007-06-19 06:44:57 +08:00
|
|
|
// Merge the true block into the entry of the diamond.
|
2014-04-14 08:51:57 +08:00
|
|
|
MergeBlocks(BBI, *BBI1, TailBB == nullptr);
|
|
|
|
MergeBlocks(BBI, *BBI2, TailBB == nullptr);
|
2007-06-06 08:57:55 +08:00
|
|
|
|
2009-05-14 07:25:24 +08:00
|
|
|
// If the if-converted block falls through or unconditionally branches into
|
|
|
|
// the tail block, and the tail block does not have other predecessors, then
|
2007-06-18 16:37:25 +08:00
|
|
|
// fold the tail block in as well. Otherwise, unless it falls through to the
|
|
|
|
// tail, add a unconditional branch to it.
|
|
|
|
if (TailBB) {
|
2011-11-05 07:49:14 +08:00
|
|
|
BBInfo &TailBBI = BBAnalysis[TailBB->getNumber()];
|
2013-05-06 02:03:49 +08:00
|
|
|
bool CanMergeTail = !TailBBI.HasFallThrough &&
|
|
|
|
!TailBBI.BB->hasAddressTaken();
|
2016-01-20 21:14:52 +08:00
|
|
|
// The if-converted block can still have a predicated terminator
|
|
|
|
// (e.g. a predicated return). If that is the case, we cannot merge
|
|
|
|
// it with the tail block.
|
|
|
|
MachineBasicBlock::const_iterator TI = BBI.BB->getFirstTerminator();
|
2016-02-23 10:46:52 +08:00
|
|
|
if (TI != BBI.BB->end() && TII->isPredicated(*TI))
|
2016-01-20 21:14:52 +08:00
|
|
|
CanMergeTail = false;
|
Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 08:55:23 +08:00
|
|
|
// There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
|
|
|
|
// check if there are any other predecessors besides those.
|
|
|
|
unsigned NumPreds = TailBB->pred_size();
|
|
|
|
if (NumPreds > 1)
|
|
|
|
CanMergeTail = false;
|
|
|
|
else if (NumPreds == 1 && CanMergeTail) {
|
|
|
|
MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
|
|
|
|
if (*PI != BBI1->BB && *PI != BBI2->BB)
|
|
|
|
CanMergeTail = false;
|
|
|
|
}
|
|
|
|
if (CanMergeTail) {
|
2007-06-19 06:44:57 +08:00
|
|
|
MergeBlocks(BBI, TailBBI);
|
2007-06-18 16:37:25 +08:00
|
|
|
TailBBI.IsDone = true;
|
|
|
|
} else {
|
2015-12-01 13:29:22 +08:00
|
|
|
BBI.BB->addSuccessor(TailBB, BranchProbability::getOne());
|
2007-06-19 06:44:57 +08:00
|
|
|
InsertUncondBranch(BBI.BB, TailBB, TII);
|
|
|
|
BBI.HasFallThrough = false;
|
2007-06-18 16:37:25 +08:00
|
|
|
}
|
2007-05-22 06:22:58 +08:00
|
|
|
}
|
2007-05-18 08:20:58 +08:00
|
|
|
|
Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 08:55:23 +08:00
|
|
|
// RemoveExtraEdges won't work if the block has an unanalyzable branch,
|
|
|
|
// which can happen here if TailBB is unanalyzable and is merged, so
|
|
|
|
// explicitly remove BBI1 and BBI2 as successors.
|
|
|
|
BBI.BB->removeSuccessor(BBI1->BB);
|
2015-12-13 17:26:17 +08:00
|
|
|
BBI.BB->removeSuccessor(BBI2->BB, true);
|
2007-06-09 06:01:07 +08:00
|
|
|
RemoveExtraEdges(BBI);
|
|
|
|
|
2007-06-06 07:46:14 +08:00
|
|
|
// Update block info.
|
2007-06-12 06:26:22 +08:00
|
|
|
BBI.IsDone = TrueBBI.IsDone = FalseBBI.IsDone = true;
|
2007-06-18 16:37:25 +08:00
|
|
|
InvalidatePreds(BBI.BB);
|
2007-05-16 10:00:57 +08:00
|
|
|
|
2007-05-22 06:22:58 +08:00
|
|
|
// FIXME: Must maintain LiveIns.
|
|
|
|
return true;
|
2007-05-16 10:00:57 +08:00
|
|
|
}
|
|
|
|
|
2016-07-01 07:04:51 +08:00
|
|
|
static bool MaySpeculate(const MachineInstr &MI,
|
2015-05-20 05:22:20 +08:00
|
|
|
SmallSet<unsigned, 4> &LaterRedefs) {
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
bool SawStore = true;
|
2016-07-01 07:04:51 +08:00
|
|
|
if (!MI.isSafeToMove(nullptr, SawStore))
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
return false;
|
|
|
|
|
2016-07-01 07:04:51 +08:00
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = MI.getOperand(i);
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
if (!MO.isReg())
|
|
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (!Reg)
|
|
|
|
continue;
|
|
|
|
if (MO.isDef() && !LaterRedefs.count(Reg))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2007-06-18 16:37:25 +08:00
|
|
|
/// PredicateBlock - Predicate instructions from the start of the block to the
|
|
|
|
/// specified end with the specified condition.
|
2007-05-23 15:23:16 +08:00
|
|
|
void IfConverter::PredicateBlock(BBInfo &BBI,
|
2007-06-18 16:37:25 +08:00
|
|
|
MachineBasicBlock::iterator E,
|
2010-06-16 15:35:02 +08:00
|
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
SmallSet<unsigned, 4> *LaterRedefs) {
|
|
|
|
bool AnyUnpred = false;
|
2014-04-14 08:51:57 +08:00
|
|
|
bool MaySpec = LaterRedefs != nullptr;
|
2016-07-01 07:04:51 +08:00
|
|
|
for (MachineInstr &I : llvm::make_range(BBI.BB->begin(), E)) {
|
|
|
|
if (I.isDebugValue() || TII->isPredicated(I))
|
2007-05-16 10:00:57 +08:00
|
|
|
continue;
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
// It may be possible not to predicate an instruction if it's the 'true'
|
|
|
|
// side of a diamond and the 'false' side may re-define the instruction's
|
|
|
|
// defs.
|
2015-05-20 05:22:20 +08:00
|
|
|
if (MaySpec && MaySpeculate(I, *LaterRedefs)) {
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
AnyUnpred = true;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// If any instruction is predicated, then every instruction after it must
|
|
|
|
// be predicated.
|
|
|
|
MaySpec = false;
|
2016-07-01 07:04:51 +08:00
|
|
|
if (!TII->PredicateInstruction(I, Cond)) {
|
2009-07-13 04:07:01 +08:00
|
|
|
#ifndef NDEBUG
|
2016-07-01 07:04:51 +08:00
|
|
|
dbgs() << "Unable to predicate " << I << "!\n";
|
2009-07-13 04:07:01 +08:00
|
|
|
#endif
|
2014-04-14 08:51:57 +08:00
|
|
|
llvm_unreachable(nullptr);
|
2007-05-17 05:54:37 +08:00
|
|
|
}
|
2010-06-16 15:35:02 +08:00
|
|
|
|
2010-06-19 13:33:57 +08:00
|
|
|
// If the predicated instruction now redefines a register as the result of
|
2010-06-16 15:35:02 +08:00
|
|
|
// if-conversion, add an implicit kill.
|
2016-07-01 07:04:51 +08:00
|
|
|
UpdatePredRedefs(I, Redefs);
|
2007-05-16 10:00:57 +08:00
|
|
|
}
|
2007-05-23 15:23:16 +08:00
|
|
|
|
2015-02-28 18:11:12 +08:00
|
|
|
BBI.Predicate.append(Cond.begin(), Cond.end());
|
2007-06-15 15:36:12 +08:00
|
|
|
|
2007-06-15 04:28:52 +08:00
|
|
|
BBI.IsAnalyzed = false;
|
2007-05-23 15:23:16 +08:00
|
|
|
BBI.NonPredSize = 0;
|
2007-06-09 03:17:12 +08:00
|
|
|
|
2010-06-22 23:08:57 +08:00
|
|
|
++NumIfConvBBs;
|
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-20 06:01:30 +08:00
|
|
|
if (AnyUnpred)
|
|
|
|
++NumUnpred;
|
2007-06-04 14:47:22 +08:00
|
|
|
}
|
|
|
|
|
2007-06-15 15:36:12 +08:00
|
|
|
/// CopyAndPredicateBlock - Copy and predicate instructions from source BB to
|
|
|
|
/// the destination block. Skip end of block branches if IgnoreBr is true.
|
|
|
|
void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
|
2008-08-15 06:49:33 +08:00
|
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
2007-06-15 15:36:12 +08:00
|
|
|
bool IgnoreBr) {
|
2008-07-08 07:14:23 +08:00
|
|
|
MachineFunction &MF = *ToBBI.BB->getParent();
|
|
|
|
|
2016-02-23 10:46:52 +08:00
|
|
|
for (auto &I : *FromBBI.BB) {
|
2007-06-15 15:36:12 +08:00
|
|
|
// Do not copy the end of the block branches.
|
2016-02-23 10:46:52 +08:00
|
|
|
if (IgnoreBr && I.isBranch())
|
2007-06-15 15:36:12 +08:00
|
|
|
break;
|
|
|
|
|
2016-02-23 10:46:52 +08:00
|
|
|
MachineInstr *MI = MF.CloneMachineInstr(&I);
|
2007-06-15 15:36:12 +08:00
|
|
|
ToBBI.BB->insert(ToBBI.BB->end(), MI);
|
2010-10-26 08:02:21 +08:00
|
|
|
ToBBI.NonPredSize++;
|
2016-02-23 10:46:52 +08:00
|
|
|
unsigned ExtraPredCost = TII->getPredicationCost(I);
|
|
|
|
unsigned NumCycles = SchedModel.computeInstrLatency(&I, false);
|
2010-11-03 08:45:17 +08:00
|
|
|
if (NumCycles > 1)
|
|
|
|
ToBBI.ExtraCost += NumCycles-1;
|
|
|
|
ToBBI.ExtraCost2 += ExtraPredCost;
|
2007-06-15 15:36:12 +08:00
|
|
|
|
Fix PR7372: Conditional branches (at least on ARM) are treated as predicated,
so when IfConverter::CopyAndPredicateBlock checks to see if it should ignore
an instruction because it is a branch, it should not check if the branch is
predicated.
This case (when IgnoreBr is true) is only relevant from IfConvertTriangle,
where new branches are inserted after the block has been copied and predicated.
If the original branch is not removed, we end up with multiple conditional
branches (possibly conflicting) at the end of the block. Aside from any
immediate errors resulting from that, this confuses the AnalyzeBranch functions
so that the branches are not analyzable. That in turn causes the IfConverter to
think that the "Simple" pattern can be applied, and things go downhill fast
because the "Simple" pattern does _not_ apply if the block can fall through.
This is pretty fragile. If there are other degenerate cases where AnalyzeBranch
fails, but where the block may still fall through, the IfConverter should not
perform its "Simple" if-conversion. But, I don't know how to do that with the
current AnalyzeBranch interface, so for now, the best thing seems to be to
avoid creating branches that AnalyzeBranch cannot handle.
Evan, please review!
llvm-svn: 106291
2010-06-19 01:07:23 +08:00
|
|
|
if (!TII->isPredicated(I) && !MI->isDebugValue()) {
|
2016-02-23 10:46:52 +08:00
|
|
|
if (!TII->PredicateInstruction(*MI, Cond)) {
|
2009-07-13 04:07:01 +08:00
|
|
|
#ifndef NDEBUG
|
2016-02-23 10:46:52 +08:00
|
|
|
dbgs() << "Unable to predicate " << I << "!\n";
|
2009-07-13 04:07:01 +08:00
|
|
|
#endif
|
2014-04-14 08:51:57 +08:00
|
|
|
llvm_unreachable(nullptr);
|
2007-06-15 15:36:12 +08:00
|
|
|
}
|
2010-06-16 15:35:02 +08:00
|
|
|
}
|
|
|
|
|
2010-06-19 13:33:57 +08:00
|
|
|
// If the predicated instruction now redefines a register as the result of
|
2010-06-16 15:35:02 +08:00
|
|
|
// if-conversion, add an implicit kill.
|
2016-02-23 10:46:52 +08:00
|
|
|
UpdatePredRedefs(*MI, Redefs);
|
2013-10-12 03:04:37 +08:00
|
|
|
|
|
|
|
// Some kill flags may not be correct anymore.
|
2013-10-15 04:45:17 +08:00
|
|
|
if (!DontKill.empty())
|
2013-12-14 14:52:56 +08:00
|
|
|
RemoveKills(*MI, DontKill);
|
2007-06-15 15:36:12 +08:00
|
|
|
}
|
|
|
|
|
Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 08:55:23 +08:00
|
|
|
if (!IgnoreBr) {
|
|
|
|
std::vector<MachineBasicBlock *> Succs(FromBBI.BB->succ_begin(),
|
|
|
|
FromBBI.BB->succ_end());
|
|
|
|
MachineBasicBlock *NBB = getNextBlock(FromBBI.BB);
|
2014-04-14 08:51:57 +08:00
|
|
|
MachineBasicBlock *FallThrough = FromBBI.HasFallThrough ? NBB : nullptr;
|
2007-06-19 06:44:57 +08:00
|
|
|
|
Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 08:55:23 +08:00
|
|
|
for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
|
|
|
|
MachineBasicBlock *Succ = Succs[i];
|
|
|
|
// Fallthrough edge can't be transferred.
|
|
|
|
if (Succ == FallThrough)
|
|
|
|
continue;
|
|
|
|
ToBBI.BB->addSuccessor(Succ);
|
|
|
|
}
|
2007-06-19 06:44:57 +08:00
|
|
|
}
|
|
|
|
|
2015-02-28 18:11:12 +08:00
|
|
|
ToBBI.Predicate.append(FromBBI.Predicate.begin(), FromBBI.Predicate.end());
|
|
|
|
ToBBI.Predicate.append(Cond.begin(), Cond.end());
|
2007-06-15 15:36:12 +08:00
|
|
|
|
|
|
|
ToBBI.ClobbersPred |= FromBBI.ClobbersPred;
|
|
|
|
ToBBI.IsAnalyzed = false;
|
|
|
|
|
2010-06-22 23:08:57 +08:00
|
|
|
++NumDupBBs;
|
2007-06-15 15:36:12 +08:00
|
|
|
}
|
|
|
|
|
2007-05-18 08:20:58 +08:00
|
|
|
/// MergeBlocks - Move all instructions from FromBB to the end of ToBB.
|
Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 08:55:23 +08:00
|
|
|
/// This will leave FromBB as an empty block, so remove all of its
|
|
|
|
/// successor edges except for the fall-through edge. If AddEdges is true,
|
|
|
|
/// i.e., when FromBBI's branch is being moved, add those successor edges to
|
|
|
|
/// ToBBI.
|
|
|
|
void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges) {
|
2013-05-06 02:03:49 +08:00
|
|
|
assert(!FromBBI.BB->hasAddressTaken() &&
|
|
|
|
"Removing a BB whose address is taken!");
|
|
|
|
|
2016-01-20 21:14:52 +08:00
|
|
|
// In case FromBBI.BB contains terminators (e.g. return instruction),
|
|
|
|
// first move the non-terminator instructions, then the terminators.
|
|
|
|
MachineBasicBlock::iterator FromTI = FromBBI.BB->getFirstTerminator();
|
|
|
|
MachineBasicBlock::iterator ToTI = ToBBI.BB->getFirstTerminator();
|
|
|
|
ToBBI.BB->splice(ToTI, FromBBI.BB, FromBBI.BB->begin(), FromTI);
|
|
|
|
|
|
|
|
// If FromBB has non-predicated terminator we should copy it at the end.
|
2016-02-23 10:46:52 +08:00
|
|
|
if (FromTI != FromBBI.BB->end() && !TII->isPredicated(*FromTI))
|
2016-01-20 21:14:52 +08:00
|
|
|
ToTI = ToBBI.BB->end();
|
|
|
|
ToBBI.BB->splice(ToTI, FromBBI.BB, FromTI, FromBBI.BB->end());
|
2007-05-23 15:23:16 +08:00
|
|
|
|
2015-12-17 09:29:08 +08:00
|
|
|
// Force normalizing the successors' probabilities of ToBBI.BB to convert all
|
|
|
|
// unknown probabilities into known ones.
|
|
|
|
// FIXME: This usage is too tricky and in the future we would like to
|
|
|
|
// eliminate all unknown probabilities in MBB.
|
|
|
|
ToBBI.BB->normalizeSuccProbs();
|
|
|
|
|
2015-09-19 04:22:41 +08:00
|
|
|
SmallVector<MachineBasicBlock *, 4> FromSuccs(FromBBI.BB->succ_begin(),
|
|
|
|
FromBBI.BB->succ_end());
|
2007-06-09 06:01:07 +08:00
|
|
|
MachineBasicBlock *NBB = getNextBlock(FromBBI.BB);
|
2014-04-14 08:51:57 +08:00
|
|
|
MachineBasicBlock *FallThrough = FromBBI.HasFallThrough ? NBB : nullptr;
|
2015-12-01 13:29:22 +08:00
|
|
|
// The edge probability from ToBBI.BB to FromBBI.BB, which is only needed when
|
2015-12-01 11:49:42 +08:00
|
|
|
// AddEdges is true and FromBBI.BB is a successor of ToBBI.BB.
|
2015-12-01 13:29:22 +08:00
|
|
|
auto To2FromProb = BranchProbability::getZero();
|
2015-12-01 08:02:51 +08:00
|
|
|
if (AddEdges && ToBBI.BB->isSuccessor(FromBBI.BB)) {
|
2015-12-01 13:29:22 +08:00
|
|
|
To2FromProb = MBPI->getEdgeProbability(ToBBI.BB, FromBBI.BB);
|
|
|
|
// Set the edge probability from ToBBI.BB to FromBBI.BB to zero to avoid the
|
|
|
|
// edge probability being merged to other edges when this edge is removed
|
|
|
|
// later.
|
|
|
|
ToBBI.BB->setSuccProbability(
|
|
|
|
std::find(ToBBI.BB->succ_begin(), ToBBI.BB->succ_end(), FromBBI.BB),
|
|
|
|
BranchProbability::getZero());
|
|
|
|
}
|
|
|
|
|
2015-09-19 04:22:41 +08:00
|
|
|
for (unsigned i = 0, e = FromSuccs.size(); i != e; ++i) {
|
|
|
|
MachineBasicBlock *Succ = FromSuccs[i];
|
2007-06-09 06:01:07 +08:00
|
|
|
// Fallthrough edge can't be transferred.
|
2007-06-07 10:12:15 +08:00
|
|
|
if (Succ == FallThrough)
|
|
|
|
continue;
|
2015-09-19 04:22:41 +08:00
|
|
|
|
2015-12-01 13:29:22 +08:00
|
|
|
auto NewProb = BranchProbability::getZero();
|
2015-09-19 04:22:41 +08:00
|
|
|
if (AddEdges) {
|
2015-12-01 13:29:22 +08:00
|
|
|
// Calculate the edge probability for the edge from ToBBI.BB to Succ,
|
|
|
|
// which is a portion of the edge probability from FromBBI.BB to Succ. The
|
|
|
|
// portion ratio is the edge probability from ToBBI.BB to FromBBI.BB (if
|
|
|
|
// FromBBI is a successor of ToBBI.BB. See comment below for excepion).
|
|
|
|
NewProb = MBPI->getEdgeProbability(FromBBI.BB, Succ);
|
2015-09-19 04:22:41 +08:00
|
|
|
|
2015-12-01 13:29:22 +08:00
|
|
|
// To2FromProb is 0 when FromBBI.BB is not a successor of ToBBI.BB. This
|
2015-09-19 04:22:41 +08:00
|
|
|
// only happens when if-converting a diamond CFG and FromBBI.BB is the
|
|
|
|
// tail BB. In this case FromBBI.BB post-dominates ToBBI.BB and hence we
|
2015-12-01 13:29:22 +08:00
|
|
|
// could just use the probabilities on FromBBI.BB's out-edges when adding
|
|
|
|
// new successors.
|
|
|
|
if (!To2FromProb.isZero())
|
|
|
|
NewProb *= To2FromProb;
|
2015-09-19 04:22:41 +08:00
|
|
|
}
|
|
|
|
|
2007-06-07 10:12:15 +08:00
|
|
|
FromBBI.BB->removeSuccessor(Succ);
|
2015-09-19 04:22:41 +08:00
|
|
|
|
|
|
|
if (AddEdges) {
|
2015-12-01 13:29:22 +08:00
|
|
|
// If the edge from ToBBI.BB to Succ already exists, update the
|
2015-12-13 17:26:17 +08:00
|
|
|
// probability of this edge by adding NewProb to it. An example is shown
|
2015-12-01 13:29:22 +08:00
|
|
|
// below, in which A is ToBBI.BB and B is FromBBI.BB. In this case we
|
|
|
|
// don't have to set C as A's successor as it already is. We only need to
|
|
|
|
// update the edge probability on A->C. Note that B will not be
|
|
|
|
// immediately removed from A's successors. It is possible that B->D is
|
|
|
|
// not removed either if D is a fallthrough of B. Later the edge A->D
|
|
|
|
// (generated here) and B->D will be combined into one edge. To maintain
|
|
|
|
// correct edge probability of this combined edge, we need to set the edge
|
|
|
|
// probability of A->B to zero, which is already done above. The edge
|
|
|
|
// probability on A->D is calculated by scaling the original probability
|
|
|
|
// on A->B by the probability of B->D.
|
2015-09-19 04:22:41 +08:00
|
|
|
//
|
|
|
|
// Before ifcvt: After ifcvt (assume B->D is kept):
|
|
|
|
//
|
|
|
|
// A A
|
|
|
|
// /| /|\
|
|
|
|
// / B / B|
|
|
|
|
// | /| | ||
|
|
|
|
// |/ | | |/
|
|
|
|
// C D C D
|
|
|
|
//
|
|
|
|
if (ToBBI.BB->isSuccessor(Succ))
|
2015-12-01 13:29:22 +08:00
|
|
|
ToBBI.BB->setSuccProbability(
|
2015-09-19 04:22:41 +08:00
|
|
|
std::find(ToBBI.BB->succ_begin(), ToBBI.BB->succ_end(), Succ),
|
2015-12-01 13:29:22 +08:00
|
|
|
MBPI->getEdgeProbability(ToBBI.BB, Succ) + NewProb);
|
2015-09-19 04:22:41 +08:00
|
|
|
else
|
2015-12-01 13:29:22 +08:00
|
|
|
ToBBI.BB->addSuccessor(Succ, NewProb);
|
2015-09-19 04:22:41 +08:00
|
|
|
}
|
2007-06-07 10:12:15 +08:00
|
|
|
}
|
2007-06-04 14:47:22 +08:00
|
|
|
|
2009-05-14 07:25:24 +08:00
|
|
|
// Now FromBBI always falls through to the next block!
|
2009-05-14 07:48:58 +08:00
|
|
|
if (NBB && !FromBBI.BB->isSuccessor(NBB))
|
2007-06-09 06:01:07 +08:00
|
|
|
FromBBI.BB->addSuccessor(NBB);
|
|
|
|
|
2015-12-13 17:26:17 +08:00
|
|
|
// Normalize the probabilities of ToBBI.BB's successors with all adjustment
|
|
|
|
// we've done above.
|
|
|
|
ToBBI.BB->normalizeSuccProbs();
|
|
|
|
|
2015-02-28 18:11:12 +08:00
|
|
|
ToBBI.Predicate.append(FromBBI.Predicate.begin(), FromBBI.Predicate.end());
|
2007-06-15 15:36:12 +08:00
|
|
|
FromBBI.Predicate.clear();
|
|
|
|
|
2007-05-23 15:23:16 +08:00
|
|
|
ToBBI.NonPredSize += FromBBI.NonPredSize;
|
2010-10-26 08:02:21 +08:00
|
|
|
ToBBI.ExtraCost += FromBBI.ExtraCost;
|
2010-11-03 08:45:17 +08:00
|
|
|
ToBBI.ExtraCost2 += FromBBI.ExtraCost2;
|
2007-05-23 15:23:16 +08:00
|
|
|
FromBBI.NonPredSize = 0;
|
2010-10-26 08:02:21 +08:00
|
|
|
FromBBI.ExtraCost = 0;
|
2010-11-03 08:45:17 +08:00
|
|
|
FromBBI.ExtraCost2 = 0;
|
2007-06-06 18:16:17 +08:00
|
|
|
|
2007-06-12 06:26:22 +08:00
|
|
|
ToBBI.ClobbersPred |= FromBBI.ClobbersPred;
|
2007-06-09 09:03:43 +08:00
|
|
|
ToBBI.HasFallThrough = FromBBI.HasFallThrough;
|
2007-06-15 04:28:52 +08:00
|
|
|
ToBBI.IsAnalyzed = false;
|
|
|
|
FromBBI.IsAnalyzed = false;
|
2007-05-16 10:00:57 +08:00
|
|
|
}
|
2015-06-09 02:50:43 +08:00
|
|
|
|
|
|
|
FunctionPass *
|
|
|
|
llvm::createIfConverter(std::function<bool(const Function &)> Ftor) {
|
2016-06-13 00:13:55 +08:00
|
|
|
return new IfConverter(std::move(Ftor));
|
2015-06-09 02:50:43 +08:00
|
|
|
}
|