2016-12-07 10:42:15 +08:00
|
|
|
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
|
|
|
|
|
; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
|
|
|
|
|
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
|
2016-07-09 15:48:11 +08:00
|
|
|
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
|
2012-12-12 05:25:42 +08:00
|
|
|
|
2013-08-01 23:23:42 +08:00
|
|
|
; These tests check that fdiv is expanded correctly and also test that the
|
|
|
|
|
; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate
|
|
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|
|
; instruction groups.
|
2012-12-12 05:25:42 +08:00
|
|
|
|
2016-06-10 03:17:15 +08:00
|
|
|
; These test check that fdiv using unsafe_fp_math, coarse fp div, and IEEE754 fp div.
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}fdiv_f32:
|
2016-07-09 15:48:11 +08:00
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
|
2014-07-16 04:18:31 +08:00
|
|
|
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_div_scale_f32 [[NUM_SCALE:v[0-9]+]]
|
|
|
|
|
; GCN-DAG: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]
|
|
|
|
|
; GCN-DAG: v_rcp_f32_e32 [[NUM_RCP:v[0-9]+]], [[NUM_SCALE]]
|
|
|
|
|
|
|
|
|
|
; GCN: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
|
|
|
|
|
; GCN: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
|
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|
|
|
; GCN: v_fma_f32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]], [[NUM_RCP]]
|
|
|
|
|
; GCN: v_mul_f32_e32 [[C:v[0-9]+]], [[B]], [[DEN_SCALE]]
|
|
|
|
|
; GCN: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
|
|
|
|
|
; GCN: v_fma_f32 [[E:v[0-9]+]], [[D]], [[B]], [[C]]
|
|
|
|
|
; GCN: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
|
|
|
|
|
; GCN: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
|
|
|
|
|
; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
|
|
|
|
|
; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]],
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_f32(float addrspace(1)* %out, float %a, float %b) #0 {
|
2016-07-20 07:16:53 +08:00
|
|
|
entry:
|
|
|
|
|
%fdiv = fdiv float %a, %b
|
|
|
|
|
store float %fdiv, float addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-12-07 10:42:15 +08:00
|
|
|
; FUNC-LABEL: {{^}}fdiv_f32_denormals:
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
|
|
|
|
|
|
|
|
|
|
; GCN: v_div_scale_f32 [[NUM_SCALE:v[0-9]+]]
|
|
|
|
|
; GCN-DAG: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]
|
|
|
|
|
; GCN-DAG: v_rcp_f32_e32 [[NUM_RCP:v[0-9]+]], [[NUM_SCALE]]
|
|
|
|
|
|
|
|
|
|
; GCN-NOT: s_setreg
|
|
|
|
|
; GCN: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
|
|
|
|
|
; GCN: v_fma_f32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]], [[NUM_RCP]]
|
|
|
|
|
; GCN: v_mul_f32_e32 [[C:v[0-9]+]], [[B]], [[DEN_SCALE]]
|
|
|
|
|
; GCN: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
|
|
|
|
|
; GCN: v_fma_f32 [[E:v[0-9]+]], [[D]], [[B]], [[C]]
|
|
|
|
|
; GCN: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
|
|
|
|
|
; GCN-NOT: s_setreg
|
|
|
|
|
; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
|
|
|
|
|
; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]],
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_f32_denormals(float addrspace(1)* %out, float %a, float %b) #2 {
|
2016-12-07 10:42:15 +08:00
|
|
|
entry:
|
|
|
|
|
%fdiv = fdiv float %a, %b
|
|
|
|
|
store float %fdiv, float addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-07-20 07:16:53 +08:00
|
|
|
; FUNC-LABEL: {{^}}fdiv_25ulp_f32:
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_cndmask_b32
|
|
|
|
|
; GCN: v_mul_f32
|
|
|
|
|
; GCN: v_rcp_f32
|
|
|
|
|
; GCN: v_mul_f32
|
|
|
|
|
; GCN: v_mul_f32
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_25ulp_f32(float addrspace(1)* %out, float %a, float %b) #0 {
|
2016-07-20 07:16:53 +08:00
|
|
|
entry:
|
|
|
|
|
%fdiv = fdiv float %a, %b, !fpmath !0
|
|
|
|
|
store float %fdiv, float addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Use correct fdiv
|
|
|
|
|
; FUNC-LABEL: {{^}}fdiv_25ulp_denormals_f32:
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_fma_f32
|
|
|
|
|
; GCN: v_div_fmas_f32
|
|
|
|
|
; GCN: v_div_fixup_f32
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_25ulp_denormals_f32(float addrspace(1)* %out, float %a, float %b) #2 {
|
2016-07-20 07:16:53 +08:00
|
|
|
entry:
|
|
|
|
|
%fdiv = fdiv float %a, %b, !fpmath !0
|
|
|
|
|
store float %fdiv, float addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2016-06-10 03:17:15 +08:00
|
|
|
|
2016-07-20 07:16:53 +08:00
|
|
|
; FUNC-LABEL: {{^}}fdiv_fast_denormals_f32:
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
|
|
|
|
|
; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
|
|
|
|
|
; GCN-NOT: [[RESULT]]
|
|
|
|
|
; GCN: buffer_store_dword [[RESULT]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_fast_denormals_f32(float addrspace(1)* %out, float %a, float %b) #2 {
|
2014-07-16 04:18:31 +08:00
|
|
|
entry:
|
2016-07-20 07:16:53 +08:00
|
|
|
%fdiv = fdiv fast float %a, %b
|
|
|
|
|
store float %fdiv, float addrspace(1)* %out
|
2014-07-16 04:18:31 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-10 03:17:15 +08:00
|
|
|
; FUNC-LABEL: {{^}}fdiv_f32_fast_math:
|
2016-07-09 15:48:11 +08:00
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
|
2016-06-10 03:17:15 +08:00
|
|
|
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
|
|
|
|
|
; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
|
|
|
|
|
; GCN-NOT: [[RESULT]]
|
|
|
|
|
; GCN: buffer_store_dword [[RESULT]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_f32_fast_math(float addrspace(1)* %out, float %a, float %b) #0 {
|
2016-06-10 03:17:15 +08:00
|
|
|
entry:
|
2016-07-20 07:16:53 +08:00
|
|
|
%fdiv = fdiv fast float %a, %b
|
|
|
|
|
store float %fdiv, float addrspace(1)* %out
|
2016-06-10 03:17:15 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}fdiv_f32_arcp_math:
|
2016-07-09 15:48:11 +08:00
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
|
2016-06-10 03:17:15 +08:00
|
|
|
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
|
|
|
|
|
; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
|
|
|
|
|
; GCN-NOT: [[RESULT]]
|
|
|
|
|
; GCN: buffer_store_dword [[RESULT]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_f32_arcp_math(float addrspace(1)* %out, float %a, float %b) #0 {
|
2016-06-10 03:17:15 +08:00
|
|
|
entry:
|
2016-07-20 07:16:53 +08:00
|
|
|
%fdiv = fdiv arcp float %a, %b
|
|
|
|
|
store float %fdiv, float addrspace(1)* %out
|
2016-06-10 03:17:15 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
2014-07-16 04:18:31 +08:00
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}fdiv_v2f32:
|
2014-07-16 04:18:31 +08:00
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
|
|
|
|
|
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_div_scale_f32
|
|
|
|
|
; GCN: v_div_scale_f32
|
|
|
|
|
; GCN: v_div_scale_f32
|
|
|
|
|
; GCN: v_div_scale_f32
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
|
2016-07-20 07:16:53 +08:00
|
|
|
entry:
|
|
|
|
|
%fdiv = fdiv <2 x float> %a, %b
|
|
|
|
|
store <2 x float> %fdiv, <2 x float> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2016-06-10 03:17:15 +08:00
|
|
|
|
2016-07-20 07:16:53 +08:00
|
|
|
; FUNC-LABEL: {{^}}fdiv_ulp25_v2f32:
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_cmp_gt_f32
|
|
|
|
|
; GCN: v_cmp_gt_f32
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_ulp25_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
|
2013-07-23 09:48:18 +08:00
|
|
|
entry:
|
2016-07-20 07:16:53 +08:00
|
|
|
%fdiv = fdiv arcp <2 x float> %a, %b, !fpmath !0
|
|
|
|
|
store <2 x float> %fdiv, <2 x float> addrspace(1)* %out
|
2013-08-01 23:23:42 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-10 03:17:15 +08:00
|
|
|
; FUNC-LABEL: {{^}}fdiv_v2f32_fast_math:
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
|
|
|
|
|
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_rcp_f32
|
|
|
|
|
; GCN: v_rcp_f32
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_v2f32_fast_math(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
|
2016-06-10 03:17:15 +08:00
|
|
|
entry:
|
2016-07-20 07:16:53 +08:00
|
|
|
%fdiv = fdiv fast <2 x float> %a, %b
|
|
|
|
|
store <2 x float> %fdiv, <2 x float> addrspace(1)* %out
|
2016-06-10 03:17:15 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}fdiv_v2f32_arcp_math:
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
|
|
|
|
|
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_rcp_f32
|
|
|
|
|
; GCN: v_rcp_f32
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_v2f32_arcp_math(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
|
2016-06-10 03:17:15 +08:00
|
|
|
entry:
|
2016-07-20 07:16:53 +08:00
|
|
|
%fdiv = fdiv arcp <2 x float> %a, %b
|
|
|
|
|
store <2 x float> %fdiv, <2 x float> addrspace(1)* %out
|
2016-06-10 03:17:15 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-02 01:15:17 +08:00
|
|
|
; FUNC-LABEL: {{^}}fdiv_v4f32:
|
2014-07-16 04:18:31 +08:00
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_div_fixup_f32
|
|
|
|
|
; GCN: v_div_fixup_f32
|
|
|
|
|
; GCN: v_div_fixup_f32
|
|
|
|
|
; GCN: v_div_fixup_f32
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) #0 {
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-28 03:29:02 +08:00
|
|
|
%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
|
2015-02-28 05:17:42 +08:00
|
|
|
%a = load <4 x float>, <4 x float> addrspace(1) * %in
|
|
|
|
|
%b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
|
2013-08-01 23:23:42 +08:00
|
|
|
%result = fdiv <4 x float> %a, %b
|
|
|
|
|
store <4 x float> %result, <4 x float> addrspace(1)* %out
|
2012-12-12 05:25:42 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
2016-06-10 03:17:15 +08:00
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}fdiv_v4f32_fast_math:
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_rcp_f32
|
|
|
|
|
; GCN: v_rcp_f32
|
|
|
|
|
; GCN: v_rcp_f32
|
|
|
|
|
; GCN: v_rcp_f32
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_v4f32_fast_math(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) #0 {
|
2016-06-10 03:17:15 +08:00
|
|
|
%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
|
|
|
|
|
%a = load <4 x float>, <4 x float> addrspace(1) * %in
|
|
|
|
|
%b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
|
|
|
|
|
%result = fdiv fast <4 x float> %a, %b
|
|
|
|
|
store <4 x float> %result, <4 x float> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}fdiv_v4f32_arcp_math:
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
|
|
|
|
|
|
2016-12-07 10:42:15 +08:00
|
|
|
; GCN: v_rcp_f32
|
|
|
|
|
; GCN: v_rcp_f32
|
|
|
|
|
; GCN: v_rcp_f32
|
|
|
|
|
; GCN: v_rcp_f32
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @fdiv_v4f32_arcp_math(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) #0 {
|
2016-06-10 03:17:15 +08:00
|
|
|
%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
|
|
|
|
|
%a = load <4 x float>, <4 x float> addrspace(1) * %in
|
|
|
|
|
%b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
|
|
|
|
|
%result = fdiv arcp <4 x float> %a, %b
|
|
|
|
|
store <4 x float> %result, <4 x float> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2016-07-20 07:16:53 +08:00
|
|
|
|
2017-01-25 06:02:15 +08:00
|
|
|
attributes #0 = { nounwind "enable-unsafe-fp-math"="false" "target-features"="-fp32-denormals,-flat-for-global" }
|
|
|
|
|
attributes #1 = { nounwind "enable-unsafe-fp-math"="true" "target-features"="-fp32-denormals,-flat-for-global" }
|
|
|
|
|
attributes #2 = { nounwind "enable-unsafe-fp-math"="false" "target-features"="+fp32-denormals,-flat-for-global" }
|
2016-07-20 07:16:53 +08:00
|
|
|
|
|
|
|
|
!0 = !{float 2.500000e+00}
|