2019-09-13 12:03:32 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
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;
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; The test case check that RV64 could handle the stack adjustment offset exceed
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; 32-bit.
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define void @foo() nounwind {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore
We would like to split the SP adjustment to reduce the instructions in
prologue and epilogue as the following case. In this way, the offset of
the callee saved register could fit in a single store.
add sp,sp,-2032
sw ra,2028(sp)
sw s0,2024(sp)
sw s1,2020(sp)
sw s3,2012(sp)
sw s4,2008(sp)
add sp,sp,-64
Differential Revision: https://reviews.llvm.org/D68011
llvm-svn: 373688
2019-10-04 10:00:57 +08:00
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; CHECK-NEXT: addi sp, sp, -2032
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2020-12-10 03:41:19 +08:00
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; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
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2019-09-13 12:03:32 +08:00
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; CHECK-NEXT: lui a0, 95
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; CHECK-NEXT: addiw a0, a0, 1505
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; CHECK-NEXT: slli a0, a0, 13
|
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore
We would like to split the SP adjustment to reduce the instructions in
prologue and epilogue as the following case. In this way, the offset of
the callee saved register could fit in a single store.
add sp,sp,-2032
sw ra,2028(sp)
sw s0,2024(sp)
sw s1,2020(sp)
sw s3,2012(sp)
sw s4,2008(sp)
add sp,sp,-64
Differential Revision: https://reviews.llvm.org/D68011
llvm-svn: 373688
2019-10-04 10:00:57 +08:00
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; CHECK-NEXT: addi a0, a0, -2000
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2019-09-13 12:03:32 +08:00
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; CHECK-NEXT: sub sp, sp, a0
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; CHECK-NEXT: addi a0, sp, 16
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2020-12-10 03:41:19 +08:00
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; CHECK-NEXT: call baz@plt
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2019-09-13 12:03:32 +08:00
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; CHECK-NEXT: lui a0, 95
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; CHECK-NEXT: addiw a0, a0, 1505
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; CHECK-NEXT: slli a0, a0, 13
|
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore
We would like to split the SP adjustment to reduce the instructions in
prologue and epilogue as the following case. In this way, the offset of
the callee saved register could fit in a single store.
add sp,sp,-2032
sw ra,2028(sp)
sw s0,2024(sp)
sw s1,2020(sp)
sw s3,2012(sp)
sw s4,2008(sp)
add sp,sp,-64
Differential Revision: https://reviews.llvm.org/D68011
llvm-svn: 373688
2019-10-04 10:00:57 +08:00
|
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; CHECK-NEXT: addi a0, a0, -2000
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2019-09-13 12:03:32 +08:00
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; CHECK-NEXT: add sp, sp, a0
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2020-12-10 03:41:19 +08:00
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; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
|
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore
We would like to split the SP adjustment to reduce the instructions in
prologue and epilogue as the following case. In this way, the offset of
the callee saved register could fit in a single store.
add sp,sp,-2032
sw ra,2028(sp)
sw s0,2024(sp)
sw s1,2020(sp)
sw s3,2012(sp)
sw s4,2008(sp)
add sp,sp,-64
Differential Revision: https://reviews.llvm.org/D68011
llvm-svn: 373688
2019-10-04 10:00:57 +08:00
|
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; CHECK-NEXT: addi sp, sp, 2032
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2019-09-13 12:03:32 +08:00
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; CHECK-NEXT: ret
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entry:
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%w = alloca [100000000 x { fp128, fp128 }], align 16
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%arraydecay = getelementptr inbounds [100000000 x { fp128, fp128 }], [100000000 x { fp128, fp128 }]* %w, i64 0, i64 0
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call void @baz({ fp128, fp128 }* nonnull %arraydecay)
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ret void
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}
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declare void @baz({ fp128, fp128 }*)
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