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llvm-project/llvm/test/CodeGen/Hexagon/newvaluestore.ll

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[Hexagon] Enable the post-RA scheduler The aggressive anti-dependency breaker can rename the restored callee- saved registers. To prevent this, mark these registers are live on all paths to the return/tail-call instructions, and add implicit use operands for them to these instructions. llvm-svn: 270898
2016-05-27 03:44:28 +08:00
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that we generate new value store.
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
@i = global i32 0, align 4
[Hexagon] Enable the post-RA scheduler The aggressive anti-dependency breaker can rename the restored callee- saved registers. To prevent this, mark these registers are live on all paths to the return/tail-call instructions, and add implicit use operands for them to these instructions. llvm-svn: 270898
2016-05-27 03:44:28 +08:00
define i32 @main(i32 %x, i32* %p) nounwind {
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
entry:
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. llvm-svn: 224952
2014-12-30 04:44:51 +08:00
; CHECK: memw(r{{[0-9]+}}+#{{[0-9]+}}) = r{{[0-9]+}}.new
[Hexagon] Enable the post-RA scheduler The aggressive anti-dependency breaker can rename the restored callee- saved registers. To prevent this, mark these registers are live on all paths to the return/tail-call instructions, and add implicit use operands for them to these instructions. llvm-svn: 270898
2016-05-27 03:44:28 +08:00
%t0 = load i32, i32* @i, align 4
store i32 %t0, i32* %p, align 4
ret i32 %x
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
}