forked from OSchip/llvm-project
111 lines
5.1 KiB
LLVM
111 lines
5.1 KiB
LLVM
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; RUN: llc -march=hexagon -mcpu=hexagonv55 -filetype=obj -o /dev/null
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; REQUIRES: asserts
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; There should be no output (nothing on stderr).
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; Due to a bug in converting a dot-new branch into a dot-old one, opcodes
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; with branch prediction bits were selected even if the architecture did
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; not support them. On V55-, the dot-old branch opcodes are J2_jumpt and
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; J2_jumpf (and a pair of J2_jumpr*), whereas J2_jumptpt could have been
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; a result of the conversion to dot-old. This would fail a verification
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; check in the MC code emitter, so make sure it does not happen.
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target triple = "hexagon"
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define void @fred(i16* nocapture %a0, i16* nocapture %a1, i16* nocapture %a2, i16 signext %a3, i16* %a4, i16 signext %a5, i16 signext %a6, i16 signext %a7, i32 %a8, i16 signext %a9, i16 signext %a10) local_unnamed_addr #0 {
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b11:
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%v12 = sext i16 %a5 to i32
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%v13 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v12)
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%v14 = tail call i32 @llvm.hexagon.A2.sxth(i32 2)
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%v15 = tail call i32 @llvm.hexagon.A2.sxth(i32 undef)
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%v16 = tail call i32 @llvm.hexagon.A2.sath(i32 undef)
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%v17 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v16)
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%v18 = tail call i32 @llvm.hexagon.A2.aslh(i32 undef)
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%v19 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v18, i32 %v14)
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%v20 = tail call i32 @llvm.hexagon.A2.asrh(i32 %v19)
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%v21 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v20)
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%v22 = tail call i32 @llvm.hexagon.A2.sub(i32 %v17, i32 %v21)
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%v23 = tail call i32 @llvm.hexagon.A2.sath(i32 %v22)
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%v24 = select i1 undef, i32 undef, i32 %v23
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%v25 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v24)
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%v26 = tail call i32 @llvm.hexagon.A2.sub(i32 %v13, i32 %v25)
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%v27 = tail call i32 @llvm.hexagon.A2.sath(i32 %v26)
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%v28 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v27)
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%v29 = tail call i32 @llvm.hexagon.A2.sub(i32 %v28, i32 %v14)
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%v30 = tail call i32 @llvm.hexagon.A2.sath(i32 %v29)
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%v31 = shl i32 %v30, 16
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%v32 = icmp sgt i32 undef, %v31
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%v33 = select i1 %v32, i32 %v30, i32 undef
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%v34 = trunc i32 %v33 to i16
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%v35 = trunc i32 %v24 to i16
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call void @foo(i16* nonnull undef, i32* nonnull undef, i16* %a4, i16 signext %v35, i16 signext %v34, i16 signext 2) #4
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%v36 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v18, i32 undef)
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%v37 = call i32 @llvm.hexagon.A2.asrh(i32 %v36)
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%v38 = call i32 @llvm.hexagon.A2.sub(i32 %v13, i32 undef)
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%v39 = call i32 @llvm.hexagon.A2.sath(i32 %v38)
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%v40 = call i32 @llvm.hexagon.A2.sxth(i32 %v39)
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%v41 = call i32 @llvm.hexagon.A2.sub(i32 %v40, i32 %v14)
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%v42 = call i32 @llvm.hexagon.A2.sath(i32 %v41)
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%v43 = select i1 undef, i32 %v42, i32 %v37
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%v44 = trunc i32 %v43 to i16
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call void @foo(i16* nonnull undef, i32* nonnull undef, i16* %a4, i16 signext undef, i16 signext %v44, i16 signext 2) #4
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%v45 = call i32 @llvm.hexagon.A2.sath(i32 undef)
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%v46 = select i1 undef, i32 undef, i32 %v45
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%v47 = trunc i32 %v46 to i16
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call void @foo(i16* nonnull undef, i32* nonnull undef, i16* %a4, i16 signext %v47, i16 signext undef, i16 signext 2) #4
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%v48 = call i32 @llvm.hexagon.A2.sub(i32 undef, i32 %v15)
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%v49 = call i32 @llvm.hexagon.A2.sath(i32 %v48)
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%v50 = trunc i32 %v49 to i16
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store i16 %v50, i16* undef, align 2
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store i16 %a3, i16* %a0, align 2
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%v51 = sext i16 %a10 to i32
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%v52 = call i32 @llvm.hexagon.A2.sxth(i32 %v51)
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%v53 = call i32 @llvm.hexagon.A2.add(i32 undef, i32 %v52)
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%v54 = call i32 @llvm.hexagon.A2.sath(i32 %v53)
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%v55 = trunc i32 %v54 to i16
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store i16 %v55, i16* %a1, align 2
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store i16 %a7, i16* %a2, align 2
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%v56 = sext i16 %a9 to i32
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%v57 = call i32 @llvm.hexagon.A2.sxth(i32 %v56)
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br i1 undef, label %b58, label %b62
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b58: ; preds = %b11
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%v59 = call i32 @llvm.hexagon.A2.add(i32 %v57, i32 %v52)
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%v60 = call i32 @llvm.hexagon.A2.sath(i32 %v59)
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%v61 = trunc i32 %v60 to i16
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store i16 %v61, i16* %a1, align 2
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br label %b63
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b62: ; preds = %b11
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br label %b63
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b63: ; preds = %b62, %b58
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%v64 = phi i16 [ undef, %b58 ], [ %a9, %b62 ]
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%v65 = icmp slt i16 undef, %v64
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br i1 %v65, label %b66, label %b67
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b66: ; preds = %b63
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br i1 undef, label %b67, label %b68
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b67: ; preds = %b66, %b63
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store i16 0, i16* %a2, align 2
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br label %b68
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b68: ; preds = %b67, %b66
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ret void
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}
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declare i32 @llvm.hexagon.A2.sath(i32) #2
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declare i32 @llvm.hexagon.A2.add(i32, i32) #2
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declare i32 @llvm.hexagon.A2.sxth(i32) #2
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declare i32 @llvm.hexagon.A2.sub(i32, i32) #2
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declare i32 @llvm.hexagon.A2.asrh(i32) #2
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declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2
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declare i32 @llvm.hexagon.A2.aslh(i32) #2
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declare void @foo(i16*, i32*, i16*, i16 signext, i16 signext, i16 signext) local_unnamed_addr #3
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attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }
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attributes #1 = { argmemonly nounwind }
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attributes #2 = { nounwind readnone }
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attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }
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attributes #4 = { nounwind optsize }
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