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llvm-project/clang/test/CodeGen/builtins-arm64.c

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ARM64: initial clang support commit. This adds Clang support for the ARM64 backend. There are definitely still some rough edges, so please bring up any issues you see with this patch. As with the LLVM commit though, we think it'll be more useful for merging with AArch64 from within the tree. llvm-svn: 205100
2014-03-29 23:09:45 +08:00
// RUN: %clang_cc1 -triple arm64-apple-ios -O3 -emit-llvm -o - %s | FileCheck %s
void f0(void *a, void *b) {
__clear_cache(a,b);
// CHECK: call {{.*}} @__clear_cache
}
AArch64: Support for __builtin_arm_rbit() and __builtin_arm_rbit64(). __builtin_arm_rbit() and __builtin_arm_rbit64(). rdar://9283021 llvm-svn: 211060
2014-06-17 05:56:02 +08:00
// CHECK: call {{.*}} @llvm.aarch64.rbit.i32(i32 %a)
AArch64: Fix silly think-o in tests. rdar://9283021 llvm-svn: 211064
2014-06-17 06:18:26 +08:00
unsigned rbit(unsigned a) {
return __builtin_arm_rbit(a);
AArch64: Support for __builtin_arm_rbit() and __builtin_arm_rbit64(). __builtin_arm_rbit() and __builtin_arm_rbit64(). rdar://9283021 llvm-svn: 211060
2014-06-17 05:56:02 +08:00
}
// CHECK: call {{.*}} @llvm.aarch64.rbit.i64(i64 %a)
AArch64: Fix silly think-o in tests. rdar://9283021 llvm-svn: 211064
2014-06-17 06:18:26 +08:00
unsigned long long rbit64(unsigned long long a) {
return __builtin_arm_rbit64(a);
AArch64: Support for __builtin_arm_rbit() and __builtin_arm_rbit64(). __builtin_arm_rbit() and __builtin_arm_rbit64(). rdar://9283021 llvm-svn: 211060
2014-06-17 05:56:02 +08:00
}
Add test cases for AArch64 hints codegen llvm-svn: 212909
2014-07-14 00:17:30 +08:00
void hints() {
ARM: Implement __builtin_arm_nop intrinsic This patch implements __builtin_arm_nop intrinsic for AArch32 and AArch64, which generates hint 0x0, the alias of NOP instruction. This intrinsic is necessary to implement ACLE __nop intrinsic. Differential Revision: http://reviews.llvm.org/D4495 llvm-svn: 212947
2014-07-14 23:20:09 +08:00
__builtin_arm_nop(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 0)
Add test cases for AArch64 hints codegen llvm-svn: 212909
2014-07-14 00:17:30 +08:00
__builtin_arm_yield(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 1)
__builtin_arm_wfe(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 2)
__builtin_arm_wfi(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 3)
__builtin_arm_sev(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 4)
__builtin_arm_sevl(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 5)
}
Port memory barriers intrinsics to AArch64 Memory barrier __builtin_arm_[dmb, dsb, isb] intrinsics are required to implement their corresponding ACLE and MSVC intrinsics. This patch ports ARM dmb, dsb, isb intrinsic to AArch64. Requires LLVM r213247. Differential Revision: http://reviews.llvm.org/D4521 llvm-svn: 213250
2014-07-17 18:52:06 +08:00
void barriers() {
__builtin_arm_dmb(1); //CHECK: call {{.*}} @llvm.aarch64.dmb(i32 1)
__builtin_arm_dsb(2); //CHECK: call {{.*}} @llvm.aarch64.dsb(i32 2)
__builtin_arm_isb(3); //CHECK: call {{.*}} @llvm.aarch64.isb(i32 3)
}
AArch64: Prefetch intrinsic llvm-svn: 215569
2014-08-14 03:18:20 +08:00
void prefetch() {
__builtin_arm_prefetch(0, 1, 2, 0, 1); // pstl3keep
// CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 1, i32 1, i32 1)
__builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1keep
// CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 0, i32 1)
__builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1strm
// CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 0, i32 1)
__builtin_arm_prefetch(0, 0, 0, 0, 0); // plil1keep
// CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 3, i32 0)
}