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llvm-project/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll

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Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81290
2009-09-09 07:54:48 +08:00
; RUN: llc < %s -march=x86
Add a cpu to try to bring back the atom bots. llvm-svn: 182734
2013-05-27 21:22:52 +08:00
; RUN: llc -pre-RA-sched=source < %s -march=x86 -mcpu=corei7 | FileCheck %s --check-prefix=SOURCE-SCHED
Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g. vr1024 = extract_subreg vr1025, 1 ... vr1024 = mov8rr AH If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH. llvm-svn: 56118
2008-09-12 04:07:10 +08:00
; PR2748
@g_73 = external global i32 ; <i32*> [#uses=1]
@g_5 = external global i32 ; <i32*> [#uses=1]
define i32 @func_44(i16 signext %p_46) nounwind {
entry:
Track IR ordering of SelectionDAG nodes 4/4. Unit test cases for -pre-RA-sched=source. llvm-svn: 182706
2013-05-25 11:26:51 +08:00
; SOURCE-SCHED: subl
; SOURCE-SCHED: movl
; SOURCE-SCHED: sarl
; SOURCE-SCHED: cmpl
; SOURCE-SCHED: setg
; SOURCE-SCHED: movzbl
; SOURCE-SCHED: movb
; SOURCE-SCHED: xorl
; SOURCE-SCHED: subl
; SOURCE-SCHED: testb
; SOURCE-SCHED: jne
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* @g_5, align 4 ; <i32> [#uses=1]
Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g. vr1024 = extract_subreg vr1025, 1 ... vr1024 = mov8rr AH If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH. llvm-svn: 56118
2008-09-12 04:07:10 +08:00
%1 = ashr i32 %0, 1 ; <i32> [#uses=1]
%2 = icmp sgt i32 %1, 1 ; <i1> [#uses=1]
%3 = zext i1 %2 to i32 ; <i32> [#uses=1]
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%4 = load i32, i32* @g_73, align 4 ; <i32> [#uses=1]
Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g. vr1024 = extract_subreg vr1025, 1 ... vr1024 = mov8rr AH If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH. llvm-svn: 56118
2008-09-12 04:07:10 +08:00
%5 = zext i16 %p_46 to i64 ; <i64> [#uses=1]
%6 = sub i64 0, %5 ; <i64> [#uses=1]
%7 = trunc i64 %6 to i8 ; <i8> [#uses=2]
%8 = trunc i32 %4 to i8 ; <i8> [#uses=2]
%9 = icmp eq i8 %8, 0 ; <i1> [#uses=1]
br i1 %9, label %bb11, label %bb12
bb11: ; preds = %entry
%10 = urem i8 %7, %8 ; <i8> [#uses=1]
br label %bb12
bb12: ; preds = %bb11, %entry
%.014.in = phi i8 [ %10, %bb11 ], [ %7, %entry ] ; <i8> [#uses=1]
%11 = icmp ne i8 %.014.in, 0 ; <i1> [#uses=1]
%12 = zext i1 %11 to i32 ; <i32> [#uses=1]
%13 = tail call i32 (...)* @func_48( i32 %12, i32 %3, i32 0 ) nounwind ; <i32> [#uses=0]
ret i32 undef
}
declare i32 @func_48(...)