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llvm-project/llvm/test/CodeGen/Hexagon/dadd.ll

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Hexagon V5 FP Support. llvm-svn: 156568
2012-05-11 04:20:25 +08:00
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Check that we generate double precision floating point add in V5.
[Hexagon] Replacing old fadd/fsub instructions and updating references. llvm-svn: 226176
2015-01-16 00:30:07 +08:00
; CHECK: call __hexagon_adddf3
Hexagon V5 FP Support. llvm-svn: 156568
2012-05-11 04:20:25 +08:00
define i32 @main() nounwind {
entry:
%a = alloca double, align 8
%b = alloca double, align 8
%c = alloca double, align 8
store double 1.540000e+01, double* %a, align 8
store double 9.100000e+00, double* %b, align 8
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load double, double* %a, align 8
%1 = load double, double* %b, align 8
Hexagon V5 FP Support. llvm-svn: 156568
2012-05-11 04:20:25 +08:00
%add = fadd double %0, %1
store double %add, double* %c, align 8
ret i32 0
}