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llvm-project/llvm/test/CodeGen/ARM/2011-10-26-memset-inline.ll

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Make sure short memsets on ARM lower to stores, even when optimizing for size. llvm-svn: 143055
2011-10-27 04:56:52 +08:00
; Make sure short memsets on ARM lower to stores, even when optimizing for size.
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. llvm-svn: 144102
2011-11-09 02:56:23 +08:00
; RUN: llc -march=arm < %s | FileCheck %s -check-prefix=CHECK-GENERIC
; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s -check-prefix=CHECK-UNALIGNED
Make sure short memsets on ARM lower to stores, even when optimizing for size. llvm-svn: 143055
2011-10-27 04:56:52 +08:00
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios5.0.0"
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. llvm-svn: 144102
2011-11-09 02:56:23 +08:00
; CHECK-GENERIC: strb
Fix broken CHECK lines llvm-svn: 201479
2014-02-16 15:31:05 +08:00
; CHECK-GENERIC-NEXT: strb
; CHECK-GENERIC-NEXT: strb
; CHECK-GENERIC-NEXT: strb
; CHECK-GENERIC-NEXT: strb
CriticalAntiDepBreaker is no longer needed for armv7 scheduling. This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. llvm-svn: 191348
2013-09-25 08:26:16 +08:00
; CHECK-UNALIGNED: strb
; CHECK-UNALIGNED: str
Make sure short memsets on ARM lower to stores, even when optimizing for size. llvm-svn: 143055
2011-10-27 04:56:52 +08:00
define void @foo(i8* nocapture %c) nounwind optsize {
entry:
call void @llvm.memset.p0i8.i64(i8* %c, i8 -1, i64 5, i32 1, i1 false)
ret void
}
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind