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llvm-project/llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst

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[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-09 00:50:11 +08:00
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[AMDGPU][DOC][NFC] Updated GFX10 assembler syntax description The description has been updated to reflect AMDGPU MC changes: - enabled literals for src0 of v_fmaak_f*, v_fmamk_f*, v_madak_f32, v_madmk_f32; - enabled global_atomic_fcmpswap and global_atomic_fcmpswap_x2; - enabled dlc with flat_atomic* and global_atomic_*. Bug fixing and improvements: - enabled s_wait_idle; - enabled s_waitcnt_depctr; - added description of s_waitcnt_depctr syntactic sugar; - disabled SYSMSG_OP_HOST_TRAP_ACK (it is not supported on GFX10); - corrected description of lgkmcnt (accept values from 0 to 63).
2022-04-12 20:16:20 +08:00
.. _amdgpu_synid_gfx10_soffset_c40a5a:
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-09 00:50:11 +08:00
soffset
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 22:16:22 +08:00
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[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-09 00:50:11 +08:00
An offset added to the base address to get memory address.
* If offset is specified as a register, it supplies an unsigned byte offset.
* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`