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llvm-project/llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst

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[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX9 subtargets: - gfx900; - gfx902; - gfx904; - gfx906; - gfx908; - gfx909.
2019-12-25 22:51:53 +08:00
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====================================================================================
Syntax of gfx904 Instructions
====================================================================================
.. contents::
:local:
Introduction
============
This document describes the syntax of *instructions specific to gfx904*.
For a description of other gfx904 instructions see :doc:`Syntax of Core GFX9 Instructions<AMDGPUAsmGFX9>`.
Notation
========
Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
[llvm] NFC: fix trivial typos in documents Reviewers: hans, Jim Reviewed By: Jim Subscribers: jvesely, nhaehnle, mgorny, arphaman, bmahjour, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73017
2020-01-22 11:30:57 +08:00
Overview
========
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX9 subtargets: - gfx900; - gfx902; - gfx904; - gfx906; - gfx908; - gfx909.
2019-12-25 22:51:53 +08:00
An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
Instructions
============
VOP3P
-----------------------
.. parsed-literal::
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 22:16:22 +08:00
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_fma_mix_f32 :ref:`vdst<amdgpu_synid_gfx904_vdst>`, :ref:`src0<amdgpu_synid_gfx904_src>`::ref:`m<amdgpu_synid_gfx904_m>`::ref:`fx<amdgpu_synid_gfx904_fx_operand>`, :ref:`src1<amdgpu_synid_gfx904_src_1>`::ref:`m<amdgpu_synid_gfx904_m>`::ref:`fx<amdgpu_synid_gfx904_fx_operand>`, :ref:`src2<amdgpu_synid_gfx904_src_1>`::ref:`m<amdgpu_synid_gfx904_m>`::ref:`fx<amdgpu_synid_gfx904_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid_gfx904_vdst>`, :ref:`src0<amdgpu_synid_gfx904_src>`::ref:`m<amdgpu_synid_gfx904_m>`::ref:`fx<amdgpu_synid_gfx904_fx_operand>`, :ref:`src1<amdgpu_synid_gfx904_src_1>`::ref:`m<amdgpu_synid_gfx904_m>`::ref:`fx<amdgpu_synid_gfx904_fx_operand>`, :ref:`src2<amdgpu_synid_gfx904_src_1>`::ref:`m<amdgpu_synid_gfx904_m>`::ref:`fx<amdgpu_synid_gfx904_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid_gfx904_vdst>`, :ref:`src0<amdgpu_synid_gfx904_src>`::ref:`m<amdgpu_synid_gfx904_m>`::ref:`fx<amdgpu_synid_gfx904_fx_operand>`, :ref:`src1<amdgpu_synid_gfx904_src_1>`::ref:`m<amdgpu_synid_gfx904_m>`::ref:`fx<amdgpu_synid_gfx904_fx_operand>`, :ref:`src2<amdgpu_synid_gfx904_src_1>`::ref:`m<amdgpu_synid_gfx904_m>`::ref:`fx<amdgpu_synid_gfx904_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX9 subtargets: - gfx900; - gfx902; - gfx904; - gfx906; - gfx908; - gfx909.
2019-12-25 22:51:53 +08:00
.. |---| unicode:: U+02014 .. em dash
.. toctree::
:hidden:
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 22:16:22 +08:00
gfx904_fx_operand
gfx904_m
gfx904_src
gfx904_src_1
gfx904_vdst