2017-05-12 00:54:23 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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2017-11-30 21:39:10 +08:00
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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2017-05-12 00:54:23 +08:00
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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2017-11-30 21:39:10 +08:00
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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2017-05-12 00:54:23 +08:00
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i16 0, align 2
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_llequs:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0: # %entry
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i16 %a, %b
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%conv3 = zext i1 %cmp to i64
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ret i64 %conv3
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_llequs_sext:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0: # %entry
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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2017-09-22 19:50:25 +08:00
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: neg r3, r3
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i16 %a, %b
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%conv3 = sext i1 %cmp to i64
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ret i64 %conv3
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llequs_z(i16 zeroext %a) {
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; CHECK-LABEL: test_llequs_z:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0: # %entry
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i16 %a, 0
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%conv2 = zext i1 %cmp to i64
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ret i64 %conv2
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llequs_sext_z(i16 zeroext %a) {
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; CHECK-LABEL: test_llequs_sext_z:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0: # %entry
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: cntlzw r3, r3
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2017-09-22 19:50:25 +08:00
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: neg r3, r3
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i16 %a, 0
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%conv2 = sext i1 %cmp to i64
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ret i64 %conv2
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}
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; Function Attrs: norecurse nounwind
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define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_llequs_store:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0: # %entry
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: xor r3, r3, r4
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: sth r3, 0(r4)
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i16 %a, %b
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%conv3 = zext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_llequs_sext_store:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0: # %entry
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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2018-07-05 02:54:25 +08:00
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; CHECK-NEXT: xor r3, r3, r4
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: cntlzw r3, r3
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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2017-09-22 19:50:25 +08:00
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: neg r3, r3
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: sth r3, 0(r4)
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i16 %a, %b
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%conv3 = sext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_llequs_z_store(i16 zeroext %a) {
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; CHECK-LABEL: test_llequs_z_store:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0: # %entry
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: cntlzw r3, r3
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: srwi r3, r3, 5
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: sth r3, 0(r4)
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i16 %a, 0
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%conv2 = zext i1 %cmp to i16
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store i16 %conv2, i16* @glob, align 2
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_llequs_sext_z_store(i16 zeroext %a) {
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; CHECK-LABEL: test_llequs_sext_z_store:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0: # %entry
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: cntlzw r3, r3
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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2017-09-22 19:50:25 +08:00
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: neg r3, r3
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2018-11-17 03:24:23 +08:00
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; CHECK-NEXT: sth r3, 0(r4)
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2017-05-12 00:54:23 +08:00
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i16 %a, 0
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%conv2 = sext i1 %cmp to i16
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store i16 %conv2, i16* @glob, align 2
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ret void
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}
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