2011-04-16 05:51:11 +08:00
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//===-- MipsMachineFunctionInfo.h - Private data used for Mips ----*- C++ -*-=//
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2007-07-12 06:44:21 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-07-12 06:44:21 +08:00
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-07-12 06:44:21 +08:00
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//
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// This file declares the Mips specific subclass of MachineFunctionInfo.
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-07-12 06:44:21 +08:00
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#ifndef MIPS_MACHINE_FUNCTION_INFO_H
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#define MIPS_MACHINE_FUNCTION_INFO_H
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2012-06-14 09:15:36 +08:00
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#include "MipsSubtarget.h"
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#include "llvm/CodeGen/MachineFunction.h"
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2007-08-28 13:04:41 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2012-06-14 09:15:36 +08:00
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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2012-03-18 02:46:09 +08:00
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#include <utility>
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2007-07-12 06:44:21 +08:00
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namespace llvm {
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/// MipsFunctionInfo - This class is derived from MachineFunction private
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/// Mips target-specific information for each MachineFunction.
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class MipsFunctionInfo : public MachineFunctionInfo {
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2011-12-20 10:50:00 +08:00
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virtual void anchor();
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2007-07-12 06:44:21 +08:00
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2011-06-21 08:40:49 +08:00
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MachineFunction& MF;
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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/// SRetReturnReg - Some subtargets require that sret lowering includes
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/// returning the value of the returned struct in a register. This field
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/// holds the virtual register into which the sret argument is passed.
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unsigned SRetReturnReg;
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2009-06-04 04:30:14 +08:00
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/// GlobalBaseReg - keeps track of the virtual register initialized for
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/// use as the global base register. This is used for PIC in some PIC
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/// relocation models.
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unsigned GlobalBaseReg;
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2012-10-28 14:02:37 +08:00
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/// Mips16SPAliasReg - keeps track of the virtual register initialized for
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/// use as an alias for SP for use in load/store of halfword/byte from/to
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/// the stack
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unsigned Mips16SPAliasReg;
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2010-04-17 22:41:14 +08:00
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/// VarArgsFrameIndex - FrameIndex for start of varargs area.
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int VarArgsFrameIndex;
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2012-03-28 03:08:42 +08:00
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bool EmitNOAT;
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2007-07-12 06:44:21 +08:00
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public:
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2010-09-28 18:06:53 +08:00
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MipsFunctionInfo(MachineFunction& MF)
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2012-10-28 14:02:37 +08:00
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: MF(MF), SRetReturnReg(0), GlobalBaseReg(0), Mips16SPAliasReg(0),
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VarArgsFrameIndex(0), EmitNOAT(false)
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2007-07-12 06:44:21 +08:00
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{}
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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unsigned getSRetReturnReg() const { return SRetReturnReg; }
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void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
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2009-06-04 04:30:14 +08:00
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2012-02-25 06:34:47 +08:00
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bool globalBaseRegSet() const;
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unsigned getGlobalBaseReg();
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2010-04-17 22:41:14 +08:00
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2012-10-28 14:02:37 +08:00
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bool mips16SPAliasRegSet() const;
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unsigned getMips16SPAliasReg();
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2010-04-17 22:41:14 +08:00
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int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
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void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
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2011-05-20 09:17:58 +08:00
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2012-03-28 03:08:42 +08:00
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bool getEmitNOAT() const { return EmitNOAT; }
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void setEmitNOAT() { EmitNOAT = true; }
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2007-07-12 06:44:21 +08:00
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};
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} // end of namespace llvm
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2007-08-28 13:04:41 +08:00
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#endif // MIPS_MACHINE_FUNCTION_INFO_H
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