[ARM] [Assembler] Support negative immediates for A32, T32 and T16
Summary:
To support negative immediates for certain arithmetic instructions, the
instruction is converted to the inverse instruction with a negated (or inverted)
immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD
instruction. However, "SUB r0, r1, #1" is equivalent.
These conversions are different from instruction aliases. An alias maps
several assembler instructions onto one encoding. A conversion, however, maps
an *invalid* instruction--e.g. with an immediate that cannot be represented in
the encoding--to a different (but equivalent) instruction.
Several instructions with negative immediates were being converted already, but
this was not systematically tested, nor did it cover all instructions.
This patch implements all possible substitutions for ARM, Thumb1 and
Thumb2 assembler and adds tests. It also adds a feature flag
(-mattr=+no-neg-immediates) to turn these substitutions off. This is
helpful for users who want their code to assemble to exactly what they
wrote.
Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin
Reviewed By: javed.absar
Subscribers: aadg, aemerson, llvm-commits
Differential Revision: https://reviews.llvm.org/D30571
llvm-svn: 298380
2017-03-21 22:59:17 +08:00
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# RUN: llvm-mc -triple armv7 %s -show-encoding | FileCheck %s
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# RUN: not llvm-mc -triple armv7 %s -show-encoding -mattr=+no-neg-immediates 2>&1 | FileCheck %s -check-prefix=CHECK-DISABLED
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.arm
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ADC r0, r1, #0xFFFFFF00
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# CHECK: sbc r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ADC
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ADC r0, r1, #0xFFFFFE03
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# CHECK: sbc r0, r1, #508
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ADC
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ADD r0, r1, #0xFFFFFF01
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# CHECK: sub r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ADD
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AND r0, r1, #0xFFFFFF00
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# CHECK: bic r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: AND
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BIC r0, r1, #0xFFFFFF00
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# CHECK: and r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: BIC
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CMP r0, #0xFFFFFF01
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# CHECK: cmn r0, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: CMP
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CMN r0, #0xFFFFFF01
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# CHECK: cmp r0, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: CMN
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MOV r0, #0xFFFFFF00
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# CHECK: mvn r0, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: MOV
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MVN r0, #0xFFFFFF00
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# CHECK: mov r0, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: MVN
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SBC r0, r1, #0xFFFFFF00
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# CHECK: adc r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: SBC
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SUB r0, r1, #0xFFFFFF01
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# CHECK: add r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: SUB
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.thumb
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ADC r0, r1, #0xFFFFFF00
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# CHECK: sbc r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ADC
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ADC r0, r1, #0xFFFF00FF
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# CHECK: sbc r0, r1, #65280
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ADC
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ADC r0, r1, #0xFFFEFFFE
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# CHECK: sbc r0, r1, #65537 @ encoding: [0x61,0xf1,0x01,0x10]
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ADC
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ADC r0, r1, #0xFEFFFEFF
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# CHECK: sbc r0, r1, #16777472 @ encoding: [0x61,0xf1,0x01,0x20]
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ADC
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ADD.W r0, r0, #0xFFFFFF01
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# CHECK: sub.w r0, r0, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ADD.W
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ADD.W r0, r0, #0xFF01FF02
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# CHECK: sub.w r0, r0, #16646398 @ encoding: [0xa0,0xf1,0xfe,0x10]
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ADD.W
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ADDW r0, r1, #0xFFFFFF01
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# CHECK: subw r0, r1, #255 @ encoding: [0xa1,0xf2,0xff,0x00]
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ADDW
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ADD.W r0, r1, #0xFFFFFF01
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# CHECK: sub.w r0, r1, #255 @ encoding: [0xa1,0xf1,0xff,0x00]
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ADD.W
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AND r0, r1, #0xFFFFFF00
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: AND
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# CHECK: bic r0, r1, #255
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AND r0, r1, #0xFEFFFEFF
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# CHECK: bic r0, r1, #16777472 @ encoding: [0x21,0xf0,0x01,0x20]
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: AND
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BIC r0, r1, #0xFFFFFF00
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# CHECK: and r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: BIC
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BIC r0, r1, #0xFEFFFEFF
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# CHECK: and r0, r1, #16777472 @ encoding: [0x01,0xf0,0x01,0x20]
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: BIC
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2017-05-05 19:31:25 +08:00
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ORR r0, r1, #0xFFFFFF00
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ORR
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# CHECK: orn r0, r1, #255
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ORR r0, r1, #0xFEFFFEFF
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# CHECK: orn r0, r1, #16777472 @ encoding: [0x61,0xf0,0x01,0x20]
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ORR
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ORN r0, r1, #0xFFFFFF00
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# CHECK: orr r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ORN
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ORN r0, r1, #0xFEFFFEFF
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# CHECK: orr r0, r1, #16777472 @ encoding: [0x41,0xf0,0x01,0x20]
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: ORN
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[ARM] [Assembler] Support negative immediates for A32, T32 and T16
Summary:
To support negative immediates for certain arithmetic instructions, the
instruction is converted to the inverse instruction with a negated (or inverted)
immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD
instruction. However, "SUB r0, r1, #1" is equivalent.
These conversions are different from instruction aliases. An alias maps
several assembler instructions onto one encoding. A conversion, however, maps
an *invalid* instruction--e.g. with an immediate that cannot be represented in
the encoding--to a different (but equivalent) instruction.
Several instructions with negative immediates were being converted already, but
this was not systematically tested, nor did it cover all instructions.
This patch implements all possible substitutions for ARM, Thumb1 and
Thumb2 assembler and adds tests. It also adds a feature flag
(-mattr=+no-neg-immediates) to turn these substitutions off. This is
helpful for users who want their code to assemble to exactly what they
wrote.
Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin
Reviewed By: javed.absar
Subscribers: aadg, aemerson, llvm-commits
Differential Revision: https://reviews.llvm.org/D30571
llvm-svn: 298380
2017-03-21 22:59:17 +08:00
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CMP r0, #0xFFFFFF01
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# CHECK: cmn.w r0, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: CMP
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CMN r0, #0xFFFFFF01
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# CHECK: cmp.w r0, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: CMN
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MOV r0, #0xFFFFFF00
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# CHECK: mvn r0, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: MOV
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MVN r0, #0xFFFFFF00
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# CHECK: mov.w r0, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: MVN
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SBC r0, r1, #0xFFFFFF00
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# CHECK: adc r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: SBC
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SUBW r0, r1, #0xFFFFFF01
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# CHECK: addw r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: SUBW
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SUB.W r0, r1, #0xFFFFFF01
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# CHECK: add.w r0, r1, #255
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# CHECK-DISABLED: error: instruction requires: NegativeImmediates
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# CHECK-DISABLED: SUB.W
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