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llvm-project/llvm/test/CodeGen/ARM/cmn.ll

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[ARM] Add Thumb1 coverage for cmn testcases. There's a missed optimization for immediates: we can save two instructions by using adds instead of movs+mvns+cmp. llvm-svn: 335002
2018-06-19 08:09:44 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple thumbv7-eabi | FileCheck %s -check-prefix=T2
; RUN: llc < %s -mtriple thumbv6m-eabi | FileCheck %s -check-prefix=T1
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 16:07:26 +08:00
; <rdar://problem/7569620>
define i32 @compare_i_gt(i32 %a) {
[ARM] Add Thumb1 coverage for cmn testcases. There's a missed optimization for immediates: we can save two instructions by using adds instead of movs+mvns+cmp. llvm-svn: 335002
2018-06-19 08:09:44 +08:00
; T2-LABEL: compare_i_gt:
; T2: @ %bb.0: @ %entry
; T2-NEXT: movs r1, #24
; T2-NEXT: cmn.w r0, #78
; T2-NEXT: it gt
; T2-NEXT: movgt r1, #42
; T2-NEXT: mov r0, r1
; T2-NEXT: bx lr
;
; T1-LABEL: compare_i_gt:
; T1: @ %bb.0: @ %entry
[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1. The "dead" markings allow existing target-independent optimizations, like MachineSink, to trigger more frequently. The CPSR defs would have eventually been marked dead by LiveVariables, so this only affects optimizations before regalloc. The ARMBaseInstrInfo.cpp change is fixing a bug which is only visible with this change: the transform adds a use to an otherwise dead def of CPSR. This is covered by existing regression tests. thumb2-tbh.ll breaks for Thumb1 due to MachineLICM changing the generated code; I'll fix it in D53452. Differential Revision: https://reviews.llvm.org/D53453 llvm-svn: 345420
2018-10-27 03:32:24 +08:00
; T1-NEXT: movs r1, #77
; T1-NEXT: mvns r1, r1
; T1-NEXT: cmp r0, r1
[ARM] Add Thumb1 coverage for cmn testcases. There's a missed optimization for immediates: we can save two instructions by using adds instead of movs+mvns+cmp. llvm-svn: 335002
2018-06-19 08:09:44 +08:00
; T1-NEXT: bgt .LBB0_2
; T1-NEXT: @ %bb.1: @ %entry
[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1. The "dead" markings allow existing target-independent optimizations, like MachineSink, to trigger more frequently. The CPSR defs would have eventually been marked dead by LiveVariables, so this only affects optimizations before regalloc. The ARMBaseInstrInfo.cpp change is fixing a bug which is only visible with this change: the transform adds a use to an otherwise dead def of CPSR. This is covered by existing regression tests. thumb2-tbh.ll breaks for Thumb1 due to MachineLICM changing the generated code; I'll fix it in D53452. Differential Revision: https://reviews.llvm.org/D53453 llvm-svn: 345420
2018-10-27 03:32:24 +08:00
; T1-NEXT: movs r0, #24
; T1-NEXT: bx lr
; T1-NEXT: .LBB0_2:
; T1-NEXT: movs r0, #42
[ARM] Add Thumb1 coverage for cmn testcases. There's a missed optimization for immediates: we can save two instructions by using adds instead of movs+mvns+cmp. llvm-svn: 335002
2018-06-19 08:09:44 +08:00
; T1-NEXT: bx lr
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 16:07:26 +08:00
entry:
%cmp = icmp sgt i32 %a, -78
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
%ret = select i1 %cmp, i32 42, i32 24
ret i32 %ret
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 16:07:26 +08:00
}
define i32 @compare_r_eq(i32 %a, i32 %b) {
[ARM] Add Thumb1 coverage for cmn testcases. There's a missed optimization for immediates: we can save two instructions by using adds instead of movs+mvns+cmp. llvm-svn: 335002
2018-06-19 08:09:44 +08:00
; T2-LABEL: compare_r_eq:
; T2: @ %bb.0: @ %entry
; T2-NEXT: movs r2, #24
; T2-NEXT: cmn r0, r1
; T2-NEXT: it eq
; T2-NEXT: moveq r2, #42
; T2-NEXT: mov r0, r2
; T2-NEXT: bx lr
;
; T1-LABEL: compare_r_eq:
; T1: @ %bb.0: @ %entry
[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1. The "dead" markings allow existing target-independent optimizations, like MachineSink, to trigger more frequently. The CPSR defs would have eventually been marked dead by LiveVariables, so this only affects optimizations before regalloc. The ARMBaseInstrInfo.cpp change is fixing a bug which is only visible with this change: the transform adds a use to an otherwise dead def of CPSR. This is covered by existing regression tests. thumb2-tbh.ll breaks for Thumb1 due to MachineLICM changing the generated code; I'll fix it in D53452. Differential Revision: https://reviews.llvm.org/D53453 llvm-svn: 345420
2018-10-27 03:32:24 +08:00
; T1-NEXT: cmn r0, r1
[ARM] Add Thumb1 coverage for cmn testcases. There's a missed optimization for immediates: we can save two instructions by using adds instead of movs+mvns+cmp. llvm-svn: 335002
2018-06-19 08:09:44 +08:00
; T1-NEXT: beq .LBB1_2
; T1-NEXT: @ %bb.1: @ %entry
[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1. The "dead" markings allow existing target-independent optimizations, like MachineSink, to trigger more frequently. The CPSR defs would have eventually been marked dead by LiveVariables, so this only affects optimizations before regalloc. The ARMBaseInstrInfo.cpp change is fixing a bug which is only visible with this change: the transform adds a use to an otherwise dead def of CPSR. This is covered by existing regression tests. thumb2-tbh.ll breaks for Thumb1 due to MachineLICM changing the generated code; I'll fix it in D53452. Differential Revision: https://reviews.llvm.org/D53453 llvm-svn: 345420
2018-10-27 03:32:24 +08:00
; T1-NEXT: movs r0, #24
; T1-NEXT: bx lr
; T1-NEXT: .LBB1_2:
; T1-NEXT: movs r0, #42
[ARM] Add Thumb1 coverage for cmn testcases. There's a missed optimization for immediates: we can save two instructions by using adds instead of movs+mvns+cmp. llvm-svn: 335002
2018-06-19 08:09:44 +08:00
; T1-NEXT: bx lr
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 16:07:26 +08:00
entry:
%sub = sub nsw i32 0, %b
%cmp = icmp eq i32 %a, %sub
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
%ret = select i1 %cmp, i32 42, i32 24
ret i32 %ret
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 16:07:26 +08:00
}