2007-06-06 15:42:06 +08:00
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//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 15:42:06 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format MIPS assembly language.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-asm-printer"
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#include "Mips.h"
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2008-07-14 22:42:54 +08:00
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#include "MipsSubtarget.h"
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2007-06-06 15:42:06 +08:00
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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2007-07-12 07:24:41 +08:00
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#include "MipsMachineFunction.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Module.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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2007-07-12 07:24:41 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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2007-11-13 03:49:57 +08:00
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#include "llvm/Target/TargetOptions.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/Support/Mangler.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/StringExtras.h"
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2007-07-12 07:24:41 +08:00
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#include "llvm/Support/Debug.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/MathExtras.h"
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#include <cctype>
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using namespace llvm;
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STATISTIC(EmittedInsts, "Number of machine instrs printed");
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namespace {
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struct VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
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2008-07-14 22:42:54 +08:00
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const MipsSubtarget *Subtarget;
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2007-06-06 15:42:06 +08:00
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MipsAsmPrinter(std::ostream &O, MipsTargetMachine &TM,
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const TargetAsmInfo *T):
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2008-07-14 22:42:54 +08:00
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AsmPrinter(O, TM, T) {
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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}
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2007-06-06 15:42:06 +08:00
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virtual const char *getPassName() const {
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return "Mips Assembly Printer";
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}
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2008-07-19 21:16:11 +08:00
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virtual std::string getSectionForFunction(const Function &F) const;
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2008-08-03 03:42:36 +08:00
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode);
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2007-06-06 15:42:06 +08:00
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void printOperand(const MachineInstr *MI, int opNum);
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void printMemOperand(const MachineInstr *MI, int opNum,
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const char *Modifier = 0);
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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void printFCCOperand(const MachineInstr *MI, int opNum,
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const char *Modifier = 0);
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2008-07-19 21:16:11 +08:00
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void printModuleLevelGV(const GlobalVariable* GVar);
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2008-08-06 14:14:43 +08:00
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void printSavedRegsBitmask(MachineFunction &MF);
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2007-07-12 07:24:41 +08:00
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void printHex32(unsigned int Value);
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2007-08-28 13:06:17 +08:00
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2008-07-14 22:42:54 +08:00
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const char *emitCurrentABIString(void);
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2007-07-12 07:24:41 +08:00
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void emitFunctionStart(MachineFunction &MF);
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2007-10-09 11:01:19 +08:00
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void emitFunctionEnd(MachineFunction &MF);
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2007-07-12 07:24:41 +08:00
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void emitFrameDirective(MachineFunction &MF);
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2008-07-19 21:16:11 +08:00
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2007-06-06 15:42:06 +08:00
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bool printInstruction(const MachineInstr *MI); // autogenerated.
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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bool doFinalization(Module &M);
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};
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} // end of anonymous namespace
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#include "MipsGenAsmWriter.inc"
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/// createMipsCodePrinterPass - Returns a pass that prints the MIPS
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/// assembly code for a MachineFunction to the given output stream,
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/// using the given target machine description. This should work
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/// regardless of whether the function is in SSA form.
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FunctionPass *llvm::createMipsCodePrinterPass(std::ostream &o,
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MipsTargetMachine &tm)
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{
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return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo());
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}
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2007-08-28 13:06:17 +08:00
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//===----------------------------------------------------------------------===//
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//
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// Mips Asm Directives
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//
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// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
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// Describe the stack frame.
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//
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// -- Mask directives "(f)mask bitmask, offset"
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// Tells the assembler which registers are saved and where.
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// bitmask - contain a little endian bitset indicating which registers are
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// saved on function prologue (e.g. with a 0x80000000 mask, the
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// assembler knows the register 31 (RA) is saved at prologue.
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// offset - the position before stack pointer subtraction indicating where
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// the first saved register on prologue is located. (e.g. with a
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//
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// Consider the following function prologue:
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//
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2008-02-27 14:33:05 +08:00
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// .frame $fp,48,$ra
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// .mask 0xc0000000,-8
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// addiu $sp, $sp, -48
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// sw $ra, 40($sp)
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// sw $fp, 36($sp)
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2007-08-28 13:06:17 +08:00
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//
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// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
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// 30 (FP) are saved at prologue. As the save order on prologue is from
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// left to right, RA is saved first. A -8 offset means that after the
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// stack pointer subtration, the first register in the mask (RA) will be
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// saved at address 48-8=40.
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//
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//===----------------------------------------------------------------------===//
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2007-07-12 07:24:41 +08:00
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2008-07-14 22:42:54 +08:00
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//===----------------------------------------------------------------------===//
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// Mask directives
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//===----------------------------------------------------------------------===//
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2008-08-06 14:14:43 +08:00
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// Create a bitmask with all callee saved registers for CPU or Floating Point
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// registers. For CPU registers consider RA, GP and FP for saving if necessary.
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2007-07-12 07:24:41 +08:00
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void MipsAsmPrinter::
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2008-08-06 14:14:43 +08:00
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printSavedRegsBitmask(MachineFunction &MF)
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2007-08-28 13:06:17 +08:00
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{
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2008-02-11 02:45:23 +08:00
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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2008-08-06 14:14:43 +08:00
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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2007-08-28 13:06:17 +08:00
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2008-08-06 14:14:43 +08:00
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// CPU and FPU Saved Registers Bitmasks
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unsigned int CPUBitmask = 0;
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unsigned int FPUBitmask = 0;
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2007-08-28 13:06:17 +08:00
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2008-08-06 14:14:43 +08:00
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// Set the CPU and FPU Bitmasks
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2007-08-28 13:06:17 +08:00
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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2008-08-06 14:14:43 +08:00
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(CSI[i].getReg());
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if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
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CPUBitmask |= (1 << RegNum);
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else
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FPUBitmask |= (1 << RegNum);
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}
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2007-08-28 13:06:17 +08:00
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2008-08-06 14:14:43 +08:00
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// Return Address and Frame registers must also be set in CPUBitmask.
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2007-08-28 13:06:17 +08:00
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if (RI.hasFP(MF))
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2008-08-06 14:14:43 +08:00
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CPUBitmask |= (1 << MipsRegisterInfo::
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2007-10-09 11:01:19 +08:00
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getRegisterNumbering(RI.getFrameRegister(MF)));
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2007-08-28 13:06:17 +08:00
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if (MF.getFrameInfo()->hasCalls())
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2008-08-06 14:14:43 +08:00
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CPUBitmask |= (1 << MipsRegisterInfo::
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2007-10-09 11:01:19 +08:00
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getRegisterNumbering(RI.getRARegister()));
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2007-08-28 13:06:17 +08:00
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2008-08-06 14:14:43 +08:00
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// Print CPUBitmask
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O << "\t.mask \t"; printHex32(CPUBitmask); O << ','
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<< MipsFI->getCPUTopSavedRegOff() << '\n';
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// Print FPUBitmask
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O << "\t.fmask\t"; printHex32(FPUBitmask); O << ","
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<< MipsFI->getFPUTopSavedRegOff() << '\n';
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2007-08-28 13:06:17 +08:00
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}
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// Print a 32 bit hex number with all numbers.
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void MipsAsmPrinter::
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printHex32(unsigned int Value)
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{
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O << "0x" << std::hex;
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for (int i = 7; i >= 0; i--)
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O << std::hex << ( (Value & (0xF << (i*4))) >> (i*4) );
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O << std::dec;
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2007-07-12 07:24:41 +08:00
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}
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2008-07-14 22:42:54 +08:00
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//===----------------------------------------------------------------------===//
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// Frame and Set directives
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//===----------------------------------------------------------------------===//
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/// Frame Directive
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void MipsAsmPrinter::
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emitFrameDirective(MachineFunction &MF)
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{
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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unsigned stackReg = RI.getFrameRegister(MF);
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unsigned returnReg = RI.getRARegister();
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unsigned stackSize = MF.getFrameInfo()->getStackSize();
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2008-07-19 21:16:32 +08:00
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O << "\t.frame\t" << '$' << LowercaseString(RI.get(stackReg).AsmName)
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<< ',' << stackSize << ','
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<< '$' << LowercaseString(RI.get(returnReg).AsmName)
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<< '\n';
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2008-07-14 22:42:54 +08:00
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}
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/// Emit Set directives.
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const char * MipsAsmPrinter::
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emitCurrentABIString(void)
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{
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switch(Subtarget->getTargetABI()) {
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case MipsSubtarget::O32: return "abi32";
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case MipsSubtarget::O64: return "abiO64";
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case MipsSubtarget::N32: return "abiN32";
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case MipsSubtarget::N64: return "abi64";
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case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
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default: break;
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}
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assert(0 && "Unknown Mips ABI");
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return NULL;
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}
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2008-07-19 21:16:11 +08:00
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// Substitute old hook with new one temporary
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std::string MipsAsmPrinter::getSectionForFunction(const Function &F) const {
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return TAI->SectionForGlobal(&F);
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}
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2007-07-12 07:24:41 +08:00
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/// Emit the directives used by GAS on the start of functions
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void MipsAsmPrinter::
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emitFunctionStart(MachineFunction &MF)
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{
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// Print out the label for the function.
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const Function *F = MF.getFunction();
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2008-07-19 21:16:11 +08:00
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SwitchToTextSection(TAI->SectionForGlobal(F).c_str());
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2007-07-12 07:24:41 +08:00
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2007-11-13 03:49:57 +08:00
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// 2 bits aligned
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EmitAlignment(2, F);
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2007-07-12 07:24:41 +08:00
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2008-07-19 21:16:32 +08:00
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O << "\t.globl\t" << CurrentFnName << '\n';
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O << "\t.ent\t" << CurrentFnName << '\n';
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2008-07-14 22:42:54 +08:00
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if ((TAI->hasDotTypeDotSizeDirective()) && Subtarget->isLinux())
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O << "\t.type\t" << CurrentFnName << ", @function\n";
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2007-07-12 07:24:41 +08:00
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O << CurrentFnName << ":\n";
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emitFrameDirective(MF);
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2008-08-06 14:14:43 +08:00
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printSavedRegsBitmask(MF);
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2007-10-09 11:01:19 +08:00
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2008-07-19 21:16:32 +08:00
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O << '\n';
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2007-07-12 07:24:41 +08:00
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}
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/// Emit the directives used by GAS on the end of functions
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void MipsAsmPrinter::
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2007-10-09 11:01:19 +08:00
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emitFunctionEnd(MachineFunction &MF)
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{
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2008-07-14 22:42:54 +08:00
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// There are instruction for this macros, but they must
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// always be at the function end, and we can't emit and
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// break with BB logic.
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O << "\t.set\tmacro\n";
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O << "\t.set\treorder\n";
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2007-10-09 11:01:19 +08:00
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2008-07-19 21:16:32 +08:00
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O << "\t.end\t" << CurrentFnName << '\n';
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2008-07-14 22:42:54 +08:00
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if (TAI->hasDotTypeDotSizeDirective() && !Subtarget->isLinux())
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2008-07-19 21:16:32 +08:00
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O << "\t.size\t" << CurrentFnName << ", .-" << CurrentFnName << '\n';
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2007-07-12 07:24:41 +08:00
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}
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2007-06-06 15:42:06 +08:00
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/// runOnMachineFunction - This uses the printMachineInstruction()
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/// method to print assembly for each instruction.
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bool MipsAsmPrinter::
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runOnMachineFunction(MachineFunction &MF)
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{
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SetupMachineFunction(MF);
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// Print out constants referenced by the function
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EmitConstantPool(MF.getConstantPool());
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2007-11-13 03:49:57 +08:00
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// Print out jump tables referenced by the function
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EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
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2007-06-06 15:42:06 +08:00
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O << "\n\n";
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// What's my mangled name?
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CurrentFnName = Mang->getValueName(MF.getFunction());
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2007-07-12 07:24:41 +08:00
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// Emit the function start directives
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|
emitFunctionStart(MF);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Print out code for the function.
|
|
|
|
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
|
|
|
|
I != E; ++I) {
|
|
|
|
|
|
|
|
// Print a label for the basic block.
|
|
|
|
if (I != MF.begin()) {
|
2008-02-28 08:43:03 +08:00
|
|
|
printBasicBlockLabel(I, true, true);
|
2007-06-06 15:42:06 +08:00
|
|
|
O << '\n';
|
|
|
|
}
|
|
|
|
|
|
|
|
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
|
|
|
|
II != E; ++II) {
|
|
|
|
// Print the assembly for the instruction.
|
|
|
|
printInstruction(II);
|
|
|
|
++EmittedInsts;
|
|
|
|
}
|
2007-11-05 11:02:32 +08:00
|
|
|
|
|
|
|
// Each Basic Block is separated by a newline
|
|
|
|
O << '\n';
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
2007-07-12 07:24:41 +08:00
|
|
|
// Emit function end directives
|
2007-10-09 11:01:19 +08:00
|
|
|
emitFunctionEnd(MF);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// We didn't modify anything.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2008-08-03 03:42:36 +08:00
|
|
|
// Print out an operand for an inline asm expression.
|
|
|
|
bool MipsAsmPrinter::
|
|
|
|
PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
|
|
|
|
unsigned AsmVariant, const char *ExtraCode)
|
|
|
|
{
|
|
|
|
// Does this asm operand have a single letter operand modifier?
|
|
|
|
if (ExtraCode && ExtraCode[0])
|
|
|
|
return true; // Unknown modifier.
|
|
|
|
|
|
|
|
printOperand(MI, OpNo);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
void MipsAsmPrinter::
|
|
|
|
printOperand(const MachineInstr *MI, int opNum)
|
|
|
|
{
|
|
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
2008-02-11 02:45:23 +08:00
|
|
|
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
|
2007-11-05 11:02:32 +08:00
|
|
|
bool closeP = false;
|
|
|
|
bool isPIC = (TM.getRelocationModel() == Reloc::PIC_);
|
|
|
|
bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
|
|
|
|
|
|
|
|
// %hi and %lo used on mips gas to load global addresses on
|
|
|
|
// static code. %got is used to load global addresses when
|
|
|
|
// using PIC_. %call16 is used to load direct call targets
|
|
|
|
// on PIC_ and small code size. %call_lo and %call_hi load
|
|
|
|
// direct call targets on PIC_ and large code size.
|
2007-06-06 15:42:06 +08:00
|
|
|
if (MI->getOpcode() == Mips::LUi && !MO.isRegister()
|
|
|
|
&& !MO.isImmediate()) {
|
2007-11-05 11:02:32 +08:00
|
|
|
if ((isPIC) && (isCodeLarge))
|
|
|
|
O << "%call_hi(";
|
|
|
|
else
|
|
|
|
O << "%hi(";
|
2007-06-06 15:42:06 +08:00
|
|
|
closeP = true;
|
|
|
|
} else if ((MI->getOpcode() == Mips::ADDiu) && !MO.isRegister()
|
|
|
|
&& !MO.isImmediate()) {
|
2008-07-22 02:52:34 +08:00
|
|
|
const MachineOperand &firstMO = MI->getOperand(opNum-1);
|
|
|
|
if (firstMO.getReg() == Mips::GP)
|
|
|
|
O << "%gp_rel(";
|
|
|
|
else
|
|
|
|
O << "%lo(";
|
2007-06-06 15:42:06 +08:00
|
|
|
closeP = true;
|
2007-11-05 11:02:32 +08:00
|
|
|
} else if ((isPIC) && (MI->getOpcode() == Mips::LW)
|
|
|
|
&& (!MO.isRegister()) && (!MO.isImmediate())) {
|
|
|
|
const MachineOperand &firstMO = MI->getOperand(opNum-1);
|
|
|
|
const MachineOperand &lastMO = MI->getOperand(opNum+1);
|
|
|
|
if ((firstMO.isRegister()) && (lastMO.isRegister())) {
|
|
|
|
if ((firstMO.getReg() == Mips::T9) && (lastMO.getReg() == Mips::GP)
|
|
|
|
&& (!isCodeLarge))
|
|
|
|
O << "%call16(";
|
|
|
|
else if ((firstMO.getReg() != Mips::T9) && (lastMO.getReg() == Mips::GP))
|
|
|
|
O << "%got(";
|
|
|
|
else if ((firstMO.getReg() == Mips::T9) && (lastMO.getReg() != Mips::GP)
|
|
|
|
&& (isCodeLarge))
|
|
|
|
O << "%call_lo(";
|
|
|
|
closeP = true;
|
|
|
|
}
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (MO.getType())
|
|
|
|
{
|
|
|
|
case MachineOperand::MO_Register:
|
2008-02-11 02:45:23 +08:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
|
2008-07-19 21:16:32 +08:00
|
|
|
O << '$' << LowercaseString (RI.get(MO.getReg()).AsmName);
|
2007-06-06 15:42:06 +08:00
|
|
|
else
|
2008-07-19 21:16:32 +08:00
|
|
|
O << '$' << MO.getReg();
|
2007-06-06 15:42:06 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MachineOperand::MO_Immediate:
|
|
|
|
if ((MI->getOpcode() == Mips::SLTiu) || (MI->getOpcode() == Mips::ORi) ||
|
2007-07-12 07:24:41 +08:00
|
|
|
(MI->getOpcode() == Mips::LUi) || (MI->getOpcode() == Mips::ANDi))
|
2007-12-31 04:49:49 +08:00
|
|
|
O << (unsigned short int)MO.getImm();
|
2007-06-06 15:42:06 +08:00
|
|
|
else
|
2007-12-31 04:49:49 +08:00
|
|
|
O << (short int)MO.getImm();
|
2007-06-06 15:42:06 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
2007-12-31 07:10:15 +08:00
|
|
|
printBasicBlockLabel(MO.getMBB());
|
2007-06-06 15:42:06 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
case MachineOperand::MO_GlobalAddress:
|
|
|
|
O << Mang->getValueName(MO.getGlobal());
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MachineOperand::MO_ExternalSymbol:
|
|
|
|
O << MO.getSymbolName();
|
|
|
|
break;
|
|
|
|
|
2007-11-13 03:49:57 +08:00
|
|
|
case MachineOperand::MO_JumpTableIndex:
|
|
|
|
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
|
2007-12-31 07:10:15 +08:00
|
|
|
<< '_' << MO.getIndex();
|
2007-11-13 03:49:57 +08:00
|
|
|
break;
|
|
|
|
|
2007-11-05 11:02:32 +08:00
|
|
|
// FIXME: Verify correct
|
2007-06-06 15:42:06 +08:00
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
|
|
|
O << TAI->getPrivateGlobalPrefix() << "CPI"
|
2007-12-31 07:10:15 +08:00
|
|
|
<< getFunctionNumber() << "_" << MO.getIndex();
|
2007-06-06 15:42:06 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
O << "<unknown operand type>"; abort (); break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (closeP) O << ")";
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsAsmPrinter::
|
|
|
|
printMemOperand(const MachineInstr *MI, int opNum, const char *Modifier)
|
|
|
|
{
|
2007-09-25 04:15:11 +08:00
|
|
|
// when using stack locations for not load/store instructions
|
|
|
|
// print the same way as all normal 3 operand instructions.
|
|
|
|
if (Modifier && !strcmp(Modifier, "stackloc")) {
|
|
|
|
printOperand(MI, opNum+1);
|
|
|
|
O << ", ";
|
|
|
|
printOperand(MI, opNum);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2007-11-05 11:02:32 +08:00
|
|
|
// Load/Store memory operands -- imm($reg)
|
|
|
|
// If PIC target the target is loaded as the
|
|
|
|
// pattern lw $25,%call16($28)
|
2007-06-06 15:42:06 +08:00
|
|
|
printOperand(MI, opNum);
|
|
|
|
O << "(";
|
|
|
|
printOperand(MI, opNum+1);
|
|
|
|
O << ")";
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
void MipsAsmPrinter::
|
|
|
|
printFCCOperand(const MachineInstr *MI, int opNum, const char *Modifier)
|
|
|
|
{
|
|
|
|
const MachineOperand& MO = MI->getOperand(opNum);
|
|
|
|
O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
|
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
bool MipsAsmPrinter::
|
|
|
|
doInitialization(Module &M)
|
|
|
|
{
|
|
|
|
Mang = new Mangler(M);
|
2008-07-14 22:42:54 +08:00
|
|
|
|
|
|
|
// Tell the assembler which ABI we are using
|
2008-07-19 21:16:32 +08:00
|
|
|
O << "\t.section .mdebug." << emitCurrentABIString() << '\n';
|
2008-07-14 22:42:54 +08:00
|
|
|
|
|
|
|
// TODO: handle O64 ABI
|
|
|
|
if (Subtarget->isABI_EABI())
|
|
|
|
O << "\t.section .gcc_compiled_long" <<
|
2008-07-19 21:16:32 +08:00
|
|
|
(Subtarget->isGP32bit() ? "32" : "64") << '\n';
|
2008-07-14 22:42:54 +08:00
|
|
|
|
|
|
|
// return to previous section
|
2008-07-19 21:16:32 +08:00
|
|
|
O << "\t.previous" << '\n';
|
2008-07-14 22:42:54 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
return false; // success
|
|
|
|
}
|
|
|
|
|
2008-07-19 21:16:11 +08:00
|
|
|
void MipsAsmPrinter::
|
|
|
|
printModuleLevelGV(const GlobalVariable* GVar) {
|
2007-06-06 15:42:06 +08:00
|
|
|
const TargetData *TD = TM.getTargetData();
|
|
|
|
|
2008-07-19 21:16:11 +08:00
|
|
|
if (!GVar->hasInitializer())
|
|
|
|
return; // External global require no code
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2008-07-19 21:16:11 +08:00
|
|
|
// Check to see if this is a special global used by LLVM, if so, emit it.
|
|
|
|
if (EmitSpecialLLVMGlobal(GVar))
|
|
|
|
return;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2008-07-19 21:16:11 +08:00
|
|
|
O << "\n\n";
|
|
|
|
std::string SectionName = TAI->SectionForGlobal(GVar);
|
|
|
|
std::string name = Mang->getValueName(GVar);
|
|
|
|
Constant *C = GVar->getInitializer();
|
|
|
|
const Type *CTy = C->getType();
|
|
|
|
unsigned Size = TD->getABITypeSize(CTy);
|
2008-07-22 02:52:34 +08:00
|
|
|
const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
|
2008-07-19 21:16:11 +08:00
|
|
|
bool printSizeAndType = true;
|
|
|
|
|
|
|
|
// A data structure or array is aligned in memory to the largest
|
|
|
|
// alignment boundary required by any data type inside it (this matches
|
|
|
|
// the Preferred Type Alignment). For integral types, the alignment is
|
|
|
|
// the type size.
|
|
|
|
unsigned Align;
|
|
|
|
if (CTy->getTypeID() == Type::IntegerTyID ||
|
|
|
|
CTy->getTypeID() == Type::VoidTyID) {
|
|
|
|
assert(!(Size & (Size-1)) && "Alignment is not a power of two!");
|
|
|
|
Align = Log2_32(Size);
|
|
|
|
} else
|
|
|
|
Align = TD->getPreferredTypeAlignmentShift(CTy);
|
|
|
|
|
|
|
|
// FIXME: ELF supports visibility
|
|
|
|
|
|
|
|
SwitchToDataSection(SectionName.c_str());
|
|
|
|
|
|
|
|
if (C->isNullValue() && !GVar->hasSection()) {
|
|
|
|
if (!GVar->isThreadLocal() &&
|
|
|
|
(GVar->hasInternalLinkage() || GVar->isWeakForLinker())) {
|
|
|
|
if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
|
|
|
|
|
2008-07-29 03:11:24 +08:00
|
|
|
if (GVar->hasInternalLinkage())
|
|
|
|
O << "\t.local\t" << name << '\n';
|
|
|
|
|
|
|
|
O << TAI->getCOMMDirective() << name << ',' << Size;
|
|
|
|
if (TAI->getCOMMDirectiveTakesAlignment())
|
|
|
|
O << ',' << (1 << Align);
|
|
|
|
|
2008-07-19 21:16:11 +08:00
|
|
|
O << '\n';
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
switch (GVar->getLinkage()) {
|
|
|
|
case GlobalValue::LinkOnceLinkage:
|
|
|
|
case GlobalValue::CommonLinkage:
|
|
|
|
case GlobalValue::WeakLinkage:
|
|
|
|
// FIXME: Verify correct for weak.
|
|
|
|
// Nonnull linkonce -> weak
|
2008-07-19 21:16:32 +08:00
|
|
|
O << "\t.weak " << name << '\n';
|
2008-07-19 21:16:11 +08:00
|
|
|
break;
|
|
|
|
case GlobalValue::AppendingLinkage:
|
|
|
|
// FIXME: appending linkage variables should go into a section of their name
|
|
|
|
// or something. For now, just emit them as external.
|
|
|
|
case GlobalValue::ExternalLinkage:
|
|
|
|
// If external or appending, declare as a global symbol
|
2008-07-19 21:16:32 +08:00
|
|
|
O << TAI->getGlobalDirective() << name << '\n';
|
2008-07-19 21:16:11 +08:00
|
|
|
// Fall Through
|
|
|
|
case GlobalValue::InternalLinkage:
|
2008-07-22 02:52:34 +08:00
|
|
|
if (CVA && CVA->isCString())
|
2008-08-07 17:53:38 +08:00
|
|
|
printSizeAndType = false;
|
2008-07-19 21:16:11 +08:00
|
|
|
break;
|
|
|
|
case GlobalValue::GhostLinkage:
|
|
|
|
cerr << "Should not have any unmaterialized functions!\n";
|
|
|
|
abort();
|
|
|
|
case GlobalValue::DLLImportLinkage:
|
|
|
|
cerr << "DLLImport linkage is not supported by this target!\n";
|
|
|
|
abort();
|
|
|
|
case GlobalValue::DLLExportLinkage:
|
|
|
|
cerr << "DLLExport linkage is not supported by this target!\n";
|
|
|
|
abort();
|
|
|
|
default:
|
|
|
|
assert(0 && "Unknown linkage type!");
|
|
|
|
}
|
|
|
|
|
2008-08-07 17:53:38 +08:00
|
|
|
EmitAlignment(Align, GVar);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2008-07-19 21:16:11 +08:00
|
|
|
if (TAI->hasDotTypeDotSizeDirective() && printSizeAndType) {
|
|
|
|
O << "\t.type " << name << ",@object\n";
|
2008-07-19 21:16:32 +08:00
|
|
|
O << "\t.size " << name << ',' << Size << '\n';
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
2008-07-19 21:16:11 +08:00
|
|
|
O << name << ":\n";
|
|
|
|
EmitGlobalConstant(C);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool MipsAsmPrinter::
|
|
|
|
doFinalization(Module &M)
|
|
|
|
{
|
|
|
|
// Print out module-level global variables here.
|
|
|
|
for (Module::const_global_iterator I = M.global_begin(),
|
|
|
|
E = M.global_end(); I != E; ++I)
|
|
|
|
printModuleLevelGV(I);
|
|
|
|
|
2008-07-19 21:16:32 +08:00
|
|
|
O << '\n';
|
2008-06-04 09:45:25 +08:00
|
|
|
|
2007-07-26 03:33:14 +08:00
|
|
|
return AsmPrinter::doFinalization(M);
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|