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llvm-project/lldb/source/Plugins/Process/Utility/ARMDefines.h

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Move #define's out of ARMUtils.h and into a newly created file ARMDefines.h. llvm-svn: 124261
2011-01-26 09:18:52 +08:00
//===-- lldb_ARMDefines.h ---------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef lldb_ARMDefines_h_
#define lldb_ARMDefines_h_
Fix typos. llvm-svn: 212553
2014-07-09 02:05:41 +08:00
// Common definitions for the ARM/Thumb Instruction Set Architecture.
Move #define's out of ARMUtils.h and into a newly created file ARMDefines.h. llvm-svn: 124261
2011-01-26 09:18:52 +08:00
namespace lldb_private {
Add emulation methods for LSL (immediate), LSL (register), LSR (immediate), and LSR (register). Create two helper methods EmulateShiftImm() and EmulateShiftReg() and have ASR, LSL, and LSR delegate to the helper methods which take an extra ARM_ShifterType parameter. The opcodes tables have not been updated yet to reflect these new entries. llvm-svn: 125633
2011-02-16 09:27:54 +08:00
// ARM shifter types
typedef enum
{
SRType_LSL,
SRType_LSR,
SRType_ASR,
SRType_ROR,
Remove asserts that will crash LLDB. These should be changed to return true/false in an extra boolean parameter and not cause the the binary that us using the LLDB framework to crash. llvm-svn: 132501
2011-06-03 06:23:35 +08:00
SRType_RRX,
SRType_Invalid
Add emulation methods for LSL (immediate), LSL (register), LSR (immediate), and LSR (register). Create two helper methods EmulateShiftImm() and EmulateShiftReg() and have ASR, LSL, and LSR delegate to the helper methods which take an extra ARM_ShifterType parameter. The opcodes tables have not been updated yet to reflect these new entries. llvm-svn: 125633
2011-02-16 09:27:54 +08:00
} ARM_ShifterType;
Add some comments and a little utility to convert ARM conditions to strings. llvm-svn: 124898
2011-02-05 05:27:54 +08:00
// ARM conditions // Meaning (integer) Meaning (floating-point) Condition flags
#define COND_EQ 0x0 // Equal Equal Z == 1
#define COND_NE 0x1 // Not equal Not equal, or unordered Z == 0
#define COND_CS 0x2 // Carry set >, ==, or unordered C == 1
Move #define's out of ARMUtils.h and into a newly created file ARMDefines.h. llvm-svn: 124261
2011-01-26 09:18:52 +08:00
#define COND_HS 0x2
Add some comments and a little utility to convert ARM conditions to strings. llvm-svn: 124898
2011-02-05 05:27:54 +08:00
#define COND_CC 0x3 // Carry clear Less than C == 0
Move #define's out of ARMUtils.h and into a newly created file ARMDefines.h. llvm-svn: 124261
2011-01-26 09:18:52 +08:00
#define COND_LO 0x3
Add some comments and a little utility to convert ARM conditions to strings. llvm-svn: 124898
2011-02-05 05:27:54 +08:00
#define COND_MI 0x4 // Minus, negative Less than N == 1
#define COND_PL 0x5 // Plus, positive or zero >, ==, or unordered N == 0
#define COND_VS 0x6 // Overflow Unordered V == 1
#define COND_VC 0x7 // No overflow Not unordered V == 0
#define COND_HI 0x8 // Unsigned higher Greater than, or unordered C == 1 and Z == 0
#define COND_LS 0x9 // Unsigned lower or same Less than or equal C == 0 or Z == 1
#define COND_GE 0xA // Greater than or equal Greater than or equal N == V
#define COND_LT 0xB // Less than Less than, or unordered N != V
#define COND_GT 0xC // Greater than Greater than Z == 0 and N == V
#define COND_LE 0xD // Less than or equal <, ==, or unordered Z == 1 or N != V
#define COND_AL 0xE // Always (unconditional) Always (unconditional) Any
Move #define's out of ARMUtils.h and into a newly created file ARMDefines.h. llvm-svn: 124261
2011-01-26 09:18:52 +08:00
#define COND_UNCOND 0xF
Handle thumb IT instructions correctly all the time. The issue with Thumb IT (if/then) instructions is the IT instruction preceeds up to four instructions that are made conditional. If a breakpoint is placed on one of the conditional instructions, the instruction either needs to match the thumb opcode size (2 or 4 bytes) or a BKPT instruction needs to be used as these are always unconditional (even in a IT instruction). If BKPT instructions are used, then we might end up stopping on an instruction that won't get executed. So if we do stop at a BKPT instruction, we need to continue if the condition is not true. When using the BKPT isntructions are easy in that you don't need to detect the size of the breakpoint that needs to be used when setting a breakpoint even in a thumb IT instruction. The bad part is you will now always stop at the opcode location and let LLDB determine if it should auto-continue. If the BKPT instruction is used, the BKPT that is used for ARM code should be something that also triggers the BKPT instruction in Thumb in case you set a breakpoint in the middle of code and the code is actually Thumb code. A value of 0xE120BE70 will work since the lower 16 bits being 0xBE70 happens to be a Thumb BKPT instruction. The alternative is to use trap or illegal instructions that the kernel will translate into breakpoint hits. On Mac this was 0xE7FFDEFE for ARM and 0xDEFE for Thumb. The darwin kernel currently doesn't recognize any 32 bit Thumb instruction as a instruction that will get turned into a breakpoint exception (EXC_BREAKPOINT), so we had to use the BKPT instruction on Mac. The linux kernel recognizes a 16 and a 32 bit instruction as valid thumb breakpoint opcodes. The benefit of using 16 or 32 bit instructions is you don't stop on opcodes in a IT block when the condition doesn't match. To further complicate things, single stepping on ARM is often implemented by modifying the BCR/BVR registers and setting the processor to stop when the PC is not equal to the current value. This means single stepping is another way the ARM target can stop on instructions that won't get executed. This patch does the following: 1 - Fix the internal debugserver for Apple to use the BKPT instruction for ARM and Thumb 2 - Fix LLDB to catch when we stop in the middle of a Thumb IT instruction and continue if we stop at an instruction that won't execute 3 - Fixes this in a way that will work for any target on any platform as long as it is ARM/Thumb 4 - Adds a patch for ignoring conditions that don't match when in ARM mode (see below) This patch also provides the code that implements the same thing for ARM instructions, though it is disabled for now. The ARM patch will check the condition of the instruction in ARM mode and continue if the condition isn't true (and therefore the instruction would not be executed). Again, this is not enable, but the code for it has been added. <rdar://problem/19145455> llvm-svn: 223851
2014-12-10 07:31:02 +08:00
static inline const char *
ARMCondCodeToString(uint32_t CC)
Add some comments and a little utility to convert ARM conditions to strings. llvm-svn: 124898
2011-02-05 05:27:54 +08:00
{
switch (CC) {
default: assert(0 && "Unknown condition code");
case COND_EQ: return "eq";
case COND_NE: return "ne";
case COND_HS: return "hs";
case COND_LO: return "lo";
case COND_MI: return "mi";
case COND_PL: return "pl";
case COND_VS: return "vs";
case COND_VC: return "vc";
case COND_HI: return "hi";
case COND_LS: return "ls";
case COND_GE: return "ge";
case COND_LT: return "lt";
case COND_GT: return "gt";
case COND_LE: return "le";
case COND_AL: return "al";
}
}
Handle thumb IT instructions correctly all the time. The issue with Thumb IT (if/then) instructions is the IT instruction preceeds up to four instructions that are made conditional. If a breakpoint is placed on one of the conditional instructions, the instruction either needs to match the thumb opcode size (2 or 4 bytes) or a BKPT instruction needs to be used as these are always unconditional (even in a IT instruction). If BKPT instructions are used, then we might end up stopping on an instruction that won't get executed. So if we do stop at a BKPT instruction, we need to continue if the condition is not true. When using the BKPT isntructions are easy in that you don't need to detect the size of the breakpoint that needs to be used when setting a breakpoint even in a thumb IT instruction. The bad part is you will now always stop at the opcode location and let LLDB determine if it should auto-continue. If the BKPT instruction is used, the BKPT that is used for ARM code should be something that also triggers the BKPT instruction in Thumb in case you set a breakpoint in the middle of code and the code is actually Thumb code. A value of 0xE120BE70 will work since the lower 16 bits being 0xBE70 happens to be a Thumb BKPT instruction. The alternative is to use trap or illegal instructions that the kernel will translate into breakpoint hits. On Mac this was 0xE7FFDEFE for ARM and 0xDEFE for Thumb. The darwin kernel currently doesn't recognize any 32 bit Thumb instruction as a instruction that will get turned into a breakpoint exception (EXC_BREAKPOINT), so we had to use the BKPT instruction on Mac. The linux kernel recognizes a 16 and a 32 bit instruction as valid thumb breakpoint opcodes. The benefit of using 16 or 32 bit instructions is you don't stop on opcodes in a IT block when the condition doesn't match. To further complicate things, single stepping on ARM is often implemented by modifying the BCR/BVR registers and setting the processor to stop when the PC is not equal to the current value. This means single stepping is another way the ARM target can stop on instructions that won't get executed. This patch does the following: 1 - Fix the internal debugserver for Apple to use the BKPT instruction for ARM and Thumb 2 - Fix LLDB to catch when we stop in the middle of a Thumb IT instruction and continue if we stop at an instruction that won't execute 3 - Fixes this in a way that will work for any target on any platform as long as it is ARM/Thumb 4 - Adds a patch for ignoring conditions that don't match when in ARM mode (see below) This patch also provides the code that implements the same thing for ARM instructions, though it is disabled for now. The ARM patch will check the condition of the instruction in ARM mode and continue if the condition isn't true (and therefore the instruction would not be executed). Again, this is not enable, but the code for it has been added. <rdar://problem/19145455> llvm-svn: 223851
2014-12-10 07:31:02 +08:00
static inline bool
ARMConditionPassed(const uint32_t condition, const uint32_t cpsr)
{
const uint32_t cpsr_n = (cpsr >> 31) & 1u; // Negative condition code flag
const uint32_t cpsr_z = (cpsr >> 30) & 1u; // Zero condition code flag
const uint32_t cpsr_c = (cpsr >> 29) & 1u; // Carry condition code flag
const uint32_t cpsr_v = (cpsr >> 28) & 1u; // Overflow condition code flag
switch (condition) {
case COND_EQ: return (cpsr_z == 1);
case COND_NE: return (cpsr_z == 0);
case COND_CS: return (cpsr_c == 1);
case COND_CC: return (cpsr_c == 0);
case COND_MI: return (cpsr_n == 1);
case COND_PL: return (cpsr_n == 0);
case COND_VS: return (cpsr_v == 1);
case COND_VC: return (cpsr_v == 0);
case COND_HI: return ((cpsr_c == 1) && (cpsr_z == 0));
case COND_LS: return ((cpsr_c == 0) || (cpsr_z == 1));
case COND_GE: return (cpsr_n == cpsr_v);
case COND_LT: return (cpsr_n != cpsr_v);
case COND_GT: return ((cpsr_z == 0) && (cpsr_n == cpsr_v));
case COND_LE: return ((cpsr_z == 1) || (cpsr_n != cpsr_v));
case COND_AL:
case COND_UNCOND:
default:
return true;
}
return false;
}
Add a generic EmulateMovRdRm() method and modify/add entries to the g_thumb_opcodes table. Also add some more defines and convenience functions. llvm-svn: 125300
2011-02-11 03:29:03 +08:00
// Bit positions for CPSR
Renamed macro definition of CPSR_C to be CPSR_C_POS to avoid confusions and subtle bugs. llvm-svn: 126271
2011-02-23 08:15:56 +08:00
#define CPSR_T_POS 5
#define CPSR_F_POS 6
#define CPSR_I_POS 7
#define CPSR_A_POS 8
#define CPSR_E_POS 9
#define CPSR_J_POS 24
#define CPSR_Q_POS 27
#define CPSR_V_POS 28
#define CPSR_C_POS 29
#define CPSR_Z_POS 30
#define CPSR_N_POS 31
Add a generic EmulateMovRdRm() method and modify/add entries to the g_thumb_opcodes table. Also add some more defines and convenience functions. llvm-svn: 125300
2011-02-11 03:29:03 +08:00
Changed the emulate instruction function to take emulate options which are defined as enumerations. Current bits include: eEmulateInstructionOptionAutoAdvancePC eEmulateInstructionOptionIgnoreConditions Modified the EmulateInstruction class to have a few more pure virtuals that can help clients understand how many instructions the emulator can handle: virtual bool SupportsEmulatingIntructionsOfType (InstructionType inst_type) = 0; Where instruction types are defined as: //------------------------------------------------------------------ /// Instruction types //------------------------------------------------------------------ typedef enum InstructionType { eInstructionTypeAny, // Support for any instructions at all (at least one) eInstructionTypePrologueEpilogue, // All prologue and epilogue instructons that push and pop register values and modify sp/fp eInstructionTypePCModifying, // Any instruction that modifies the program counter/instruction pointer eInstructionTypeAll // All instructions of any kind } InstructionType; This allows use to tell what an emulator can do and also allows us to request these abilities when we are finding the plug-in interface. Added the ability for an EmulateInstruction class to get the register names for any registers that are part of the emulation. This helps with being able to dump and log effectively. The UnwindAssembly class now stores the architecture it was created with in case it is needed later in the unwinding process. Added a function that can tell us DWARF register names for ARM that goes along with the source/Utility/ARM_DWARF_Registers.h file: source/Utility/ARM_DWARF_Registers.c Took some of plug-ins out of the lldb_private namespace. llvm-svn: 130189
2011-04-26 12:39:08 +08:00
// CPSR mode definitions
#define CPSR_MODE_USR 0x10u
#define CPSR_MODE_FIQ 0x11u
#define CPSR_MODE_IRQ 0x12u
#define CPSR_MODE_SVC 0x13u
#define CPSR_MODE_ABT 0x17u
#define CPSR_MODE_UND 0x1bu
#define CPSR_MODE_SYS 0x1fu
Move #define's out of ARMUtils.h and into a newly created file ARMDefines.h. llvm-svn: 124261
2011-01-26 09:18:52 +08:00
// Masks for CPSR
Added a way to resolve an load address from a target: bool Address::SetLoadAddress (lldb::addr_t load_addr, Target *target); Added an == and != operator to RegisterValue. Modified the ThreadPlanTracer to use RegisterValue objects to store the register values when single stepping. Also modified the output to be a bit less wide. Fixed the ABIMacOSX_arm to not overwrite stuff on the stack. Also made the trivial function call be able to set the ARM/Thumbness of the target correctly, and also sets the return value ARM/Thumbness. Fixed the encoding on the arm s0-s31 and d16 - d31 registers when the default register set from a standard GDB server register sets. llvm-svn: 131517
2011-05-18 09:58:14 +08:00
#define MASK_CPSR_MODE_MASK (0x0000001fu)
#define MASK_CPSR_IT_MASK (0x0600fc00u)
Renamed macro definition of CPSR_C to be CPSR_C_POS to avoid confusions and subtle bugs. llvm-svn: 126271
2011-02-23 08:15:56 +08:00
#define MASK_CPSR_T (1u << CPSR_T_POS)
#define MASK_CPSR_F (1u << CPSR_F_POS)
#define MASK_CPSR_I (1u << CPSR_I_POS)
#define MASK_CPSR_A (1u << CPSR_A_POS)
#define MASK_CPSR_E (1u << CPSR_E_POS)
Move #define's out of ARMUtils.h and into a newly created file ARMDefines.h. llvm-svn: 124261
2011-01-26 09:18:52 +08:00
#define MASK_CPSR_GE_MASK (0x000f0000u)
Renamed macro definition of CPSR_C to be CPSR_C_POS to avoid confusions and subtle bugs. llvm-svn: 126271
2011-02-23 08:15:56 +08:00
#define MASK_CPSR_J (1u << CPSR_J_POS)
#define MASK_CPSR_Q (1u << CPSR_Q_POS)
#define MASK_CPSR_V (1u << CPSR_V_POS)
#define MASK_CPSR_C (1u << CPSR_C_POS)
#define MASK_CPSR_Z (1u << CPSR_Z_POS)
#define MASK_CPSR_N (1u << CPSR_N_POS)
Move #define's out of ARMUtils.h and into a newly created file ARMDefines.h. llvm-svn: 124261
2011-01-26 09:18:52 +08:00
} // namespace lldb_private
#endif // lldb_ARMDefines_h_