2007-10-13 05:30:57 +08:00
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//====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
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2006-02-22 03:13:53 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2006-02-22 03:13:53 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 SSE instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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2006-10-08 05:55:32 +08:00
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2006-03-18 09:23:20 +08:00
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//===----------------------------------------------------------------------===//
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// SSE specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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2007-01-05 15:55:56 +08:00
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def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
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SDTCisFP<0>, SDTCisInt<2> ]>;
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2006-11-11 05:43:37 +08:00
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def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
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def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
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2006-04-06 07:38:46 +08:00
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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2006-03-22 10:53:00 +08:00
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[SDNPCommutative, SDNPAssociative]>;
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2007-01-05 15:55:56 +08:00
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def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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2006-04-06 07:38:46 +08:00
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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2006-03-22 10:53:00 +08:00
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[SDNPCommutative, SDNPAssociative]>;
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2007-07-10 08:05:58 +08:00
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def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
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def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
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2007-01-05 15:55:56 +08:00
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def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
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2007-10-02 02:12:48 +08:00
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def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
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2007-09-29 08:00:36 +08:00
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def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
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2008-02-11 12:19:36 +08:00
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def X86pextrb : SDNode<"X86ISD::PEXTRB",
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
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def X86pextrw : SDNode<"X86ISD::PEXTRW",
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
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def X86pinsrb : SDNode<"X86ISD::PINSRB",
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SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
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def X86pinsrw : SDNode<"X86ISD::PINSRW",
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SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
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def X86insrtps : SDNode<"X86ISD::INSERTPS",
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SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
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SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
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2008-05-10 05:53:03 +08:00
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def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
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SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
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def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
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[SDNPHasChain, SDNPMayLoad]>;
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2006-03-25 17:37:23 +08:00
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2006-10-08 05:55:32 +08:00
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//===----------------------------------------------------------------------===//
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// SSE Complex Patterns
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//===----------------------------------------------------------------------===//
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// These are 'extloads' from a scalar to the low element of a vector, zeroing
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// the top elements. These are used for the SSE 'ss' and 'sd' instruction
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// forms.
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2006-10-12 05:06:01 +08:00
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def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
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2008-01-10 15:59:24 +08:00
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[SDNPHasChain, SDNPMayLoad]>;
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2006-10-12 05:06:01 +08:00
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def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
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2008-01-10 15:59:24 +08:00
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[SDNPHasChain, SDNPMayLoad]>;
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2006-10-08 05:55:32 +08:00
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def ssmem : Operand<v4f32> {
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let PrintMethod = "printf32mem";
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let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
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}
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def sdmem : Operand<v2f64> {
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let PrintMethod = "printf64mem";
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let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
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}
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2006-02-22 04:00:20 +08:00
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//===----------------------------------------------------------------------===//
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2006-03-18 03:55:52 +08:00
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// SSE pattern fragments
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//===----------------------------------------------------------------------===//
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2006-03-18 09:23:20 +08:00
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def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
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def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
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2007-06-25 23:19:03 +08:00
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def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
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2006-03-23 15:44:07 +08:00
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def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
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2006-03-18 03:55:52 +08:00
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2007-07-28 01:16:43 +08:00
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// Like 'store', but always requires vector alignment.
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2007-07-19 04:23:34 +08:00
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def alignedstore : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
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return !ST->isTruncatingStore() &&
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ST->getAddressingMode() == ISD::UNINDEXED &&
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2007-07-28 01:16:43 +08:00
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ST->getAlignment() >= 16;
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2007-07-19 04:23:34 +08:00
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return false;
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}]>;
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2007-07-28 01:16:43 +08:00
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// Like 'load', but always requires vector alignment.
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2007-07-19 04:23:34 +08:00
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def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
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return LD->getExtensionType() == ISD::NON_EXTLOAD &&
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LD->getAddressingMode() == ISD::UNINDEXED &&
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2007-07-28 01:16:43 +08:00
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LD->getAlignment() >= 16;
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2007-07-19 04:23:34 +08:00
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return false;
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}]>;
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2007-07-28 01:16:43 +08:00
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def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
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def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
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2007-07-19 04:23:34 +08:00
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def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
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def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
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def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
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def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
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// Like 'load', but uses special alignment checks suitable for use in
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// memory operands in most SSE instructions, which are required to
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// be naturally aligned on some targets but not on others.
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// FIXME: Actually implement support for targets that don't require the
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// alignment. This probably wants a subtarget predicate.
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def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
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return LD->getExtensionType() == ISD::NON_EXTLOAD &&
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LD->getAddressingMode() == ISD::UNINDEXED &&
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2007-07-28 01:16:43 +08:00
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LD->getAlignment() >= 16;
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2007-07-19 04:23:34 +08:00
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return false;
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}]>;
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2007-07-28 01:16:43 +08:00
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def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
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def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
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2007-07-19 04:23:34 +08:00
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def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
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def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
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def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
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def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
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2008-02-10 07:46:37 +08:00
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def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
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2007-07-19 04:23:34 +08:00
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2007-08-11 17:52:53 +08:00
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// SSSE3 uses MMX registers for some instructions. They aren't aligned on a
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// 16-byte boundary.
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2008-02-10 07:46:37 +08:00
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// FIXME: 8 byte alignment for mmx reads is not required
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2007-08-11 17:52:53 +08:00
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def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
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return LD->getExtensionType() == ISD::NON_EXTLOAD &&
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LD->getAddressingMode() == ISD::UNINDEXED &&
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LD->getAlignment() >= 8;
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return false;
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}]>;
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def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
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def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
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def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
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def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
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2006-03-30 15:33:32 +08:00
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def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
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def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
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2006-03-30 07:07:14 +08:00
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def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
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def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
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2006-03-30 02:47:40 +08:00
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def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
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def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
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2006-03-24 15:29:27 +08:00
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def fp32imm0 : PatLeaf<(f32 fpimm), [{
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return N->isExactlyValue(+0.0);
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}]>;
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2006-04-05 05:49:39 +08:00
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def PSxLDQ_imm : SDNodeXForm<imm, [{
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// Transformation function: imm >> 3
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return getI32Imm(N->getValue() >> 3);
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}]>;
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2008-05-13 04:34:32 +08:00
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def SSE_CC_imm : SDNodeXForm<cond, [{
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unsigned Val;
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switch (N->get()) {
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default: Val = 0; assert(0 && "Unexpected CondCode"); break;
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case ISD::SETOEQ: Val = 0; break;
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case ISD::SETOLT: Val = 1; break;
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case ISD::SETOLE: Val = 2; break;
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case ISD::SETUO: Val = 3; break;
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case ISD::SETONE: Val = 4; break;
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case ISD::SETOGE: Val = 5; break;
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case ISD::SETOGT: Val = 6; break;
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case ISD::SETO: Val = 7; break;
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}
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return getI8Imm(Val);
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}]>;
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2006-03-22 16:01:21 +08:00
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// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
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// SHUFP* etc. imm.
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def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
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return getI8Imm(X86::getShuffleSHUFImmediate(N));
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2006-03-22 10:53:00 +08:00
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}]>;
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2006-03-30 07:07:14 +08:00
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// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
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// PSHUFHW imm.
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def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
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return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
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}]>;
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// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
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// PSHUFLW imm.
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def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
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return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
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}]>;
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2006-03-30 03:02:40 +08:00
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def SSE_splat_mask : PatLeaf<(build_vector), [{
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2006-03-23 02:59:22 +08:00
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return X86::isSplatMask(N);
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2006-03-30 03:02:40 +08:00
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}], SHUFFLE_get_shuf_imm>;
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2006-03-23 02:59:22 +08:00
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2006-10-28 05:08:32 +08:00
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def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
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return X86::isSplatLoMask(N);
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2006-04-15 05:59:03 +08:00
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}]>;
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2006-03-24 10:58:06 +08:00
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def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVHLPSMask(N);
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2006-03-28 10:43:26 +08:00
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}]>;
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2006-03-24 10:58:06 +08:00
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Fixed a bug which causes x86 be to incorrectly match
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
llvm-svn: 31519
2006-11-08 06:14:24 +08:00
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def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVHLPS_v_undef_Mask(N);
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}]>;
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2006-04-07 07:23:56 +08:00
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def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVHPMask(N);
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}]>;
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def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVLPMask(N);
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}]>;
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Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
llvm-svn: 27923
2006-04-21 09:05:10 +08:00
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def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVLMask(N);
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2006-04-11 08:19:04 +08:00
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}]>;
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2006-04-15 05:59:03 +08:00
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def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVSHDUPMask(N);
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}]>;
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def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVSLDUPMask(N);
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}]>;
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2006-03-28 08:39:58 +08:00
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def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKLMask(N);
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}]>;
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2006-03-28 10:43:26 +08:00
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def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKHMask(N);
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}]>;
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Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
llvm-svn: 27437
2006-04-05 15:20:06 +08:00
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def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
|
|
|
|
return X86::isUNPCKL_v_undef_Mask(N);
|
|
|
|
}]>;
|
|
|
|
|
2007-05-18 02:44:37 +08:00
|
|
|
def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
|
|
|
|
return X86::isUNPCKH_v_undef_Mask(N);
|
|
|
|
}]>;
|
|
|
|
|
2006-03-23 02:59:22 +08:00
|
|
|
def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
|
2006-03-29 09:30:51 +08:00
|
|
|
return X86::isPSHUFDMask(N);
|
2006-03-24 09:18:28 +08:00
|
|
|
}], SHUFFLE_get_shuf_imm>;
|
2006-03-23 02:59:22 +08:00
|
|
|
|
2006-03-30 07:07:14 +08:00
|
|
|
def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
|
|
|
|
return X86::isPSHUFHWMask(N);
|
|
|
|
}], SHUFFLE_get_pshufhw_imm>;
|
|
|
|
|
|
|
|
def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
|
|
|
|
return X86::isPSHUFLWMask(N);
|
|
|
|
}], SHUFFLE_get_pshuflw_imm>;
|
|
|
|
|
2006-04-11 06:35:16 +08:00
|
|
|
def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
|
|
|
|
return X86::isPSHUFDMask(N);
|
2006-03-31 03:54:57 +08:00
|
|
|
}], SHUFFLE_get_shuf_imm>;
|
|
|
|
|
2006-03-24 09:18:28 +08:00
|
|
|
def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
|
|
|
|
return X86::isSHUFPMask(N);
|
|
|
|
}], SHUFFLE_get_shuf_imm>;
|
2006-03-22 10:53:00 +08:00
|
|
|
|
2006-04-11 06:35:16 +08:00
|
|
|
def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
|
|
|
|
return X86::isSHUFPMask(N);
|
2006-03-29 11:04:49 +08:00
|
|
|
}], SHUFFLE_get_shuf_imm>;
|
|
|
|
|
2008-05-13 04:34:32 +08:00
|
|
|
|
2006-03-18 03:55:52 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2006-02-22 04:00:20 +08:00
|
|
|
// SSE scalar FP Instructions
|
|
|
|
//===----------------------------------------------------------------------===//
|
2006-02-22 03:13:53 +08:00
|
|
|
|
2006-02-22 04:00:20 +08:00
|
|
|
// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
|
|
|
|
// scheduler into a branch sequence.
|
2007-09-25 09:57:46 +08:00
|
|
|
// These are expanded by the scheduler.
|
|
|
|
let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
|
2006-02-22 04:00:20 +08:00
|
|
|
def CMOV_FR32 : I<0, Pseudo,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
|
2006-02-22 04:00:20 +08:00
|
|
|
"#CMOV_FR32 PSEUDO!",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
|
2007-09-25 09:57:46 +08:00
|
|
|
EFLAGS))]>;
|
2007-09-29 08:00:36 +08:00
|
|
|
def CMOV_FR64 : I<0, Pseudo,
|
2007-09-25 09:57:46 +08:00
|
|
|
(outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
|
|
|
|
"#CMOV_FR64 PSEUDO!",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
|
2007-09-25 09:57:46 +08:00
|
|
|
EFLAGS))]>;
|
2007-09-29 08:00:36 +08:00
|
|
|
def CMOV_V4F32 : I<0, Pseudo,
|
2007-09-25 09:57:46 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
|
|
|
|
"#CMOV_V4F32 PSEUDO!",
|
|
|
|
[(set VR128:$dst,
|
2007-09-29 08:00:36 +08:00
|
|
|
(v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
|
2007-09-25 09:57:46 +08:00
|
|
|
EFLAGS)))]>;
|
2007-09-29 08:00:36 +08:00
|
|
|
def CMOV_V2F64 : I<0, Pseudo,
|
2007-09-25 09:57:46 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
|
|
|
|
"#CMOV_V2F64 PSEUDO!",
|
|
|
|
[(set VR128:$dst,
|
2007-09-29 08:00:36 +08:00
|
|
|
(v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
|
2007-09-25 09:57:46 +08:00
|
|
|
EFLAGS)))]>;
|
2007-09-29 08:00:36 +08:00
|
|
|
def CMOV_V2I64 : I<0, Pseudo,
|
2007-09-25 09:57:46 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
|
|
|
|
"#CMOV_V2I64 PSEUDO!",
|
|
|
|
[(set VR128:$dst,
|
2007-09-29 08:00:36 +08:00
|
|
|
(v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
|
2007-09-25 09:57:46 +08:00
|
|
|
EFLAGS)))]>;
|
2006-02-22 03:13:53 +08:00
|
|
|
}
|
2006-02-22 03:26:52 +08:00
|
|
|
|
2007-05-03 07:11:52 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SSE1 Instructions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2006-02-22 04:00:20 +08:00
|
|
|
// Move Instructions
|
2008-01-11 14:59:07 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movss\t{$src, $dst|$dst, $src}", []>;
|
2008-01-07 07:38:27 +08:00
|
|
|
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (loadf32 addr:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(store FR32:$src, addr:$dst)]>;
|
2006-02-22 03:26:52 +08:00
|
|
|
|
2007-05-03 07:11:52 +08:00
|
|
|
// Conversion instructions
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttss2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst, (fp_to_sint FR32:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttss2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsi2ss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (sint_to_fp GR32:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsi2ss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
|
|
|
|
|
|
|
|
// Match intrinsics which expect XMM operand(s).
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtss2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtss2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst, (int_x86_sse_cvtss2si
|
|
|
|
(load addr:$src)))]>;
|
|
|
|
|
2007-10-31 06:15:38 +08:00
|
|
|
// Match intrinisics which expect MM and XMM operand(s).
|
|
|
|
def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
|
|
|
|
"cvtps2pi\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
|
|
|
|
def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
|
|
|
|
"cvtps2pi\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR64:$dst, (int_x86_sse_cvtps2pi
|
|
|
|
(load addr:$src)))]>;
|
|
|
|
def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
|
|
|
|
"cvttps2pi\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
|
|
|
|
def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
|
|
|
|
"cvttps2pi\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR64:$dst, (int_x86_sse_cvttps2pi
|
|
|
|
(load addr:$src)))]>;
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-10-31 06:15:38 +08:00
|
|
|
def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
|
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
|
|
|
|
"cvtpi2ps\t{$src2, $dst|$dst, $src2}",
|
|
|
|
[(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
|
|
|
|
VR64:$src2))]>;
|
|
|
|
def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
|
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
|
|
|
|
"cvtpi2ps\t{$src2, $dst|$dst, $src2}",
|
|
|
|
[(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
|
|
|
|
(load addr:$src2)))]>;
|
|
|
|
}
|
|
|
|
|
2007-05-03 07:11:52 +08:00
|
|
|
// Aliases for intrinsics
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttss2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst,
|
|
|
|
(int_x86_sse_cvttss2si VR128:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttss2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst,
|
|
|
|
(int_x86_sse_cvttss2si(load addr:$src)))]>;
|
|
|
|
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsi2ss\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
|
|
|
|
GR32:$src2))]>;
|
|
|
|
def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsi2ss\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
|
|
|
|
(loadi32 addr:$src2)))]>;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Comparison instructions
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2008-01-11 14:59:07 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
2007-12-17 04:12:41 +08:00
|
|
|
def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
|
2008-01-11 14:59:07 +08:00
|
|
|
let neverHasSideEffects = 1, mayLoad = 1 in
|
2007-12-17 04:12:41 +08:00
|
|
|
def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
|
2007-05-03 07:11:52 +08:00
|
|
|
}
|
|
|
|
|
2007-09-15 05:48:26 +08:00
|
|
|
let Defs = [EFLAGS] in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86cmp FR32:$src1, (loadf32 addr:$src2)),
|
2007-09-25 09:57:46 +08:00
|
|
|
(implicit EFLAGS)]>;
|
2007-09-15 05:48:26 +08:00
|
|
|
} // Defs = [EFLAGS]
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
// Aliases to match intrinsics which expect XMM operand(s).
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-12-17 04:12:41 +08:00
|
|
|
def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cmp${cc}ss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
|
|
|
|
VR128:$src, imm:$cc))]>;
|
2007-12-17 04:12:41 +08:00
|
|
|
def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cmp${cc}ss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
|
|
|
|
(load addr:$src), imm:$cc))]>;
|
|
|
|
}
|
|
|
|
|
2007-09-15 05:48:26 +08:00
|
|
|
let Defs = [EFLAGS] in {
|
2007-09-29 08:00:36 +08:00
|
|
|
def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
|
2007-09-25 09:57:46 +08:00
|
|
|
(ins VR128:$src1, VR128:$src2),
|
|
|
|
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
|
2007-09-25 09:57:46 +08:00
|
|
|
(implicit EFLAGS)]>;
|
2007-09-29 08:00:36 +08:00
|
|
|
def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
|
2007-09-25 09:57:46 +08:00
|
|
|
(ins VR128:$src1, f128mem:$src2),
|
|
|
|
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
|
2007-09-25 09:57:46 +08:00
|
|
|
(implicit EFLAGS)]>;
|
|
|
|
|
2007-09-29 08:00:36 +08:00
|
|
|
def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
|
2007-09-25 09:57:46 +08:00
|
|
|
(ins VR128:$src1, VR128:$src2),
|
|
|
|
"comiss\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86comi (v4f32 VR128:$src1), VR128:$src2),
|
2007-09-25 09:57:46 +08:00
|
|
|
(implicit EFLAGS)]>;
|
2007-09-29 08:00:36 +08:00
|
|
|
def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
|
2007-09-25 09:57:46 +08:00
|
|
|
(ins VR128:$src1, f128mem:$src2),
|
|
|
|
"comiss\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
|
2007-09-25 09:57:46 +08:00
|
|
|
(implicit EFLAGS)]>;
|
2007-09-15 05:48:26 +08:00
|
|
|
} // Defs = [EFLAGS]
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
// Aliases of packed SSE1 instructions for scalar use. These all have names that
|
|
|
|
// start with 'Fs'.
|
|
|
|
|
|
|
|
// Alias instructions that map fld0 to pxor for sse.
|
2008-01-10 13:45:39 +08:00
|
|
|
let isReMaterializable = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
|
2007-08-01 04:11:57 +08:00
|
|
|
"pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
|
2007-05-03 07:11:52 +08:00
|
|
|
Requires<[HasSSE1]>, TB, OpSize;
|
|
|
|
|
|
|
|
// Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
|
|
|
|
// disregarded.
|
2008-01-10 15:59:24 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movaps\t{$src, $dst|$dst, $src}", []>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
// Alias instruction to load FR32 from f128mem using movaps. Upper bits are
|
|
|
|
// disregarded.
|
2008-01-07 07:38:27 +08:00
|
|
|
let isSimpleLoad = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movaps\t{$src, $dst|$dst, $src}",
|
2007-07-28 01:16:43 +08:00
|
|
|
[(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
// Alias bitwise logical operations using SSE logical ops on packed FP values.
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
let isCommutable = 1 in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"orps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"xorps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (X86fand FR32:$src1,
|
2007-07-28 01:16:43 +08:00
|
|
|
(memopfsf32 addr:$src2)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"orps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (X86for FR32:$src1,
|
2007-07-28 01:16:43 +08:00
|
|
|
(memopfsf32 addr:$src2)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"xorps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (X86fxor FR32:$src1,
|
2007-07-28 01:16:43 +08:00
|
|
|
(memopfsf32 addr:$src2)))]>;
|
2008-01-10 15:59:24 +08:00
|
|
|
let neverHasSideEffects = 1 in {
|
2007-06-25 23:44:19 +08:00
|
|
|
def FsANDNPSrr : PSI<0x55, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andnps\t{$src2, $dst|$dst, $src2}", []>;
|
2008-01-10 15:59:24 +08:00
|
|
|
|
|
|
|
let mayLoad = 1 in
|
2007-06-25 23:44:19 +08:00
|
|
|
def FsANDNPSrm : PSI<0x55, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andnps\t{$src2, $dst|$dst, $src2}", []>;
|
2007-05-03 07:11:52 +08:00
|
|
|
}
|
2008-01-10 15:59:24 +08:00
|
|
|
}
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
/// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
|
|
|
|
///
|
|
|
|
/// In addition, we also have a special variant of the scalar form here to
|
|
|
|
/// represent the associated intrinsic operation. This form is unlike the
|
|
|
|
/// plain scalar form, in that it takes an entire vector (instead of a scalar)
|
|
|
|
/// and leaves the top elements undefined.
|
2006-10-08 04:55:57 +08:00
|
|
|
///
|
2007-07-10 08:05:58 +08:00
|
|
|
/// These three forms can each be reg+reg or reg+mem, so there are a total of
|
|
|
|
/// six "instructions".
|
2006-10-08 04:55:57 +08:00
|
|
|
///
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-07-10 08:05:58 +08:00
|
|
|
multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
|
|
|
|
SDNode OpNode, Intrinsic F32Int,
|
|
|
|
bit Commutable = 0> {
|
2006-10-08 04:55:57 +08:00
|
|
|
// Scalar operation, reg+reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
2007-06-25 23:44:19 +08:00
|
|
|
[(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
|
2006-10-08 04:35:44 +08:00
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2006-10-08 04:55:57 +08:00
|
|
|
// Scalar operation, reg+mem.
|
2008-05-23 08:37:07 +08:00
|
|
|
def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
|
|
|
|
(ins FR32:$src1, f32mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
2006-10-08 05:55:32 +08:00
|
|
|
[(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
|
2006-10-08 04:55:57 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Vector operation, reg+reg.
|
2008-05-23 08:37:07 +08:00
|
|
|
def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Vector operation, reg+mem.
|
2008-05-23 08:37:07 +08:00
|
|
|
def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
|
2008-05-23 08:37:07 +08:00
|
|
|
[(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
|
2007-07-10 08:05:58 +08:00
|
|
|
|
|
|
|
// Intrinsic operation, reg+reg.
|
2008-05-23 08:37:07 +08:00
|
|
|
def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
2006-10-08 04:55:57 +08:00
|
|
|
[(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Intrinsic operation, reg+mem.
|
2008-05-23 08:37:07 +08:00
|
|
|
def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, ssmem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
2006-10-08 04:55:57 +08:00
|
|
|
[(set VR128:$dst, (F32Int VR128:$src1,
|
2006-10-08 05:55:32 +08:00
|
|
|
sse_load_f32:$src2))]>;
|
2006-02-22 03:26:52 +08:00
|
|
|
}
|
2006-02-22 04:00:20 +08:00
|
|
|
}
|
2006-02-22 03:26:52 +08:00
|
|
|
|
2006-10-08 04:35:44 +08:00
|
|
|
// Arithmetic instructions
|
2007-07-10 08:05:58 +08:00
|
|
|
defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
|
|
|
|
defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
|
|
|
|
defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
|
|
|
|
defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
|
2006-10-08 04:35:44 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
/// sse1_fp_binop_rm - Other SSE1 binops
|
|
|
|
///
|
|
|
|
/// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
|
|
|
|
/// instructions for a full-vector intrinsic form. Operations that map
|
|
|
|
/// onto C operators don't use this form since they just use the plain
|
|
|
|
/// vector form instead of having a separate vector intrinsic form.
|
|
|
|
///
|
|
|
|
/// This provides a total of eight "instructions".
|
|
|
|
///
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-07-10 08:05:58 +08:00
|
|
|
multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
|
|
|
|
SDNode OpNode,
|
|
|
|
Intrinsic F32Int,
|
|
|
|
Intrinsic V4F32Int,
|
|
|
|
bit Commutable = 0> {
|
|
|
|
|
|
|
|
// Scalar operation, reg+reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Scalar operation, reg+mem.
|
2008-05-23 08:37:07 +08:00
|
|
|
def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
|
|
|
|
(ins FR32:$src1, f32mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
|
|
|
|
|
|
|
|
// Vector operation, reg+reg.
|
2008-05-23 08:37:07 +08:00
|
|
|
def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Vector operation, reg+mem.
|
2008-05-23 08:37:07 +08:00
|
|
|
def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
|
2008-05-23 08:37:07 +08:00
|
|
|
[(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
|
2007-07-10 08:05:58 +08:00
|
|
|
|
|
|
|
// Intrinsic operation, reg+reg.
|
2008-05-23 08:37:07 +08:00
|
|
|
def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Intrinsic operation, reg+mem.
|
2008-05-23 08:37:07 +08:00
|
|
|
def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, ssmem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (F32Int VR128:$src1,
|
|
|
|
sse_load_f32:$src2))]>;
|
|
|
|
|
|
|
|
// Vector intrinsic operation, reg+reg.
|
2008-05-23 08:37:07 +08:00
|
|
|
def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Vector intrinsic operation, reg+mem.
|
2008-05-23 08:37:07 +08:00
|
|
|
def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
|
2008-05-23 08:37:07 +08:00
|
|
|
[(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
|
2007-07-10 08:05:58 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
|
|
|
|
int_x86_sse_max_ss, int_x86_sse_max_ps>;
|
|
|
|
defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
|
|
|
|
int_x86_sse_min_ss, int_x86_sse_min_ps>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SSE packed FP Instructions
|
|
|
|
|
|
|
|
// Move Instructions
|
2008-01-10 15:59:24 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movaps\t{$src, $dst|$dst, $src}", []>;
|
2008-01-07 07:38:27 +08:00
|
|
|
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movaps\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
|
2006-10-08 04:35:44 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movaps\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
|
2006-11-11 05:43:37 +08:00
|
|
|
|
2008-01-11 14:59:07 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movups\t{$src, $dst|$dst, $src}", []>;
|
2008-01-07 07:38:27 +08:00
|
|
|
let isSimpleLoad = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movups\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(set VR128:$dst, (loadv4f32 addr:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movups\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(store (v4f32 VR128:$src), addr:$dst)]>;
|
|
|
|
|
|
|
|
// Intrinsic forms of MOVUPS load and store
|
2008-01-07 07:38:27 +08:00
|
|
|
let isSimpleLoad = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movups\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movups\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-06-25 23:44:19 +08:00
|
|
|
let AddedComplexity = 20 in {
|
|
|
|
def MOVLPSrm : PSI<0x12, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movlps\t{$src2, $dst|$dst, $src2}",
|
2008-05-10 08:59:18 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (vector_shuffle VR128:$src1,
|
|
|
|
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
|
|
|
|
MOVLP_shuffle_mask)))]>;
|
2007-06-25 23:44:19 +08:00
|
|
|
def MOVHPSrm : PSI<0x16, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movhps\t{$src2, $dst|$dst, $src2}",
|
2008-05-10 08:59:18 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (vector_shuffle VR128:$src1,
|
|
|
|
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
|
|
|
|
MOVHP_shuffle_mask)))]>;
|
2007-06-25 23:44:19 +08:00
|
|
|
} // AddedComplexity
|
2008-03-05 16:19:16 +08:00
|
|
|
} // Constraints = "$src1 = $dst"
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2008-05-10 08:59:18 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movlps\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
|
|
|
|
(iPTR 0))), addr:$dst)]>;
|
|
|
|
|
|
|
|
// v2f64 extract element 1 is always custom lowered to unpack high to low
|
|
|
|
// and extract element 0 so the non-store version isn't too horrible.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movhps\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(store (f64 (vector_extract
|
|
|
|
(v2f64 (vector_shuffle
|
|
|
|
(bc_v2f64 (v4f32 VR128:$src)), (undef),
|
|
|
|
UNPCKH_shuffle_mask)), (iPTR 0))),
|
|
|
|
addr:$dst)]>;
|
|
|
|
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
let AddedComplexity = 15 in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movlhps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
MOVHP_shuffle_mask)))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movhlps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
MOVHLPS_shuffle_mask)))]>;
|
|
|
|
} // AddedComplexity
|
2008-03-05 16:19:16 +08:00
|
|
|
} // Constraints = "$src1 = $dst"
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Arithmetic
|
|
|
|
|
|
|
|
/// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
|
2007-05-03 07:11:52 +08:00
|
|
|
///
|
2007-07-10 08:05:58 +08:00
|
|
|
/// In addition, we also have a special variant of the scalar form here to
|
|
|
|
/// represent the associated intrinsic operation. This form is unlike the
|
|
|
|
/// plain scalar form, in that it takes an entire vector (instead of a
|
|
|
|
/// scalar) and leaves the top elements undefined.
|
|
|
|
///
|
|
|
|
/// And, we have a special variant form for a full-vector intrinsic form.
|
|
|
|
///
|
|
|
|
/// These four forms can each have a reg or a mem operand, so there are a
|
|
|
|
/// total of eight "instructions".
|
|
|
|
///
|
|
|
|
multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
|
|
|
|
SDNode OpNode,
|
|
|
|
Intrinsic F32Int,
|
|
|
|
Intrinsic V4F32Int,
|
|
|
|
bit Commutable = 0> {
|
|
|
|
// Scalar operation, reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set FR32:$dst, (OpNode FR32:$src))]> {
|
2007-05-03 07:11:52 +08:00
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Scalar operation, mem.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set FR32:$dst, (OpNode (load addr:$src)))]>;
|
|
|
|
|
|
|
|
// Vector operation, reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Vector operation, mem.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
|
2007-07-19 04:23:34 +08:00
|
|
|
[(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Intrinsic operation, reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (F32Int VR128:$src))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Intrinsic operation, mem.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Vector intrinsic operation, reg
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (V4F32Int VR128:$src))]> {
|
|
|
|
let isCommutable = Commutable;
|
2007-05-03 07:11:52 +08:00
|
|
|
}
|
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Vector intrinsic operation, mem
|
2007-08-03 05:06:40 +08:00
|
|
|
def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
|
2008-05-23 08:37:07 +08:00
|
|
|
[(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
}
|
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Square root.
|
|
|
|
defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
|
|
|
|
int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
|
|
|
|
|
|
|
|
// Reciprocal approximations. Note that these typically require refinement
|
|
|
|
// in order to obtain suitable precision.
|
|
|
|
defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
|
|
|
|
int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
|
|
|
|
defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
|
|
|
|
int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
|
|
|
|
|
2007-05-03 07:11:52 +08:00
|
|
|
// Logical
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
let isCommutable = 1 in {
|
|
|
|
def ANDPSrr : PSI<0x54, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v2i64
|
|
|
|
(and VR128:$src1, VR128:$src2)))]>;
|
|
|
|
def ORPSrr : PSI<0x56, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"orps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v2i64
|
|
|
|
(or VR128:$src1, VR128:$src2)))]>;
|
|
|
|
def XORPSrr : PSI<0x57, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"xorps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v2i64
|
|
|
|
(xor VR128:$src1, VR128:$src2)))]>;
|
|
|
|
}
|
|
|
|
|
|
|
|
def ANDPSrm : PSI<0x54, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andps\t{$src2, $dst|$dst, $src2}",
|
2007-07-20 07:34:10 +08:00
|
|
|
[(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
|
|
|
|
(memopv2i64 addr:$src2)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def ORPSrm : PSI<0x56, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"orps\t{$src2, $dst|$dst, $src2}",
|
2007-07-20 07:34:10 +08:00
|
|
|
[(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
|
|
|
|
(memopv2i64 addr:$src2)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def XORPSrm : PSI<0x57, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"xorps\t{$src2, $dst|$dst, $src2}",
|
2007-07-20 07:34:10 +08:00
|
|
|
[(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
|
|
|
|
(memopv2i64 addr:$src2)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def ANDNPSrr : PSI<0x55, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andnps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2i64 (and (xor VR128:$src1,
|
|
|
|
(bc_v2i64 (v4i32 immAllOnesV))),
|
|
|
|
VR128:$src2)))]>;
|
|
|
|
def ANDNPSrm : PSI<0x55, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andnps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
2007-07-20 07:34:10 +08:00
|
|
|
(v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
|
2007-05-03 07:11:52 +08:00
|
|
|
(bc_v2i64 (v4i32 immAllOnesV))),
|
2007-07-20 07:34:10 +08:00
|
|
|
(memopv2i64 addr:$src2))))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
}
|
|
|
|
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
|
2008-05-13 04:34:32 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
|
|
|
|
"cmp${cc}ps\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
|
|
|
|
VR128:$src, imm:$cc))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
|
2008-05-13 04:34:32 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
|
|
|
|
"cmp${cc}ps\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src), imm:$cc))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
}
|
2008-05-13 04:34:32 +08:00
|
|
|
def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), VR128:$src2, cond:$cc)),
|
|
|
|
(CMPPSrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
|
|
|
|
def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), (memop addr:$src2), cond:$cc)),
|
|
|
|
(CMPPSrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
// Shuffle and unpack instructions
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
let isConvertibleToThreeAddress = 1 in // Convert to pshufd
|
|
|
|
def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1,
|
2007-05-03 07:11:52 +08:00
|
|
|
VR128:$src2, i32i8imm:$src3),
|
2007-08-01 04:11:57 +08:00
|
|
|
"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (vector_shuffle
|
|
|
|
VR128:$src1, VR128:$src2,
|
|
|
|
SHUFP_shuffle_mask:$src3)))]>;
|
|
|
|
def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1,
|
2007-05-03 07:11:52 +08:00
|
|
|
f128mem:$src2, i32i8imm:$src3),
|
2007-08-01 04:11:57 +08:00
|
|
|
"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (vector_shuffle
|
2007-08-03 05:17:01 +08:00
|
|
|
VR128:$src1, (memopv4f32 addr:$src2),
|
2007-05-03 07:11:52 +08:00
|
|
|
SHUFP_shuffle_mask:$src3)))]>;
|
|
|
|
|
|
|
|
let AddedComplexity = 10 in {
|
|
|
|
def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"unpckhps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (vector_shuffle
|
|
|
|
VR128:$src1, VR128:$src2,
|
|
|
|
UNPCKH_shuffle_mask)))]>;
|
|
|
|
def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"unpckhps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (vector_shuffle
|
2007-08-03 05:17:01 +08:00
|
|
|
VR128:$src1, (memopv4f32 addr:$src2),
|
2007-05-03 07:11:52 +08:00
|
|
|
UNPCKH_shuffle_mask)))]>;
|
|
|
|
|
|
|
|
def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"unpcklps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (vector_shuffle
|
|
|
|
VR128:$src1, VR128:$src2,
|
|
|
|
UNPCKL_shuffle_mask)))]>;
|
|
|
|
def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"unpcklps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (vector_shuffle
|
2007-08-03 05:17:01 +08:00
|
|
|
VR128:$src1, (memopv4f32 addr:$src2),
|
2007-05-03 07:11:52 +08:00
|
|
|
UNPCKL_shuffle_mask)))]>;
|
|
|
|
} // AddedComplexity
|
2008-03-05 16:19:16 +08:00
|
|
|
} // Constraints = "$src1 = $dst"
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
// Mask creation
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movmskps\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movmskpd\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
|
|
|
|
|
2008-03-08 08:58:38 +08:00
|
|
|
// Prefetch intrinsic.
|
|
|
|
def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
|
|
|
|
"prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
|
|
|
|
def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
|
|
|
|
"prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
|
|
|
|
def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
|
|
|
|
"prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
|
|
|
|
def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
|
|
|
|
"prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
// Non-temporal stores
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movntps\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
|
|
|
|
|
|
|
|
// Load, store, and memory fence
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
// MXCSR register
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
|
2007-08-01 04:11:57 +08:00
|
|
|
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
// Alias instructions that map zero vector to pxor / xorp* for sse.
|
2008-01-10 13:45:39 +08:00
|
|
|
let isReMaterializable = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
|
2007-08-01 04:11:57 +08:00
|
|
|
"xorps\t$dst, $dst",
|
Fix a long standing deficiency in the X86 backend: we would
sometimes emit "zero" and "all one" vectors multiple times,
for example:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
pcmpeqd %mm0, %mm0
movq %mm0, _M2
ret
instead of:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
movq %mm0, _M2
ret
This patch fixes this by always arranging for zero/one vectors
to be defined as v4i32 or v2i32 (SSE/MMX) instead of letting them be
any random type. This ensures they get trivially CSE'd on the dag.
This fix is also important for LegalizeDAGTypes, as it gets unhappy
when the x86 backend wants BUILD_VECTOR(i64 0) to be legal even when
'i64' isn't legal.
This patch makes the following changes:
1) X86TargetLowering::LowerBUILD_VECTOR now lowers 0/1 vectors into
their canonical types.
2) The now-dead patterns are removed from the SSE/MMX .td files.
3) All the patterns in the .td file that referred to immAllOnesV or
immAllZerosV in the wrong form now use *_bc to match them with a
bitcast wrapped around them.
4) X86DAGToDAGISel::SelectScalarSSELoad is generalized to handle
bitcast'd zero vectors, which simplifies the code actually.
5) getShuffleVectorZeroOrUndef is updated to generate a shuffle that
is legal, instead of generating one that is illegal and expecting
a later legalize pass to clean it up.
6) isZeroShuffle is generalized to handle bitcast of zeros.
7) several other minor tweaks.
This patch is definite goodness, but has the potential to cause random
code quality regressions. Please be on the lookout for these and let
me know if they happen.
llvm-svn: 44310
2007-11-25 08:24:49 +08:00
|
|
|
[(set VR128:$dst, (v4i32 immAllZerosV))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2008-03-12 15:02:50 +08:00
|
|
|
let Predicates = [HasSSE1] in {
|
|
|
|
def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
|
|
|
|
def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
|
|
|
|
def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
|
|
|
|
def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
|
|
|
|
def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
|
|
|
|
}
|
|
|
|
|
2007-05-03 07:11:52 +08:00
|
|
|
// FR32 to 128-bit vector conversion.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (scalar_to_vector FR32:$src)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
|
|
|
|
|
|
|
|
// FIXME: may not be able to eliminate this movss with coalescing the src and
|
|
|
|
// dest register classes are different. We really want to write this pattern
|
|
|
|
// like this:
|
|
|
|
// def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
|
|
|
|
// (f32 FR32:$src)>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
|
|
|
|
(iPTR 0)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(store (f32 (vector_extract (v4f32 VR128:$src),
|
|
|
|
(iPTR 0))), addr:$dst)]>;
|
|
|
|
|
|
|
|
|
|
|
|
// Move to lower bits of a VR128, leaving upper bits alone.
|
|
|
|
// Three operand (but two address) aliases.
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2008-01-11 14:59:07 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
2007-05-03 07:11:52 +08:00
|
|
|
def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movss\t{$src2, $dst|$dst, $src2}", []>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
let AddedComplexity = 15 in
|
|
|
|
def MOVLPSrr : SSI<0x10, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movss\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
MOVL_shuffle_mask)))]>;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Move to lower bits of a VR128 and zeroing upper bits.
|
|
|
|
// Loading from memory automatically zeroing upper bits.
|
|
|
|
let AddedComplexity = 20 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movss\t{$src, $dst|$dst, $src}",
|
2008-05-10 05:53:03 +08:00
|
|
|
[(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
|
2008-05-08 08:57:18 +08:00
|
|
|
(loadf32 addr:$src))))))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2008-05-21 02:24:47 +08:00
|
|
|
def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
|
2008-05-08 08:57:18 +08:00
|
|
|
(MOVZSS2PSrm addr:$src)>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SSE2 Instructions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
// Move Instructions
|
2008-01-11 14:59:07 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movsd\t{$src, $dst|$dst, $src}", []>;
|
2008-01-07 07:38:27 +08:00
|
|
|
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movsd\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (loadf64 addr:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movsd\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(store FR64:$src, addr:$dst)]>;
|
2006-10-08 04:35:44 +08:00
|
|
|
|
2006-03-29 07:51:43 +08:00
|
|
|
// Conversion instructions
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttsd2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst, (fp_to_sint FR64:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttsd2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsd2ss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (fround FR64:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsd2ss\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsi2sd\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (sint_to_fp GR32:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsi2sd\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
|
2006-04-13 07:42:44 +08:00
|
|
|
|
2006-03-29 07:51:43 +08:00
|
|
|
// SSE2 instructions with XS prefix
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtss2sd\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (fextend FR32:$src))]>, XS,
|
|
|
|
Requires<[HasSSE2]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtss2sd\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
|
|
|
|
Requires<[HasSSE2]>;
|
2006-03-29 07:51:43 +08:00
|
|
|
|
2006-04-13 07:42:44 +08:00
|
|
|
// Match intrinsics which expect XMM operand(s).
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsd2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsd2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst, (int_x86_sse2_cvtsd2si
|
|
|
|
(load addr:$src)))]>;
|
2006-04-13 07:42:44 +08:00
|
|
|
|
2007-10-31 06:15:38 +08:00
|
|
|
// Match intrinisics which expect MM and XMM operand(s).
|
|
|
|
def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
|
|
|
|
"cvtpd2pi\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
|
|
|
|
def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
|
|
|
|
"cvtpd2pi\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR64:$dst, (int_x86_sse_cvtpd2pi
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src)))]>;
|
2007-10-31 06:15:38 +08:00
|
|
|
def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
|
|
|
|
"cvttpd2pi\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
|
|
|
|
def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
|
|
|
|
"cvttpd2pi\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR64:$dst, (int_x86_sse_cvttpd2pi
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src)))]>;
|
2007-10-31 06:15:38 +08:00
|
|
|
def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
|
|
|
|
"cvtpi2pd\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
|
|
|
|
def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
|
|
|
"cvtpi2pd\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR128:$dst, (int_x86_sse_cvtpi2pd
|
|
|
|
(load addr:$src)))]>;
|
|
|
|
|
2006-04-13 07:42:44 +08:00
|
|
|
// Aliases for intrinsics
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttsd2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst,
|
|
|
|
(int_x86_sse2_cvttsd2si VR128:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttsd2si\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set GR32:$dst, (int_x86_sse2_cvttsd2si
|
|
|
|
(load addr:$src)))]>;
|
2006-04-12 13:20:24 +08:00
|
|
|
|
2006-02-22 04:00:20 +08:00
|
|
|
// Comparison instructions
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
|
2007-12-21 03:57:09 +08:00
|
|
|
def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
|
2008-01-11 14:59:07 +08:00
|
|
|
let mayLoad = 1 in
|
2007-12-21 03:57:09 +08:00
|
|
|
def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
|
2006-02-22 03:26:52 +08:00
|
|
|
}
|
|
|
|
|
2007-09-25 09:57:46 +08:00
|
|
|
let Defs = [EFLAGS] in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86cmp FR64:$src1, (loadf64 addr:$src2)),
|
2007-09-25 09:57:46 +08:00
|
|
|
(implicit EFLAGS)]>;
|
|
|
|
}
|
|
|
|
|
2006-03-30 14:21:22 +08:00
|
|
|
// Aliases to match intrinsics which expect XMM operand(s).
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-12-21 03:57:09 +08:00
|
|
|
def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cmp${cc}sd\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
|
|
|
|
VR128:$src, imm:$cc))]>;
|
2007-12-21 03:57:09 +08:00
|
|
|
def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cmp${cc}sd\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
|
|
|
|
(load addr:$src), imm:$cc))]>;
|
2006-03-30 14:21:22 +08:00
|
|
|
}
|
|
|
|
|
2007-09-25 09:57:46 +08:00
|
|
|
let Defs = [EFLAGS] in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
|
2007-09-25 09:57:46 +08:00
|
|
|
(implicit EFLAGS)]>;
|
2007-09-29 08:00:36 +08:00
|
|
|
def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
|
2007-09-25 09:57:46 +08:00
|
|
|
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
|
2007-09-25 09:57:46 +08:00
|
|
|
(implicit EFLAGS)]>;
|
|
|
|
|
2007-09-29 08:00:36 +08:00
|
|
|
def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
2007-09-25 09:57:46 +08:00
|
|
|
"comisd\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
|
2007-09-25 09:57:46 +08:00
|
|
|
(implicit EFLAGS)]>;
|
2007-09-29 08:00:36 +08:00
|
|
|
def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
|
2007-09-25 09:57:46 +08:00
|
|
|
"comisd\t{$src2, $src1|$src1, $src2}",
|
2007-09-29 08:00:36 +08:00
|
|
|
[(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
|
2007-09-25 09:57:46 +08:00
|
|
|
(implicit EFLAGS)]>;
|
|
|
|
} // Defs = EFLAGS]
|
|
|
|
|
2007-06-25 23:44:19 +08:00
|
|
|
// Aliases of packed SSE2 instructions for scalar use. These all have names that
|
2006-02-22 04:00:20 +08:00
|
|
|
// start with 'Fs'.
|
2006-02-22 03:26:52 +08:00
|
|
|
|
|
|
|
// Alias instructions that map fld0 to pxor for sse.
|
2008-01-10 13:45:39 +08:00
|
|
|
let isReMaterializable = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
|
2007-08-01 04:11:57 +08:00
|
|
|
"pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
|
2006-02-22 03:26:52 +08:00
|
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
|
|
|
2007-06-25 23:44:19 +08:00
|
|
|
// Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
|
2007-05-03 07:11:52 +08:00
|
|
|
// disregarded.
|
2008-01-10 15:59:24 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movapd\t{$src, $dst|$dst, $src}", []>;
|
2006-02-22 03:26:52 +08:00
|
|
|
|
2007-06-25 23:44:19 +08:00
|
|
|
// Alias instruction to load FR64 from f128mem using movapd. Upper bits are
|
2007-05-03 07:11:52 +08:00
|
|
|
// disregarded.
|
2008-01-07 07:38:27 +08:00
|
|
|
let isSimpleLoad = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movapd\t{$src, $dst|$dst, $src}",
|
2007-07-28 01:16:43 +08:00
|
|
|
[(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
|
2006-02-22 03:26:52 +08:00
|
|
|
|
2007-05-03 07:11:52 +08:00
|
|
|
// Alias bitwise logical operations using SSE logical ops on packed FP values.
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
let isCommutable = 1 in {
|
2008-05-02 15:53:32 +08:00
|
|
|
def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
|
|
|
|
(ins FR64:$src1, FR64:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
|
2008-05-02 15:53:32 +08:00
|
|
|
def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
|
|
|
|
(ins FR64:$src1, FR64:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"orpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
|
2008-05-02 15:53:32 +08:00
|
|
|
def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
|
|
|
|
(ins FR64:$src1, FR64:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"xorpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
|
|
|
|
}
|
|
|
|
|
2008-05-02 15:53:32 +08:00
|
|
|
def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
|
|
|
|
(ins FR64:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (X86fand FR64:$src1,
|
2007-07-28 01:16:43 +08:00
|
|
|
(memopfsf64 addr:$src2)))]>;
|
2008-05-02 15:53:32 +08:00
|
|
|
def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
|
|
|
|
(ins FR64:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"orpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (X86for FR64:$src1,
|
2007-07-28 01:16:43 +08:00
|
|
|
(memopfsf64 addr:$src2)))]>;
|
2008-05-02 15:53:32 +08:00
|
|
|
def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
|
|
|
|
(ins FR64:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"xorpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (X86fxor FR64:$src1,
|
2007-07-28 01:16:43 +08:00
|
|
|
(memopfsf64 addr:$src2)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2008-01-10 15:59:24 +08:00
|
|
|
let neverHasSideEffects = 1 in {
|
2007-05-03 07:11:52 +08:00
|
|
|
def FsANDNPDrr : PDI<0x55, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andnpd\t{$src2, $dst|$dst, $src2}", []>;
|
2008-01-10 15:59:24 +08:00
|
|
|
let mayLoad = 1 in
|
2007-05-03 07:11:52 +08:00
|
|
|
def FsANDNPDrm : PDI<0x55, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andnpd\t{$src2, $dst|$dst, $src2}", []>;
|
2007-05-03 07:11:52 +08:00
|
|
|
}
|
2008-01-10 15:59:24 +08:00
|
|
|
}
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
/// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
|
|
|
|
///
|
|
|
|
/// In addition, we also have a special variant of the scalar form here to
|
|
|
|
/// represent the associated intrinsic operation. This form is unlike the
|
|
|
|
/// plain scalar form, in that it takes an entire vector (instead of a scalar)
|
|
|
|
/// and leaves the top elements undefined.
|
2007-05-03 07:11:52 +08:00
|
|
|
///
|
2007-07-10 08:05:58 +08:00
|
|
|
/// These three forms can each be reg+reg or reg+mem, so there are a total of
|
|
|
|
/// six "instructions".
|
2007-05-03 07:11:52 +08:00
|
|
|
///
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-07-10 08:05:58 +08:00
|
|
|
multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
|
|
|
|
SDNode OpNode, Intrinsic F64Int,
|
|
|
|
bit Commutable = 0> {
|
2007-05-03 07:11:52 +08:00
|
|
|
// Scalar operation, reg+reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Scalar operation, reg+mem.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
|
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Vector operation, reg+reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Vector operation, reg+mem.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
|
2007-07-19 04:23:34 +08:00
|
|
|
[(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
|
2007-07-10 08:05:58 +08:00
|
|
|
|
|
|
|
// Intrinsic operation, reg+reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
2006-02-22 10:26:30 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Intrinsic operation, reg+mem.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (F64Int VR128:$src1,
|
|
|
|
sse_load_f64:$src2))]>;
|
2006-02-22 03:26:52 +08:00
|
|
|
}
|
2007-05-03 07:11:52 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Arithmetic instructions
|
2007-07-10 08:05:58 +08:00
|
|
|
defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
|
|
|
|
defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
|
|
|
|
defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
|
|
|
|
defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
/// sse2_fp_binop_rm - Other SSE2 binops
|
|
|
|
///
|
|
|
|
/// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
|
|
|
|
/// instructions for a full-vector intrinsic form. Operations that map
|
|
|
|
/// onto C operators don't use this form since they just use the plain
|
|
|
|
/// vector form instead of having a separate vector intrinsic form.
|
|
|
|
///
|
|
|
|
/// This provides a total of eight "instructions".
|
|
|
|
///
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-07-10 08:05:58 +08:00
|
|
|
multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
|
|
|
|
SDNode OpNode,
|
|
|
|
Intrinsic F64Int,
|
|
|
|
Intrinsic V2F64Int,
|
|
|
|
bit Commutable = 0> {
|
|
|
|
|
|
|
|
// Scalar operation, reg+reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Scalar operation, reg+mem.
|
2008-05-23 08:37:07 +08:00
|
|
|
def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
|
|
|
|
(ins FR64:$src1, f64mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
|
|
|
|
|
|
|
|
// Vector operation, reg+reg.
|
2008-05-23 08:37:07 +08:00
|
|
|
def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Vector operation, reg+mem.
|
2008-05-23 08:37:07 +08:00
|
|
|
def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
|
2008-05-23 08:37:07 +08:00
|
|
|
[(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
|
2007-07-10 08:05:58 +08:00
|
|
|
|
|
|
|
// Intrinsic operation, reg+reg.
|
2008-05-23 08:37:07 +08:00
|
|
|
def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Intrinsic operation, reg+mem.
|
2008-05-23 08:37:07 +08:00
|
|
|
def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, sdmem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (F64Int VR128:$src1,
|
|
|
|
sse_load_f64:$src2))]>;
|
|
|
|
|
|
|
|
// Vector intrinsic operation, reg+reg.
|
2008-05-23 08:37:07 +08:00
|
|
|
def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Vector intrinsic operation, reg+mem.
|
2008-05-23 08:37:07 +08:00
|
|
|
def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
|
2008-05-23 08:37:07 +08:00
|
|
|
[(set VR128:$dst, (V2F64Int VR128:$src1,
|
|
|
|
(memopv2f64 addr:$src2)))]>;
|
2007-07-10 08:05:58 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
|
|
|
|
int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
|
|
|
|
defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
|
|
|
|
int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
|
2006-02-22 04:00:20 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
2006-04-15 07:32:40 +08:00
|
|
|
// SSE packed FP Instructions
|
2006-03-19 17:38:54 +08:00
|
|
|
|
2006-02-22 04:00:20 +08:00
|
|
|
// Move Instructions
|
2008-01-10 15:59:24 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movapd\t{$src, $dst|$dst, $src}", []>;
|
2008-01-07 07:38:27 +08:00
|
|
|
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movapd\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
|
2006-02-22 04:00:20 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movapd\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
|
2006-02-22 10:26:30 +08:00
|
|
|
|
2008-01-11 14:59:07 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movupd\t{$src, $dst|$dst, $src}", []>;
|
2008-01-07 07:38:27 +08:00
|
|
|
let isSimpleLoad = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movupd\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(set VR128:$dst, (loadv2f64 addr:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movupd\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(store (v2f64 VR128:$src), addr:$dst)]>;
|
|
|
|
|
|
|
|
// Intrinsic forms of MOVUPD load and store
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movupd\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movupd\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
|
2006-02-22 10:26:30 +08:00
|
|
|
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
let AddedComplexity = 20 in {
|
|
|
|
def MOVLPDrm : PDI<0x12, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movlpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (vector_shuffle VR128:$src1,
|
|
|
|
(scalar_to_vector (loadf64 addr:$src2)),
|
|
|
|
MOVLP_shuffle_mask)))]>;
|
|
|
|
def MOVHPDrm : PDI<0x16, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movhpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (vector_shuffle VR128:$src1,
|
|
|
|
(scalar_to_vector (loadf64 addr:$src2)),
|
|
|
|
MOVHP_shuffle_mask)))]>;
|
|
|
|
} // AddedComplexity
|
2008-03-05 16:19:16 +08:00
|
|
|
} // Constraints = "$src1 = $dst"
|
2006-03-28 10:43:26 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movlpd\t{$src, $dst|$dst, $src}",
|
2006-04-04 06:30:54 +08:00
|
|
|
[(store (f64 (vector_extract (v2f64 VR128:$src),
|
2006-06-15 16:14:54 +08:00
|
|
|
(iPTR 0))), addr:$dst)]>;
|
2006-03-28 15:01:28 +08:00
|
|
|
|
2006-04-08 05:20:58 +08:00
|
|
|
// v2f64 extract element 1 is always custom lowered to unpack high to low
|
|
|
|
// and extract element 0 so the non-store version isn't too horrible.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movhpd\t{$src, $dst|$dst, $src}",
|
2006-04-04 06:30:54 +08:00
|
|
|
[(store (f64 (vector_extract
|
|
|
|
(v2f64 (vector_shuffle VR128:$src, (undef),
|
2006-06-15 16:14:54 +08:00
|
|
|
UNPCKH_shuffle_mask)), (iPTR 0))),
|
2006-04-04 06:30:54 +08:00
|
|
|
addr:$dst)]>;
|
2006-02-22 10:26:30 +08:00
|
|
|
|
|
|
|
// SSE2 instructions without OpSize prefix
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtdq2ps\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
|
|
|
|
TB, Requires<[HasSSE2]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
2008-03-14 15:46:48 +08:00
|
|
|
"cvtdq2ps\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtdq2ps
|
|
|
|
(bitconvert (memopv2i64 addr:$src))))]>,
|
2006-06-01 03:00:07 +08:00
|
|
|
TB, Requires<[HasSSE2]>;
|
2006-02-22 10:26:30 +08:00
|
|
|
|
|
|
|
// SSE2 instructions with XS prefix
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtdq2pd\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
|
|
|
|
XS, Requires<[HasSSE2]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
2008-03-14 15:46:48 +08:00
|
|
|
"cvtdq2pd\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtdq2pd
|
|
|
|
(bitconvert (memopv2i64 addr:$src))))]>,
|
2006-06-01 03:00:07 +08:00
|
|
|
XS, Requires<[HasSSE2]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2008-03-14 15:46:48 +08:00
|
|
|
"cvtps2dq\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtps2dq\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtps2dq
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src)))]>;
|
2006-04-12 13:20:24 +08:00
|
|
|
// SSE2 packed instructions with XS prefix
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttps2dq\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
|
|
|
|
XS, Requires<[HasSSE2]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttps2dq\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvttps2dq
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src)))]>,
|
2006-06-01 03:00:07 +08:00
|
|
|
XS, Requires<[HasSSE2]>;
|
2006-04-12 13:20:24 +08:00
|
|
|
|
2006-02-22 10:26:30 +08:00
|
|
|
// SSE2 packed instructions with XD prefix
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtpd2dq\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
|
|
|
|
XD, Requires<[HasSSE2]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtpd2dq\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtpd2dq
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src)))]>,
|
2006-06-01 03:00:07 +08:00
|
|
|
XD, Requires<[HasSSE2]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
|
2008-03-14 15:46:48 +08:00
|
|
|
def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvttpd2dq
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src)))]>;
|
2006-02-22 10:26:30 +08:00
|
|
|
|
|
|
|
// SSE2 instructions without OpSize prefix
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtps2pd\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
|
|
|
|
TB, Requires<[HasSSE2]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f64mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtps2pd\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtps2pd
|
2006-10-07 14:17:43 +08:00
|
|
|
(load addr:$src)))]>,
|
2006-06-01 03:00:07 +08:00
|
|
|
TB, Requires<[HasSSE2]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtpd2ps\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtpd2ps\t{$src, $dst|$dst, $src}",
|
2006-06-01 03:00:07 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtpd2ps
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src)))]>;
|
2006-02-22 10:26:30 +08:00
|
|
|
|
2006-04-13 07:42:44 +08:00
|
|
|
// Match intrinsics which expect XMM operand(s).
|
|
|
|
// Aliases for intrinsics
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2006-04-13 07:42:44 +08:00
|
|
|
def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsi2sd\t{$src2, $dst|$dst, $src2}",
|
2006-04-13 07:42:44 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
|
2006-05-16 15:21:53 +08:00
|
|
|
GR32:$src2))]>;
|
2006-04-13 07:42:44 +08:00
|
|
|
def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsi2sd\t{$src2, $dst|$dst, $src2}",
|
2006-04-13 07:42:44 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
|
|
|
|
(loadi32 addr:$src2)))]>;
|
|
|
|
def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsd2ss\t{$src2, $dst|$dst, $src2}",
|
2006-04-13 07:42:44 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
|
|
|
|
VR128:$src2))]>;
|
|
|
|
def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtsd2ss\t{$src2, $dst|$dst, $src2}",
|
2006-04-13 07:42:44 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
|
2006-10-07 14:17:43 +08:00
|
|
|
(load addr:$src2)))]>;
|
2006-04-13 07:42:44 +08:00
|
|
|
def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtss2sd\t{$src2, $dst|$dst, $src2}",
|
2006-04-13 07:42:44 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
|
|
|
|
VR128:$src2))]>, XS,
|
|
|
|
Requires<[HasSSE2]>;
|
|
|
|
def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"cvtss2sd\t{$src2, $dst|$dst, $src2}",
|
2006-04-13 07:42:44 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
|
2006-10-07 14:17:43 +08:00
|
|
|
(load addr:$src2)))]>, XS,
|
2006-04-13 07:42:44 +08:00
|
|
|
Requires<[HasSSE2]>;
|
|
|
|
}
|
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Arithmetic
|
|
|
|
|
|
|
|
/// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
|
2006-10-08 05:17:13 +08:00
|
|
|
///
|
2007-07-10 08:05:58 +08:00
|
|
|
/// In addition, we also have a special variant of the scalar form here to
|
|
|
|
/// represent the associated intrinsic operation. This form is unlike the
|
|
|
|
/// plain scalar form, in that it takes an entire vector (instead of a
|
|
|
|
/// scalar) and leaves the top elements undefined.
|
|
|
|
///
|
|
|
|
/// And, we have a special variant form for a full-vector intrinsic form.
|
|
|
|
///
|
|
|
|
/// These four forms can each have a reg or a mem operand, so there are a
|
|
|
|
/// total of eight "instructions".
|
|
|
|
///
|
|
|
|
multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
|
|
|
|
SDNode OpNode,
|
|
|
|
Intrinsic F64Int,
|
|
|
|
Intrinsic V2F64Int,
|
|
|
|
bit Commutable = 0> {
|
|
|
|
// Scalar operation, reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set FR64:$dst, (OpNode FR64:$src))]> {
|
2006-10-08 05:17:13 +08:00
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Scalar operation, mem.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set FR64:$dst, (OpNode (load addr:$src)))]>;
|
|
|
|
|
|
|
|
// Vector operation, reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
2006-02-22 10:26:30 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Vector operation, mem.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
|
2007-07-19 04:23:34 +08:00
|
|
|
[(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
|
2006-04-15 05:59:03 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Intrinsic operation, reg.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (F64Int VR128:$src))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
2006-02-22 10:26:30 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Intrinsic operation, mem.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
|
2006-10-07 13:50:25 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Vector intrinsic operation, reg
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
|
2007-07-10 08:05:58 +08:00
|
|
|
[(set VR128:$dst, (V2F64Int VR128:$src))]> {
|
|
|
|
let isCommutable = Commutable;
|
2007-05-03 07:11:52 +08:00
|
|
|
}
|
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Vector intrinsic operation, mem
|
2007-08-03 05:06:40 +08:00
|
|
|
def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
|
2008-05-23 08:37:07 +08:00
|
|
|
[(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
|
2006-04-04 07:49:17 +08:00
|
|
|
}
|
2006-02-22 04:00:20 +08:00
|
|
|
|
2007-07-10 08:05:58 +08:00
|
|
|
// Square root.
|
|
|
|
defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
|
|
|
|
int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
|
|
|
|
|
|
|
|
// There is no f64 version of the reciprocal approximation instructions.
|
|
|
|
|
2006-02-22 04:00:20 +08:00
|
|
|
// Logical
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
let isCommutable = 1 in {
|
|
|
|
def ANDPDrr : PDI<0x54, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(and (bc_v2i64 (v2f64 VR128:$src1)),
|
2006-10-07 14:27:03 +08:00
|
|
|
(bc_v2i64 (v2f64 VR128:$src2))))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def ORPDrr : PDI<0x56, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"orpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(or (bc_v2i64 (v2f64 VR128:$src1)),
|
2006-10-07 14:27:03 +08:00
|
|
|
(bc_v2i64 (v2f64 VR128:$src2))))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def XORPDrr : PDI<0x57, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"xorpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(xor (bc_v2i64 (v2f64 VR128:$src1)),
|
|
|
|
(bc_v2i64 (v2f64 VR128:$src2))))]>;
|
|
|
|
}
|
|
|
|
|
|
|
|
def ANDPDrm : PDI<0x54, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(and (bc_v2i64 (v2f64 VR128:$src1)),
|
2007-07-20 07:34:10 +08:00
|
|
|
(memopv2i64 addr:$src2)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def ORPDrm : PDI<0x56, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"orpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(or (bc_v2i64 (v2f64 VR128:$src1)),
|
2007-07-20 07:34:10 +08:00
|
|
|
(memopv2i64 addr:$src2)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def XORPDrm : PDI<0x57, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"xorpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(xor (bc_v2i64 (v2f64 VR128:$src1)),
|
2007-07-20 07:34:10 +08:00
|
|
|
(memopv2i64 addr:$src2)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def ANDNPDrr : PDI<0x55, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andnpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
|
|
|
|
(bc_v2i64 (v2f64 VR128:$src2))))]>;
|
|
|
|
def ANDNPDrm : PDI<0x55, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"andnpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
|
2007-07-20 07:34:10 +08:00
|
|
|
(memopv2i64 addr:$src2)))]>;
|
2006-02-22 10:26:30 +08:00
|
|
|
}
|
|
|
|
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
|
2008-03-14 15:46:48 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
|
|
|
|
"cmp${cc}pd\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
|
2008-05-13 04:34:32 +08:00
|
|
|
VR128:$src, imm:$cc))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
|
2008-03-14 15:46:48 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
|
|
|
|
"cmp${cc}pd\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src), imm:$cc))]>;
|
2006-02-22 04:00:20 +08:00
|
|
|
}
|
2008-05-13 04:34:32 +08:00
|
|
|
def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), VR128:$src2, cond:$cc)),
|
|
|
|
(CMPPDrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
|
|
|
|
def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), (memop addr:$src2), cond:$cc)),
|
|
|
|
(CMPPDrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
|
2006-02-22 04:00:20 +08:00
|
|
|
|
2006-02-22 10:26:30 +08:00
|
|
|
// Shuffle and unpack instructions
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
|
2008-03-14 15:46:48 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
|
|
|
|
"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
|
|
[(set VR128:$dst, (v2f64 (vector_shuffle
|
|
|
|
VR128:$src1, VR128:$src2,
|
|
|
|
SHUFP_shuffle_mask:$src3)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1,
|
2007-05-03 07:11:52 +08:00
|
|
|
f128mem:$src2, i8imm:$src3),
|
2007-08-01 04:11:57 +08:00
|
|
|
"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (vector_shuffle
|
2007-08-03 05:17:01 +08:00
|
|
|
VR128:$src1, (memopv2f64 addr:$src2),
|
2007-05-03 07:11:52 +08:00
|
|
|
SHUFP_shuffle_mask:$src3)))]>;
|
|
|
|
|
|
|
|
let AddedComplexity = 10 in {
|
|
|
|
def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"unpckhpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (vector_shuffle
|
|
|
|
VR128:$src1, VR128:$src2,
|
|
|
|
UNPCKH_shuffle_mask)))]>;
|
|
|
|
def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"unpckhpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (vector_shuffle
|
2007-08-03 05:17:01 +08:00
|
|
|
VR128:$src1, (memopv2f64 addr:$src2),
|
2007-05-03 07:11:52 +08:00
|
|
|
UNPCKH_shuffle_mask)))]>;
|
|
|
|
|
|
|
|
def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"unpcklpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (vector_shuffle
|
|
|
|
VR128:$src1, VR128:$src2,
|
|
|
|
UNPCKL_shuffle_mask)))]>;
|
|
|
|
def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"unpcklpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (vector_shuffle
|
2007-08-03 05:17:01 +08:00
|
|
|
VR128:$src1, (memopv2f64 addr:$src2),
|
2007-05-03 07:11:52 +08:00
|
|
|
UNPCKL_shuffle_mask)))]>;
|
|
|
|
} // AddedComplexity
|
2008-03-05 16:19:16 +08:00
|
|
|
} // Constraints = "$src1 = $dst"
|
2006-10-07 14:33:36 +08:00
|
|
|
|
2006-04-01 05:29:33 +08:00
|
|
|
|
2006-02-22 04:00:20 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SSE integer instructions
|
|
|
|
|
|
|
|
// Move Instructions
|
2008-01-11 14:59:07 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movdqa\t{$src, $dst|$dst, $src}", []>;
|
2008-01-11 14:59:07 +08:00
|
|
|
let isSimpleLoad = 1, mayLoad = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movdqa\t{$src, $dst|$dst, $src}",
|
2007-07-20 08:27:43 +08:00
|
|
|
[/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
|
2008-01-11 14:59:07 +08:00
|
|
|
let mayStore = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movdqa\t{$src, $dst|$dst, $src}",
|
2007-07-20 08:27:43 +08:00
|
|
|
[/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
|
2008-01-11 14:59:07 +08:00
|
|
|
let isSimpleLoad = 1, mayLoad = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movdqu\t{$src, $dst|$dst, $src}",
|
2007-07-20 08:27:43 +08:00
|
|
|
[/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
|
2006-04-15 07:32:40 +08:00
|
|
|
XS, Requires<[HasSSE2]>;
|
2008-01-11 14:59:07 +08:00
|
|
|
let mayStore = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movdqu\t{$src, $dst|$dst, $src}",
|
2007-07-20 08:27:43 +08:00
|
|
|
[/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
|
2006-04-15 07:32:40 +08:00
|
|
|
XS, Requires<[HasSSE2]>;
|
2006-03-23 15:44:07 +08:00
|
|
|
|
2007-07-19 04:23:34 +08:00
|
|
|
// Intrinsic forms of MOVDQU load and store
|
2008-01-07 07:38:27 +08:00
|
|
|
let isSimpleLoad = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movdqu\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
|
|
|
|
XS, Requires<[HasSSE2]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movdqu\t{$src, $dst|$dst, $src}",
|
2007-07-19 04:23:34 +08:00
|
|
|
[(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
|
|
|
|
XS, Requires<[HasSSE2]>;
|
2006-10-08 02:39:00 +08:00
|
|
|
|
2008-03-05 16:11:27 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2006-10-08 03:02:31 +08:00
|
|
|
multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
|
|
|
|
bit Commutable = 0> {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
2006-10-08 02:39:00 +08:00
|
|
|
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
2006-10-08 02:39:00 +08:00
|
|
|
[(set VR128:$dst, (IntId VR128:$src1,
|
2007-07-19 04:23:34 +08:00
|
|
|
(bitconvert (memopv2i64 addr:$src2))))]>;
|
2006-10-08 02:39:00 +08:00
|
|
|
}
|
|
|
|
|
2008-05-03 08:52:09 +08:00
|
|
|
multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
|
|
|
|
string OpcodeStr,
|
|
|
|
Intrinsic IntId, Intrinsic IntId2> {
|
|
|
|
def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
|
|
|
|
def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst, (IntId VR128:$src1,
|
|
|
|
(bitconvert (memopv2i64 addr:$src2))))]>;
|
|
|
|
def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
|
|
|
|
}
|
|
|
|
|
2006-10-08 03:14:49 +08:00
|
|
|
/// PDI_binop_rm - Simple SSE2 binary operator.
|
|
|
|
multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
|
|
|
ValueType OpVT, bit Commutable = 0> {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
2006-10-08 03:14:49 +08:00
|
|
|
[(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
2006-10-08 03:14:49 +08:00
|
|
|
[(set VR128:$dst, (OpVT (OpNode VR128:$src1,
|
2007-07-19 04:23:34 +08:00
|
|
|
(bitconvert (memopv2i64 addr:$src2)))))]>;
|
2006-10-08 03:14:49 +08:00
|
|
|
}
|
2006-10-08 03:34:33 +08:00
|
|
|
|
|
|
|
/// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
|
|
|
|
///
|
|
|
|
/// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
|
|
|
|
/// to collapse (bitconvert VT to VT) into its operand.
|
|
|
|
///
|
|
|
|
multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
|
|
|
bit Commutable = 0> {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
|
|
|
|
let isCommutable = Commutable;
|
2007-04-11 06:10:25 +08:00
|
|
|
}
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
2007-07-19 04:23:34 +08:00
|
|
|
[(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
|
2007-04-11 06:10:25 +08:00
|
|
|
}
|
2006-10-08 03:14:49 +08:00
|
|
|
|
2008-03-05 16:19:16 +08:00
|
|
|
} // Constraints = "$src1 = $dst"
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2006-03-23 09:57:24 +08:00
|
|
|
// 128-bit Integer Arithmetic
|
2006-10-08 03:14:49 +08:00
|
|
|
|
|
|
|
defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
|
|
|
|
defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
|
|
|
|
defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
|
2006-10-08 03:34:33 +08:00
|
|
|
defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
|
2006-04-13 08:43:35 +08:00
|
|
|
|
2006-10-08 03:02:31 +08:00
|
|
|
defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
|
|
|
|
defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
|
|
|
|
defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
|
|
|
|
defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
|
2006-04-13 08:43:35 +08:00
|
|
|
|
2006-10-08 03:14:49 +08:00
|
|
|
defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
|
|
|
|
defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
|
|
|
|
defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
|
2006-10-08 03:34:33 +08:00
|
|
|
defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
|
2006-04-13 08:43:35 +08:00
|
|
|
|
2006-10-08 03:02:31 +08:00
|
|
|
defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
|
|
|
|
defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
|
|
|
|
defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
|
|
|
|
defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
|
2006-10-08 02:48:46 +08:00
|
|
|
|
2006-10-08 03:14:49 +08:00
|
|
|
defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
|
2006-04-13 13:24:54 +08:00
|
|
|
|
2006-10-08 03:02:31 +08:00
|
|
|
defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
|
|
|
|
defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
|
|
|
|
defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
|
2006-04-13 14:11:45 +08:00
|
|
|
|
2006-10-08 03:02:31 +08:00
|
|
|
defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
|
2006-04-13 14:11:45 +08:00
|
|
|
|
2006-10-08 03:02:31 +08:00
|
|
|
defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
|
|
|
|
defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
|
2006-10-07 15:06:17 +08:00
|
|
|
|
|
|
|
|
2006-10-08 03:02:31 +08:00
|
|
|
defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
|
|
|
|
defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
|
|
|
|
defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
|
|
|
|
defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
|
|
|
|
defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
|
2006-03-30 07:07:14 +08:00
|
|
|
|
2006-10-07 15:06:17 +08:00
|
|
|
|
2008-05-03 08:52:09 +08:00
|
|
|
defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
|
|
|
|
int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
|
|
|
|
defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
|
|
|
|
int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
|
|
|
|
defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
|
|
|
|
int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
|
|
|
|
|
|
|
|
defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
|
|
|
|
int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
|
|
|
|
defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
|
|
|
|
int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
|
2008-05-14 01:52:09 +08:00
|
|
|
defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
|
2008-05-03 08:52:09 +08:00
|
|
|
int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
|
|
|
|
|
|
|
|
defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
|
|
|
|
int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
|
2008-05-13 09:47:52 +08:00
|
|
|
defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
|
2008-05-03 08:52:09 +08:00
|
|
|
int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
|
2006-10-07 15:06:17 +08:00
|
|
|
|
2006-10-08 03:49:05 +08:00
|
|
|
// 128-bit logical shifts.
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
|
2007-05-03 07:11:52 +08:00
|
|
|
def PSLLDQri : PDIi8<0x73, MRM7r,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"pslldq\t{$src2, $dst|$dst, $src2}", []>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def PSRLDQri : PDIi8<0x73, MRM3r,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"psrldq\t{$src2, $dst|$dst, $src2}", []>;
|
2007-05-03 07:11:52 +08:00
|
|
|
// PSRADQri doesn't exist in SSE[1-3].
|
2006-04-05 05:49:39 +08:00
|
|
|
}
|
|
|
|
|
2006-10-08 03:49:05 +08:00
|
|
|
let Predicates = [HasSSE2] in {
|
|
|
|
def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
|
|
|
|
(v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
|
|
|
|
def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
|
|
|
|
(v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
|
2007-01-05 15:55:56 +08:00
|
|
|
def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
|
|
|
|
(v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
|
2006-10-08 03:49:05 +08:00
|
|
|
}
|
|
|
|
|
2006-03-30 07:07:14 +08:00
|
|
|
// Logical
|
2006-10-08 03:37:30 +08:00
|
|
|
defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
|
|
|
|
defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
|
|
|
|
defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
|
2006-03-30 07:07:14 +08:00
|
|
|
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
def PANDNrr : PDI<0xDF, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"pandn\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
|
|
|
|
VR128:$src2)))]>;
|
|
|
|
|
|
|
|
def PANDNrm : PDI<0xDF, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"pandn\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
|
2007-08-03 05:17:01 +08:00
|
|
|
(memopv2i64 addr:$src2))))]>;
|
2006-03-30 07:07:14 +08:00
|
|
|
}
|
2006-03-25 17:37:23 +08:00
|
|
|
|
2006-10-07 14:47:08 +08:00
|
|
|
// SSE2 Integer comparison
|
2007-05-03 07:11:52 +08:00
|
|
|
defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
|
|
|
|
defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
|
|
|
|
defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
|
|
|
|
defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
|
|
|
|
defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
|
|
|
|
defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
|
2006-04-15 07:32:40 +08:00
|
|
|
|
2008-05-13 07:09:43 +08:00
|
|
|
def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), VR128:$src2, SETEQ)),
|
|
|
|
(PCMPEQBrr VR128:$src1, VR128:$src2)>;
|
|
|
|
def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), (memop addr:$src2), SETEQ)),
|
|
|
|
(PCMPEQBrm VR128:$src1, addr:$src2)>;
|
|
|
|
def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), VR128:$src2, SETEQ)),
|
|
|
|
(PCMPEQWrr VR128:$src1, VR128:$src2)>;
|
|
|
|
def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), (memop addr:$src2), SETEQ)),
|
|
|
|
(PCMPEQWrm VR128:$src1, addr:$src2)>;
|
|
|
|
def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), VR128:$src2, SETEQ)),
|
|
|
|
(PCMPEQDrr VR128:$src1, VR128:$src2)>;
|
|
|
|
def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), (memop addr:$src2), SETEQ)),
|
|
|
|
(PCMPEQDrm VR128:$src1, addr:$src2)>;
|
|
|
|
|
|
|
|
def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), VR128:$src2, SETGT)),
|
|
|
|
(PCMPGTBrr VR128:$src1, VR128:$src2)>;
|
|
|
|
def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), (memop addr:$src2), SETGT)),
|
|
|
|
(PCMPGTBrm VR128:$src1, addr:$src2)>;
|
|
|
|
def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), VR128:$src2, SETGT)),
|
|
|
|
(PCMPGTWrr VR128:$src1, VR128:$src2)>;
|
|
|
|
def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), (memop addr:$src2), SETGT)),
|
|
|
|
(PCMPGTWrm VR128:$src1, addr:$src2)>;
|
|
|
|
def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), VR128:$src2, SETGT)),
|
|
|
|
(PCMPGTDrr VR128:$src1, VR128:$src2)>;
|
|
|
|
def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), (memop addr:$src2), SETGT)),
|
|
|
|
(PCMPGTDrm VR128:$src1, addr:$src2)>;
|
|
|
|
|
|
|
|
|
2006-03-30 07:07:14 +08:00
|
|
|
// Pack instructions
|
2006-10-08 03:02:31 +08:00
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defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
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defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
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defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
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2006-03-30 07:07:14 +08:00
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// Shuffle and unpack instructions
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2006-04-05 03:12:30 +08:00
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def PSHUFDri : PDIi8<0x70, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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(outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
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2007-08-01 04:11:57 +08:00
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"pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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2006-03-30 07:07:14 +08:00
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[(set VR128:$dst, (v4i32 (vector_shuffle
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VR128:$src1, (undef),
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PSHUFD_shuffle_mask:$src2)))]>;
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2006-04-05 03:12:30 +08:00
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def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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(outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
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2007-08-01 04:11:57 +08:00
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"pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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2006-03-30 07:07:14 +08:00
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[(set VR128:$dst, (v4i32 (vector_shuffle
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2007-07-19 04:23:34 +08:00
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(bc_v4i32(memopv2i64 addr:$src1)),
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2006-04-13 01:12:36 +08:00
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(undef),
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2006-03-30 07:07:14 +08:00
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PSHUFD_shuffle_mask:$src2)))]>;
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// SSE2 with ImmT == Imm8 and XS prefix.
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2006-04-05 03:12:30 +08:00
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def PSHUFHWri : Ii8<0x70, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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(outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
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2007-08-01 04:11:57 +08:00
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"pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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2006-03-30 07:07:14 +08:00
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[(set VR128:$dst, (v8i16 (vector_shuffle
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VR128:$src1, (undef),
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PSHUFHW_shuffle_mask:$src2)))]>,
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XS, Requires<[HasSSE2]>;
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2006-04-05 03:12:30 +08:00
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def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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(outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
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2007-08-01 04:11:57 +08:00
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"pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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2006-03-30 07:07:14 +08:00
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[(set VR128:$dst, (v8i16 (vector_shuffle
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2007-07-19 04:23:34 +08:00
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(bc_v8i16 (memopv2i64 addr:$src1)),
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2006-04-13 01:12:36 +08:00
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(undef),
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2006-03-30 07:07:14 +08:00
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PSHUFHW_shuffle_mask:$src2)))]>,
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XS, Requires<[HasSSE2]>;
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// SSE2 with ImmT == Imm8 and XD prefix.
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2006-04-05 03:12:30 +08:00
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def PSHUFLWri : Ii8<0x70, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
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2007-08-01 04:11:57 +08:00
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"pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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2006-03-30 07:07:14 +08:00
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[(set VR128:$dst, (v8i16 (vector_shuffle
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VR128:$src1, (undef),
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PSHUFLW_shuffle_mask:$src2)))]>,
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XD, Requires<[HasSSE2]>;
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2006-04-05 03:12:30 +08:00
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def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
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(outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
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2007-08-01 04:11:57 +08:00
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"pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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2006-03-30 07:07:14 +08:00
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[(set VR128:$dst, (v8i16 (vector_shuffle
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2007-07-19 04:23:34 +08:00
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(bc_v8i16 (memopv2i64 addr:$src1)),
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2006-04-13 01:12:36 +08:00
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(undef),
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2006-03-30 07:07:14 +08:00
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PSHUFLW_shuffle_mask:$src2)))]>,
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XD, Requires<[HasSSE2]>;
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2006-03-25 17:37:23 +08:00
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2008-03-05 16:19:16 +08:00
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let Constraints = "$src1 = $dst" in {
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2007-05-03 07:11:52 +08:00
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def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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2007-08-01 04:11:57 +08:00
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"punpcklbw\t{$src2, $dst|$dst, $src2}",
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2007-05-03 07:11:52 +08:00
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[(set VR128:$dst,
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(v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
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(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
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2007-08-01 04:11:57 +08:00
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"punpcklbw\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
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[(set VR128:$dst,
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(v16i8 (vector_shuffle VR128:$src1,
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2007-07-19 04:23:34 +08:00
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(bc_v16i8 (memopv2i64 addr:$src2)),
|
2007-05-03 07:11:52 +08:00
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
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|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
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"punpcklwd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
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[(set VR128:$dst,
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(v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
|
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UNPCKL_shuffle_mask)))]>;
|
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|
def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
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|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
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|
"punpcklwd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
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[(set VR128:$dst,
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(v8i16 (vector_shuffle VR128:$src1,
|
2007-07-19 04:23:34 +08:00
|
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(bc_v8i16 (memopv2i64 addr:$src2)),
|
2007-05-03 07:11:52 +08:00
|
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UNPCKL_shuffle_mask)))]>;
|
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|
def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
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|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
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|
"punpckldq\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
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[(set VR128:$dst,
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(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
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UNPCKL_shuffle_mask)))]>;
|
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|
def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"punpckldq\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
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|
[(set VR128:$dst,
|
|
|
|
(v4i32 (vector_shuffle VR128:$src1,
|
2007-07-19 04:23:34 +08:00
|
|
|
(bc_v4i32 (memopv2i64 addr:$src2)),
|
2007-05-03 07:11:52 +08:00
|
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|
UNPCKL_shuffle_mask)))]>;
|
|
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|
def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"punpcklqdq\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
UNPCKL_shuffle_mask)))]>;
|
|
|
|
def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"punpcklqdq\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2i64 (vector_shuffle VR128:$src1,
|
2007-07-19 04:23:34 +08:00
|
|
|
(memopv2i64 addr:$src2),
|
2007-05-03 07:11:52 +08:00
|
|
|
UNPCKL_shuffle_mask)))]>;
|
|
|
|
|
|
|
|
def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"punpckhbw\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
UNPCKH_shuffle_mask)))]>;
|
|
|
|
def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"punpckhbw\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v16i8 (vector_shuffle VR128:$src1,
|
2007-07-19 04:23:34 +08:00
|
|
|
(bc_v16i8 (memopv2i64 addr:$src2)),
|
2007-05-03 07:11:52 +08:00
|
|
|
UNPCKH_shuffle_mask)))]>;
|
|
|
|
def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"punpckhwd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
UNPCKH_shuffle_mask)))]>;
|
|
|
|
def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"punpckhwd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v8i16 (vector_shuffle VR128:$src1,
|
2007-07-19 04:23:34 +08:00
|
|
|
(bc_v8i16 (memopv2i64 addr:$src2)),
|
2007-05-03 07:11:52 +08:00
|
|
|
UNPCKH_shuffle_mask)))]>;
|
|
|
|
def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"punpckhdq\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
UNPCKH_shuffle_mask)))]>;
|
|
|
|
def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"punpckhdq\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4i32 (vector_shuffle VR128:$src1,
|
2007-07-19 04:23:34 +08:00
|
|
|
(bc_v4i32 (memopv2i64 addr:$src2)),
|
2007-05-03 07:11:52 +08:00
|
|
|
UNPCKH_shuffle_mask)))]>;
|
|
|
|
def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"punpckhqdq\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
UNPCKH_shuffle_mask)))]>;
|
|
|
|
def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"punpckhqdq\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2i64 (vector_shuffle VR128:$src1,
|
2007-07-19 04:23:34 +08:00
|
|
|
(memopv2i64 addr:$src2),
|
2007-05-03 07:11:52 +08:00
|
|
|
UNPCKH_shuffle_mask)))]>;
|
2006-03-23 09:57:24 +08:00
|
|
|
}
|
2006-03-21 15:09:35 +08:00
|
|
|
|
2006-04-01 03:22:53 +08:00
|
|
|
// Extract / Insert
|
2006-04-15 07:32:40 +08:00
|
|
|
def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
2006-05-16 15:21:53 +08:00
|
|
|
[(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
|
2008-02-11 12:19:36 +08:00
|
|
|
imm:$src2))]>;
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1,
|
2007-05-03 07:11:52 +08:00
|
|
|
GR32:$src2, i32i8imm:$src3),
|
2007-08-01 04:11:57 +08:00
|
|
|
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
2008-02-11 12:19:36 +08:00
|
|
|
(X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1,
|
2007-05-03 07:11:52 +08:00
|
|
|
i16mem:$src2, i32i8imm:$src3),
|
2007-08-01 04:11:57 +08:00
|
|
|
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
2008-02-11 12:19:36 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
|
|
|
|
imm:$src3))]>;
|
2006-04-01 03:22:53 +08:00
|
|
|
}
|
|
|
|
|
2006-03-30 08:33:26 +08:00
|
|
|
// Mask creation
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"pmovmskb\t{$src, $dst|$dst, $src}",
|
2006-05-16 15:21:53 +08:00
|
|
|
[(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
|
2006-03-30 08:33:26 +08:00
|
|
|
|
2006-04-11 14:57:30 +08:00
|
|
|
// Conditional store
|
2007-09-12 03:55:27 +08:00
|
|
|
let Uses = [EDI] in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
|
2007-08-01 04:11:57 +08:00
|
|
|
"maskmovdqu\t{$mask, $src|$src, $mask}",
|
2007-09-12 03:55:27 +08:00
|
|
|
[(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
|
2006-04-11 14:57:30 +08:00
|
|
|
|
2006-03-25 14:03:26 +08:00
|
|
|
// Non-temporal stores
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movntpd\t{$src, $dst|$dst, $src}",
|
2006-04-11 14:57:30 +08:00
|
|
|
[(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movntdq\t{$src, $dst|$dst, $src}",
|
2006-04-11 14:57:30 +08:00
|
|
|
[(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movnti\t{$src, $dst|$dst, $src}",
|
2006-05-16 15:21:53 +08:00
|
|
|
[(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
|
2006-04-11 14:57:30 +08:00
|
|
|
TB, Requires<[HasSSE2]>;
|
2006-03-25 14:03:26 +08:00
|
|
|
|
2006-04-14 15:43:12 +08:00
|
|
|
// Flush cache
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
|
2006-04-14 15:43:12 +08:00
|
|
|
TB, Requires<[HasSSE2]>;
|
|
|
|
|
|
|
|
// Load, store, and memory fence
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def LFENCE : I<0xAE, MRM5m, (outs), (ins),
|
2006-04-14 15:43:12 +08:00
|
|
|
"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MFENCE : I<0xAE, MRM6m, (outs), (ins),
|
2006-04-14 15:43:12 +08:00
|
|
|
"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
|
2006-03-25 14:03:26 +08:00
|
|
|
|
2008-02-16 09:24:58 +08:00
|
|
|
//TODO: custom lower this so as to never even generate the noop
|
|
|
|
def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
|
|
|
|
(i8 0)), (NOOP)>;
|
|
|
|
def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
|
|
|
|
def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
|
|
|
|
def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
|
|
|
|
(i8 1)), (MFENCE)>;
|
|
|
|
|
2006-03-26 17:53:12 +08:00
|
|
|
// Alias instructions that map zero vector to pxor / xorp* for sse.
|
2008-01-10 13:45:39 +08:00
|
|
|
let isReMaterializable = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
|
2007-08-01 04:11:57 +08:00
|
|
|
"pcmpeqd\t$dst, $dst",
|
Fix a long standing deficiency in the X86 backend: we would
sometimes emit "zero" and "all one" vectors multiple times,
for example:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
pcmpeqd %mm0, %mm0
movq %mm0, _M2
ret
instead of:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
movq %mm0, _M2
ret
This patch fixes this by always arranging for zero/one vectors
to be defined as v4i32 or v2i32 (SSE/MMX) instead of letting them be
any random type. This ensures they get trivially CSE'd on the dag.
This fix is also important for LegalizeDAGTypes, as it gets unhappy
when the x86 backend wants BUILD_VECTOR(i64 0) to be legal even when
'i64' isn't legal.
This patch makes the following changes:
1) X86TargetLowering::LowerBUILD_VECTOR now lowers 0/1 vectors into
their canonical types.
2) The now-dead patterns are removed from the SSE/MMX .td files.
3) All the patterns in the .td file that referred to immAllOnesV or
immAllZerosV in the wrong form now use *_bc to match them with a
bitcast wrapped around them.
4) X86DAGToDAGISel::SelectScalarSSELoad is generalized to handle
bitcast'd zero vectors, which simplifies the code actually.
5) getShuffleVectorZeroOrUndef is updated to generate a shuffle that
is legal, instead of generating one that is illegal and expecting
a later legalize pass to clean it up.
6) isZeroShuffle is generalized to handle bitcast of zeros.
7) several other minor tweaks.
This patch is definite goodness, but has the potential to cause random
code quality regressions. Please be on the lookout for these and let
me know if they happen.
llvm-svn: 44310
2007-11-25 08:24:49 +08:00
|
|
|
[(set VR128:$dst, (v4i32 immAllOnesV))]>;
|
2006-03-27 15:00:16 +08:00
|
|
|
|
2007-05-03 07:11:52 +08:00
|
|
|
// FR64 to 128-bit vector conversion.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movsd\t{$src, $dst|$dst, $src}",
|
2006-04-04 04:53:28 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (scalar_to_vector FR64:$src)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movsd\t{$src, $dst|$dst, $src}",
|
2006-04-04 04:53:28 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movd\t{$src, $dst|$dst, $src}",
|
2006-04-04 04:53:28 +08:00
|
|
|
[(set VR128:$dst,
|
2006-05-16 15:21:53 +08:00
|
|
|
(v4i32 (scalar_to_vector GR32:$src)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movd\t{$src, $dst|$dst, $src}",
|
2006-04-04 04:53:28 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
|
2006-11-17 07:33:25 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movd\t{$src, $dst|$dst, $src}",
|
2006-12-06 02:45:06 +08:00
|
|
|
[(set FR32:$dst, (bitconvert GR32:$src))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movd\t{$src, $dst|$dst, $src}",
|
2006-12-15 03:43:11 +08:00
|
|
|
[(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
|
2006-12-06 02:45:06 +08:00
|
|
|
|
2006-04-04 04:53:28 +08:00
|
|
|
// SSE2 instructions with XS prefix
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movq\t{$src, $dst|$dst, $src}",
|
2006-04-04 04:53:28 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
|
|
|
|
Requires<[HasSSE2]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movq\t{$src, $dst|$dst, $src}",
|
2006-11-17 07:33:25 +08:00
|
|
|
[(store (i64 (vector_extract (v2i64 VR128:$src),
|
|
|
|
(iPTR 0))), addr:$dst)]>;
|
|
|
|
|
2006-04-04 04:53:28 +08:00
|
|
|
// FIXME: may not be able to eliminate this movss with coalescing the src and
|
|
|
|
// dest register classes are different. We really want to write this pattern
|
|
|
|
// like this:
|
2006-06-15 16:14:54 +08:00
|
|
|
// def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
|
2006-04-04 04:53:28 +08:00
|
|
|
// (f32 FR32:$src)>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movsd\t{$src, $dst|$dst, $src}",
|
2006-04-04 04:53:28 +08:00
|
|
|
[(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
|
2006-06-15 16:14:54 +08:00
|
|
|
(iPTR 0)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movsd\t{$src, $dst|$dst, $src}",
|
2006-04-19 05:29:08 +08:00
|
|
|
[(store (f64 (vector_extract (v2f64 VR128:$src),
|
2006-06-15 16:14:54 +08:00
|
|
|
(iPTR 0))), addr:$dst)]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movd\t{$src, $dst|$dst, $src}",
|
2006-05-16 15:21:53 +08:00
|
|
|
[(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
|
2006-06-15 16:14:54 +08:00
|
|
|
(iPTR 0)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movd\t{$src, $dst|$dst, $src}",
|
2006-04-04 04:53:28 +08:00
|
|
|
[(store (i32 (vector_extract (v4i32 VR128:$src),
|
2006-06-15 16:14:54 +08:00
|
|
|
(iPTR 0))), addr:$dst)]>;
|
2006-04-04 04:53:28 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movd\t{$src, $dst|$dst, $src}",
|
2006-12-15 03:43:11 +08:00
|
|
|
[(set GR32:$dst, (bitconvert FR32:$src))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movd\t{$src, $dst|$dst, $src}",
|
2006-12-15 03:43:11 +08:00
|
|
|
[(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
|
2006-12-06 02:45:06 +08:00
|
|
|
|
|
|
|
|
2006-04-04 04:53:28 +08:00
|
|
|
// Move to lower bits of a VR128, leaving upper bits alone.
|
2006-03-25 07:15:12 +08:00
|
|
|
// Three operand (but two address) aliases.
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2008-01-11 14:59:07 +08:00
|
|
|
let neverHasSideEffects = 1 in
|
2007-05-03 07:11:52 +08:00
|
|
|
def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movsd\t{$src2, $dst|$dst, $src2}", []>;
|
2006-04-11 08:19:04 +08:00
|
|
|
|
2007-05-03 07:11:52 +08:00
|
|
|
let AddedComplexity = 15 in
|
|
|
|
def MOVLPDrr : SDI<0x10, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movsd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
MOVL_shuffle_mask)))]>;
|
2006-04-20 05:15:24 +08:00
|
|
|
}
|
2006-03-21 15:09:35 +08:00
|
|
|
|
2006-04-12 06:28:25 +08:00
|
|
|
// Store / copy lower 64-bits of a XMM register.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movq\t{$src, $dst|$dst, $src}",
|
2006-04-12 06:28:25 +08:00
|
|
|
[(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
|
|
|
|
|
2006-04-04 04:53:28 +08:00
|
|
|
// Move to lower bits of a VR128 and zeroing upper bits.
|
2006-03-25 07:15:12 +08:00
|
|
|
// Loading from memory automatically zeroing upper bits.
|
2008-05-10 08:59:18 +08:00
|
|
|
let AddedComplexity = 20 in {
|
|
|
|
def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
|
|
|
"movsd\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (X86vzmovl (v2f64 (scalar_to_vector
|
|
|
|
(loadf64 addr:$src))))))]>;
|
2008-05-08 08:57:18 +08:00
|
|
|
|
2008-05-21 02:24:47 +08:00
|
|
|
def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
|
|
|
|
(MOVZSD2PDrm addr:$src)>;
|
|
|
|
def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
|
2008-05-10 08:59:18 +08:00
|
|
|
(MOVZSD2PDrm addr:$src)>;
|
2008-05-10 05:53:03 +08:00
|
|
|
def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
|
2008-05-10 08:59:18 +08:00
|
|
|
}
|
2007-05-03 07:11:52 +08:00
|
|
|
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
llvm-svn: 27923
2006-04-21 09:05:10 +08:00
|
|
|
// movd / movq to XMM register zero-extends
|
2007-12-15 11:00:47 +08:00
|
|
|
let AddedComplexity = 15 in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movd\t{$src, $dst|$dst, $src}",
|
2008-05-10 05:53:03 +08:00
|
|
|
[(set VR128:$dst, (v4i32 (X86vzmovl
|
2008-05-08 08:57:18 +08:00
|
|
|
(v4i32 (scalar_to_vector GR32:$src)))))]>;
|
2007-12-15 11:00:47 +08:00
|
|
|
// This is X86-64 only.
|
|
|
|
def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
|
|
|
|
"mov{d|q}\t{$src, $dst|$dst, $src}",
|
2008-05-10 05:53:03 +08:00
|
|
|
[(set VR128:$dst, (v2i64 (X86vzmovl
|
2008-05-08 08:57:18 +08:00
|
|
|
(v2i64 (scalar_to_vector GR64:$src)))))]>;
|
2007-12-15 11:00:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
let AddedComplexity = 20 in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movd\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
2008-05-10 05:53:03 +08:00
|
|
|
(v4i32 (X86vzmovl (v4i32 (scalar_to_vector
|
2008-05-08 08:57:18 +08:00
|
|
|
(loadi32 addr:$src))))))]>;
|
2008-05-23 02:56:56 +08:00
|
|
|
|
|
|
|
def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
|
|
|
|
(MOVZDI2PDIrm addr:$src)>;
|
|
|
|
def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
|
|
|
|
(MOVZDI2PDIrm addr:$src)>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movq\t{$src, $dst|$dst, $src}",
|
2007-12-15 11:00:47 +08:00
|
|
|
[(set VR128:$dst,
|
2008-05-10 05:53:03 +08:00
|
|
|
(v2i64 (X86vzmovl (v2i64 (scalar_to_vector
|
2008-05-08 08:57:18 +08:00
|
|
|
(loadi64 addr:$src))))))]>, XS,
|
2007-12-15 11:00:47 +08:00
|
|
|
Requires<[HasSSE2]>;
|
2006-03-22 07:01:21 +08:00
|
|
|
|
2008-05-23 02:56:56 +08:00
|
|
|
def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
|
|
|
|
(MOVZQI2PQIrm addr:$src)>;
|
|
|
|
def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
|
|
|
|
(MOVZQI2PQIrm addr:$src)>;
|
2008-05-10 05:53:03 +08:00
|
|
|
def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
|
2008-05-10 08:59:18 +08:00
|
|
|
}
|
2008-05-10 05:53:03 +08:00
|
|
|
|
2007-12-15 11:00:47 +08:00
|
|
|
// Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
|
|
|
|
// IA32 document. movq xmm1, xmm2 does clear the high bits.
|
|
|
|
let AddedComplexity = 15 in
|
|
|
|
def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
|
|
"movq\t{$src, $dst|$dst, $src}",
|
2008-05-10 05:53:03 +08:00
|
|
|
[(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
|
2007-12-15 11:00:47 +08:00
|
|
|
XS, Requires<[HasSSE2]>;
|
|
|
|
|
2008-05-21 02:24:47 +08:00
|
|
|
let AddedComplexity = 20 in {
|
2007-12-15 11:00:47 +08:00
|
|
|
def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
|
|
|
"movq\t{$src, $dst|$dst, $src}",
|
2008-05-10 05:53:03 +08:00
|
|
|
[(set VR128:$dst, (v2i64 (X86vzmovl
|
2008-05-21 02:24:47 +08:00
|
|
|
(loadv2i64 addr:$src))))]>,
|
2007-12-15 11:00:47 +08:00
|
|
|
XS, Requires<[HasSSE2]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2008-05-21 02:24:47 +08:00
|
|
|
def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
|
|
|
|
(MOVZPQILo2PQIrm addr:$src)>;
|
|
|
|
}
|
|
|
|
|
2007-05-03 07:11:52 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SSE3 Instructions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
// Move Instructions
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movshdup\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v4f32 (vector_shuffle
|
|
|
|
VR128:$src, (undef),
|
|
|
|
MOVSHDUP_shuffle_mask)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movshdup\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v4f32 (vector_shuffle
|
2007-07-19 04:23:34 +08:00
|
|
|
(memopv4f32 addr:$src), (undef),
|
2007-05-03 07:11:52 +08:00
|
|
|
MOVSHDUP_shuffle_mask)))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movsldup\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v4f32 (vector_shuffle
|
|
|
|
VR128:$src, (undef),
|
|
|
|
MOVSLDUP_shuffle_mask)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movsldup\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v4f32 (vector_shuffle
|
2007-07-19 04:23:34 +08:00
|
|
|
(memopv4f32 addr:$src), (undef),
|
2007-05-03 07:11:52 +08:00
|
|
|
MOVSLDUP_shuffle_mask)))]>;
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movddup\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v2f64 (vector_shuffle
|
|
|
|
VR128:$src, (undef),
|
|
|
|
SSE_splat_lo_mask)))]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movddup\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2f64 (vector_shuffle
|
|
|
|
(scalar_to_vector (loadf64 addr:$src)),
|
|
|
|
(undef),
|
|
|
|
SSE_splat_lo_mask)))]>;
|
|
|
|
|
|
|
|
// Arithmetic
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"addsubps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
|
|
|
|
VR128:$src2))]>;
|
|
|
|
def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"addsubps\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src2)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"addsubpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
|
|
|
|
VR128:$src2))]>;
|
|
|
|
def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
"addsubpd\t{$src2, $dst|$dst, $src2}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src2)))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"lddqu\t{$src, $dst|$dst, $src}",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
|
|
|
|
|
|
|
|
// Horizontal ops
|
|
|
|
class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
|
|
|
|
class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
2008-05-23 08:37:07 +08:00
|
|
|
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
2007-05-03 07:11:52 +08:00
|
|
|
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
|
|
|
|
class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
2007-08-01 04:11:57 +08:00
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
2008-05-23 08:37:07 +08:00
|
|
|
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-05-03 07:11:52 +08:00
|
|
|
def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
|
|
|
|
def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
|
|
|
|
def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
|
|
|
|
def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
|
|
|
|
def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
|
|
|
|
def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
|
|
|
|
def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
|
|
|
|
def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Thread synchronization
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
|
2007-05-03 07:11:52 +08:00
|
|
|
[(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
|
|
|
|
|
|
|
|
// vector_shuffle v1, <undef> <1, 1, 3, 3>
|
|
|
|
let AddedComplexity = 15 in
|
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
|
|
|
MOVSHDUP_shuffle_mask)),
|
|
|
|
(MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
|
|
|
|
let AddedComplexity = 20 in
|
2007-07-19 04:23:34 +08:00
|
|
|
def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
|
2007-05-03 07:11:52 +08:00
|
|
|
MOVSHDUP_shuffle_mask)),
|
|
|
|
(MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
|
|
|
|
|
|
|
// vector_shuffle v1, <undef> <0, 0, 2, 2>
|
|
|
|
let AddedComplexity = 15 in
|
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
|
|
|
MOVSLDUP_shuffle_mask)),
|
|
|
|
(MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
|
|
|
|
let AddedComplexity = 20 in
|
2007-07-19 04:23:34 +08:00
|
|
|
def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
|
2007-05-03 07:11:52 +08:00
|
|
|
MOVSLDUP_shuffle_mask)),
|
|
|
|
(MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SSSE3 Instructions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2007-08-10 14:22:27 +08:00
|
|
|
/// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
|
2008-02-10 07:46:37 +08:00
|
|
|
multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
|
|
|
|
Intrinsic IntId64, Intrinsic IntId128> {
|
|
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR64:$dst, (IntId64 VR64:$src))]>;
|
|
|
|
|
|
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR64:$dst,
|
|
|
|
(IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
|
|
|
|
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst, (IntId128 VR128:$src))]>,
|
|
|
|
OpSize;
|
2007-08-10 14:22:27 +08:00
|
|
|
|
2008-02-10 07:46:37 +08:00
|
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins i128mem:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId128
|
|
|
|
(bitconvert (memopv16i8 addr:$src))))]>, OpSize;
|
2007-08-10 14:22:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
|
2008-02-10 07:46:37 +08:00
|
|
|
multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
|
|
|
|
Intrinsic IntId64, Intrinsic IntId128> {
|
|
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
|
|
|
(ins VR64:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR64:$dst, (IntId64 VR64:$src))]>;
|
|
|
|
|
|
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
|
|
|
(ins i64mem:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR64:$dst,
|
|
|
|
(IntId64
|
|
|
|
(bitconvert (memopv4i16 addr:$src))))]>;
|
|
|
|
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst, (IntId128 VR128:$src))]>,
|
|
|
|
OpSize;
|
2007-08-10 14:22:27 +08:00
|
|
|
|
2008-02-10 07:46:37 +08:00
|
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins i128mem:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId128
|
|
|
|
(bitconvert (memopv8i16 addr:$src))))]>, OpSize;
|
2007-08-10 14:22:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
|
2008-02-10 07:46:37 +08:00
|
|
|
multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
|
|
|
|
Intrinsic IntId64, Intrinsic IntId128> {
|
|
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
|
|
|
(ins VR64:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR64:$dst, (IntId64 VR64:$src))]>;
|
|
|
|
|
|
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
|
|
|
(ins i64mem:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR64:$dst,
|
|
|
|
(IntId64
|
|
|
|
(bitconvert (memopv2i32 addr:$src))))]>;
|
|
|
|
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst, (IntId128 VR128:$src))]>,
|
|
|
|
OpSize;
|
2007-08-10 14:22:27 +08:00
|
|
|
|
2008-02-10 07:46:37 +08:00
|
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins i128mem:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId128
|
|
|
|
(bitconvert (memopv4i32 addr:$src))))]>, OpSize;
|
2007-05-03 07:11:52 +08:00
|
|
|
}
|
|
|
|
|
2007-08-10 14:22:27 +08:00
|
|
|
defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
|
|
|
|
int_x86_ssse3_pabs_b,
|
|
|
|
int_x86_ssse3_pabs_b_128>;
|
|
|
|
defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
|
|
|
|
int_x86_ssse3_pabs_w,
|
|
|
|
int_x86_ssse3_pabs_w_128>;
|
|
|
|
defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
|
|
|
|
int_x86_ssse3_pabs_d,
|
|
|
|
int_x86_ssse3_pabs_d_128>;
|
|
|
|
|
|
|
|
/// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-08-10 14:22:27 +08:00
|
|
|
multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
|
|
|
|
Intrinsic IntId64, Intrinsic IntId128,
|
|
|
|
bit Commutable = 0> {
|
|
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
|
|
|
(ins VR64:$src1, VR64:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
|
|
|
(ins VR64:$src1, i64mem:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR64:$dst,
|
|
|
|
(IntId64 VR64:$src1,
|
|
|
|
(bitconvert (memopv8i8 addr:$src2))))]>;
|
|
|
|
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
|
|
OpSize {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId128 VR128:$src1,
|
|
|
|
(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-08-10 14:22:27 +08:00
|
|
|
multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
|
|
|
|
Intrinsic IntId64, Intrinsic IntId128,
|
|
|
|
bit Commutable = 0> {
|
|
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
|
|
|
(ins VR64:$src1, VR64:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
|
|
|
(ins VR64:$src1, i64mem:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR64:$dst,
|
|
|
|
(IntId64 VR64:$src1,
|
|
|
|
(bitconvert (memopv4i16 addr:$src2))))]>;
|
|
|
|
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
|
|
OpSize {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId128 VR128:$src1,
|
|
|
|
(bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-08-10 14:22:27 +08:00
|
|
|
multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
|
|
|
|
Intrinsic IntId64, Intrinsic IntId128,
|
|
|
|
bit Commutable = 0> {
|
|
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
|
|
|
(ins VR64:$src1, VR64:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
|
|
|
(ins VR64:$src1, i64mem:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR64:$dst,
|
|
|
|
(IntId64 VR64:$src1,
|
|
|
|
(bitconvert (memopv2i32 addr:$src2))))]>;
|
|
|
|
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
|
|
OpSize {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId128 VR128:$src1,
|
|
|
|
(bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
|
|
|
|
int_x86_ssse3_phadd_w,
|
|
|
|
int_x86_ssse3_phadd_w_128, 1>;
|
|
|
|
defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
|
|
|
|
int_x86_ssse3_phadd_d,
|
|
|
|
int_x86_ssse3_phadd_d_128, 1>;
|
|
|
|
defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
|
|
|
|
int_x86_ssse3_phadd_sw,
|
|
|
|
int_x86_ssse3_phadd_sw_128, 1>;
|
|
|
|
defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
|
|
|
|
int_x86_ssse3_phsub_w,
|
|
|
|
int_x86_ssse3_phsub_w_128>;
|
|
|
|
defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
|
|
|
|
int_x86_ssse3_phsub_d,
|
|
|
|
int_x86_ssse3_phsub_d_128>;
|
|
|
|
defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
|
|
|
|
int_x86_ssse3_phsub_sw,
|
|
|
|
int_x86_ssse3_phsub_sw_128>;
|
|
|
|
defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
|
|
|
|
int_x86_ssse3_pmadd_ub_sw,
|
|
|
|
int_x86_ssse3_pmadd_ub_sw_128, 1>;
|
|
|
|
defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
|
|
|
|
int_x86_ssse3_pmul_hr_sw,
|
|
|
|
int_x86_ssse3_pmul_hr_sw_128, 1>;
|
|
|
|
defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
|
|
|
|
int_x86_ssse3_pshuf_b,
|
|
|
|
int_x86_ssse3_pshuf_b_128>;
|
|
|
|
defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
|
|
|
|
int_x86_ssse3_psign_b,
|
|
|
|
int_x86_ssse3_psign_b_128>;
|
|
|
|
defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
|
|
|
|
int_x86_ssse3_psign_w,
|
|
|
|
int_x86_ssse3_psign_w_128>;
|
|
|
|
defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
|
|
|
|
int_x86_ssse3_psign_d,
|
|
|
|
int_x86_ssse3_psign_d_128>;
|
|
|
|
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2007-08-10 17:00:17 +08:00
|
|
|
def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
|
|
|
|
(ins VR64:$src1, VR64:$src2, i16imm:$src3),
|
2007-10-12 04:58:37 +08:00
|
|
|
"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
2007-08-10 17:00:17 +08:00
|
|
|
[(set VR64:$dst,
|
|
|
|
(int_x86_ssse3_palign_r
|
|
|
|
VR64:$src1, VR64:$src2,
|
|
|
|
imm:$src3))]>;
|
|
|
|
def PALIGNR64rm : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
|
|
|
|
(ins VR64:$src1, i64mem:$src2, i16imm:$src3),
|
2007-10-12 04:58:37 +08:00
|
|
|
"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
2007-08-10 17:00:17 +08:00
|
|
|
[(set VR64:$dst,
|
|
|
|
(int_x86_ssse3_palign_r
|
|
|
|
VR64:$src1,
|
|
|
|
(bitconvert (memopv2i32 addr:$src2)),
|
|
|
|
imm:$src3))]>;
|
|
|
|
|
|
|
|
def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2, i32imm:$src3),
|
2007-10-12 04:58:37 +08:00
|
|
|
"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
2007-08-10 17:00:17 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(int_x86_ssse3_palign_r_128
|
|
|
|
VR128:$src1, VR128:$src2,
|
|
|
|
imm:$src3))]>, OpSize;
|
|
|
|
def PALIGNR128rm : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, i128mem:$src2, i32imm:$src3),
|
2007-10-12 04:58:37 +08:00
|
|
|
"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
2007-08-10 17:00:17 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(int_x86_ssse3_palign_r_128
|
|
|
|
VR128:$src1,
|
|
|
|
(bitconvert (memopv4i32 addr:$src2)),
|
|
|
|
imm:$src3))]>, OpSize;
|
2007-08-10 14:22:27 +08:00
|
|
|
}
|
2007-05-03 07:11:52 +08:00
|
|
|
|
2006-03-22 07:01:21 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Non-Instruction Patterns
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
llvm-svn: 46307
2008-01-24 16:07:48 +08:00
|
|
|
// extload f32 -> f64. This matches load+fextend because we have a hack in
|
|
|
|
// the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
|
|
|
|
// Since these loads aren't folded into the fextend, we have to match it
|
|
|
|
// explicitly here.
|
|
|
|
let Predicates = [HasSSE2] in
|
|
|
|
def : Pat<(fextend (loadf32 addr:$src)),
|
|
|
|
(CVTSS2SDrm addr:$src)>;
|
|
|
|
|
2006-03-24 10:58:06 +08:00
|
|
|
// bit_convert
|
2006-10-07 12:52:09 +08:00
|
|
|
let Predicates = [HasSSE2] in {
|
|
|
|
def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
|
|
|
|
def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
|
|
|
|
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
|
|
|
|
def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
|
|
|
|
def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
|
|
|
|
def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
|
|
|
|
def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
|
|
|
|
def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
|
|
|
|
def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
|
|
|
|
def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
|
|
|
|
def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
|
|
|
|
def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
|
|
|
|
def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
|
|
|
|
def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
|
|
|
|
def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
|
|
|
|
def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
|
|
|
|
def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
|
|
|
|
def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
|
|
|
|
def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
|
|
|
|
def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
|
|
|
|
def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
|
|
|
|
def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
|
|
|
|
def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
|
|
|
|
def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
|
|
|
|
def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
|
|
|
|
def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
|
|
|
|
def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
|
|
|
|
def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
|
|
|
|
def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
|
|
|
|
def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
|
|
|
|
}
|
2006-03-22 10:53:00 +08:00
|
|
|
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
llvm-svn: 27923
2006-04-21 09:05:10 +08:00
|
|
|
// Move scalar to XMM zero-extended
|
|
|
|
// movd to XMM register zero-extends
|
2006-10-10 05:42:15 +08:00
|
|
|
let AddedComplexity = 15 in {
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
llvm-svn: 27923
2006-04-21 09:05:10 +08:00
|
|
|
// Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
|
2008-05-10 05:53:03 +08:00
|
|
|
def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
|
2006-06-30 02:04:54 +08:00
|
|
|
(MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
|
2008-05-10 05:53:03 +08:00
|
|
|
def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
|
2006-06-30 02:04:54 +08:00
|
|
|
(MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
|
2008-05-10 07:37:55 +08:00
|
|
|
def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
|
|
|
|
(MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
llvm-svn: 27923
2006-04-21 09:05:10 +08:00
|
|
|
}
|
2006-03-25 07:15:12 +08:00
|
|
|
|
2006-03-22 10:53:00 +08:00
|
|
|
// Splat v2f64 / v2i64
|
2006-04-20 05:15:24 +08:00
|
|
|
let AddedComplexity = 10 in {
|
2006-10-28 05:08:32 +08:00
|
|
|
def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
|
2006-06-20 08:25:29 +08:00
|
|
|
(UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
2006-10-28 05:08:32 +08:00
|
|
|
def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
|
|
|
|
(UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
|
2006-06-20 08:25:29 +08:00
|
|
|
(PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
2006-10-28 05:08:32 +08:00
|
|
|
def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
|
|
|
|
(PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
2006-04-20 05:15:24 +08:00
|
|
|
}
|
2006-03-29 11:04:49 +08:00
|
|
|
|
2006-04-19 05:55:35 +08:00
|
|
|
// Special unary SHUFPSrri case.
|
2007-12-15 11:00:47 +08:00
|
|
|
def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
|
|
|
|
SHUFP_unary_shuffle_mask:$sm)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
|
2006-04-11 05:42:19 +08:00
|
|
|
Requires<[HasSSE1]>;
|
2007-08-03 05:17:01 +08:00
|
|
|
// Special unary SHUFPDrri case.
|
2007-12-15 11:00:47 +08:00
|
|
|
def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
|
|
|
|
SHUFP_unary_shuffle_mask:$sm)),
|
2007-08-03 05:17:01 +08:00
|
|
|
(SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
|
|
|
|
Requires<[HasSSE2]>;
|
2006-04-11 06:35:16 +08:00
|
|
|
// Unary v4f32 shuffle with PSHUF* in order to fold a load.
|
2008-04-05 08:30:36 +08:00
|
|
|
def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
|
2006-04-11 06:35:16 +08:00
|
|
|
SHUFP_unary_shuffle_mask:$sm),
|
2006-06-20 08:25:29 +08:00
|
|
|
(PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
|
2006-03-31 03:54:57 +08:00
|
|
|
Requires<[HasSSE2]>;
|
2006-04-11 06:35:16 +08:00
|
|
|
// Special binary v4i32 shuffle cases with SHUFPS.
|
2007-12-15 11:00:47 +08:00
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
|
|
|
|
PSHUFD_binary_shuffle_mask:$sm)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
|
|
|
|
Requires<[HasSSE2]>;
|
2007-12-15 11:00:47 +08:00
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src1,
|
|
|
|
(bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
|
|
|
|
Requires<[HasSSE2]>;
|
2007-12-15 11:00:47 +08:00
|
|
|
// Special binary v2i64 shuffle cases using SHUFPDrri.
|
|
|
|
def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
SHUFP_shuffle_mask:$sm)),
|
|
|
|
(SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
|
|
|
|
Requires<[HasSSE2]>;
|
|
|
|
// Special unary SHUFPDrri case.
|
|
|
|
def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
|
|
|
|
SHUFP_unary_shuffle_mask:$sm)),
|
|
|
|
(SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
|
|
|
|
Requires<[HasSSE2]>;
|
2006-03-30 15:33:32 +08:00
|
|
|
|
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
llvm-svn: 27437
2006-04-05 15:20:06 +08:00
|
|
|
// vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
|
2006-04-20 05:15:24 +08:00
|
|
|
let AddedComplexity = 10 in {
|
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
llvm-svn: 27437
2006-04-05 15:20:06 +08:00
|
|
|
def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
|
|
|
|
UNPCKL_v_undef_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
llvm-svn: 27437
2006-04-05 15:20:06 +08:00
|
|
|
def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
|
|
|
|
UNPCKL_v_undef_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
llvm-svn: 27437
2006-04-05 15:20:06 +08:00
|
|
|
def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
|
|
|
|
UNPCKL_v_undef_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
llvm-svn: 27437
2006-04-05 15:20:06 +08:00
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
|
|
|
UNPCKL_v_undef_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
|
2006-04-20 05:15:24 +08:00
|
|
|
}
|
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
llvm-svn: 27437
2006-04-05 15:20:06 +08:00
|
|
|
|
2007-05-18 02:44:37 +08:00
|
|
|
// vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
|
|
|
|
let AddedComplexity = 10 in {
|
|
|
|
def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
|
|
|
|
UNPCKH_v_undef_shuffle_mask)),
|
|
|
|
(UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
|
|
|
|
UNPCKH_v_undef_shuffle_mask)),
|
|
|
|
(PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
|
|
|
|
UNPCKH_v_undef_shuffle_mask)),
|
|
|
|
(PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
|
|
|
UNPCKH_v_undef_shuffle_mask)),
|
|
|
|
(PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
|
|
|
|
}
|
|
|
|
|
2006-10-10 05:42:15 +08:00
|
|
|
let AddedComplexity = 15 in {
|
2006-04-20 04:37:34 +08:00
|
|
|
// vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
|
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
MOVHP_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVLHPSrr VR128:$src1, VR128:$src2)>;
|
2006-04-20 04:37:34 +08:00
|
|
|
|
|
|
|
// vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
|
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
MOVHLPS_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVHLPSrr VR128:$src1, VR128:$src2)>;
|
2006-05-31 08:51:37 +08:00
|
|
|
|
Fixed a bug which causes x86 be to incorrectly match
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
llvm-svn: 31519
2006-11-08 06:14:24 +08:00
|
|
|
// vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
|
2006-05-31 08:51:37 +08:00
|
|
|
def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
|
Fixed a bug which causes x86 be to incorrectly match
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
llvm-svn: 31519
2006-11-08 06:14:24 +08:00
|
|
|
MOVHLPS_v_undef_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVHLPSrr VR128:$src1, VR128:$src1)>;
|
2006-05-31 08:51:37 +08:00
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
|
Fixed a bug which causes x86 be to incorrectly match
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
llvm-svn: 31519
2006-11-08 06:14:24 +08:00
|
|
|
MOVHLPS_v_undef_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVHLPSrr VR128:$src1, VR128:$src1)>;
|
2006-10-10 05:42:15 +08:00
|
|
|
}
|
2006-04-20 04:37:34 +08:00
|
|
|
|
Fixed a bug which causes x86 be to incorrectly match
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
llvm-svn: 31519
2006-11-08 06:14:24 +08:00
|
|
|
let AddedComplexity = 20 in {
|
2006-04-20 04:37:34 +08:00
|
|
|
// vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
|
|
|
|
// vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
|
2008-05-23 08:37:07 +08:00
|
|
|
def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
|
2006-04-20 02:20:17 +08:00
|
|
|
MOVLP_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
|
2008-05-23 08:37:07 +08:00
|
|
|
def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
|
2006-04-20 02:20:17 +08:00
|
|
|
MOVLP_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
2008-05-23 08:37:07 +08:00
|
|
|
def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
|
2006-04-20 02:20:17 +08:00
|
|
|
MOVHP_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
|
2008-05-23 08:37:07 +08:00
|
|
|
def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
|
2006-04-20 02:20:17 +08:00
|
|
|
MOVHP_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
2006-04-20 02:20:17 +08:00
|
|
|
|
2008-05-24 05:23:16 +08:00
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src1,
|
|
|
|
(bc_v4i32 (memopv2i64 addr:$src2)),
|
2006-04-20 02:20:17 +08:00
|
|
|
MOVLP_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
2008-05-23 08:37:07 +08:00
|
|
|
def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
|
2006-04-25 05:58:20 +08:00
|
|
|
MOVLP_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
2008-05-24 05:23:16 +08:00
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src1,
|
|
|
|
(bc_v4i32 (memopv2i64 addr:$src2)),
|
2006-04-25 05:58:20 +08:00
|
|
|
MOVHP_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
|
2008-05-23 08:37:07 +08:00
|
|
|
def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
|
2008-05-24 02:00:18 +08:00
|
|
|
MOVHP_shuffle_mask)),
|
|
|
|
(MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
2006-10-10 05:42:15 +08:00
|
|
|
}
|
2006-04-25 05:58:20 +08:00
|
|
|
|
2008-05-24 05:23:16 +08:00
|
|
|
// (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
|
|
|
|
// (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
|
|
|
|
def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
|
|
|
|
MOVLP_shuffle_mask)), addr:$src1),
|
|
|
|
(MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
|
|
|
|
def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
|
|
|
|
MOVLP_shuffle_mask)), addr:$src1),
|
|
|
|
(MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
|
|
|
|
MOVHP_shuffle_mask)), addr:$src1),
|
|
|
|
(MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
|
|
|
|
def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
|
|
|
|
MOVHP_shuffle_mask)), addr:$src1),
|
|
|
|
(MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
|
|
|
|
|
|
|
def : Pat<(store (v4i32 (vector_shuffle
|
|
|
|
(bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
|
|
|
|
MOVLP_shuffle_mask)), addr:$src1),
|
|
|
|
(MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
|
|
|
|
def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
|
|
|
|
MOVLP_shuffle_mask)), addr:$src1),
|
|
|
|
(MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(store (v4i32 (vector_shuffle
|
|
|
|
(bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
|
|
|
|
MOVHP_shuffle_mask)), addr:$src1),
|
|
|
|
(MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
|
|
|
|
def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
|
|
|
|
MOVHP_shuffle_mask)), addr:$src1),
|
|
|
|
(MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
|
|
|
|
|
|
|
|
2006-10-10 05:42:15 +08:00
|
|
|
let AddedComplexity = 15 in {
|
2006-04-25 05:58:20 +08:00
|
|
|
// Setting the lowest element in the vector.
|
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
MOVL_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
2006-04-20 02:11:52 +08:00
|
|
|
def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
llvm-svn: 27923
2006-04-21 09:05:10 +08:00
|
|
|
MOVL_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
2006-04-25 07:34:56 +08:00
|
|
|
|
2006-05-04 04:32:03 +08:00
|
|
|
// vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
|
|
|
|
def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
MOVLP_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
2006-05-04 04:32:03 +08:00
|
|
|
def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
|
|
|
MOVLP_shuffle_mask)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
2006-10-10 05:42:15 +08:00
|
|
|
}
|
2006-05-04 04:32:03 +08:00
|
|
|
|
2006-04-25 07:34:56 +08:00
|
|
|
// Set lowest element and zero upper elements.
|
2007-12-15 11:00:47 +08:00
|
|
|
let AddedComplexity = 15 in
|
|
|
|
def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
|
|
|
|
MOVL_shuffle_mask)),
|
|
|
|
(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
|
2008-05-10 05:53:03 +08:00
|
|
|
def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
|
2008-05-09 06:35:02 +08:00
|
|
|
(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
|
2006-04-25 07:34:56 +08:00
|
|
|
|
2006-04-13 05:21:57 +08:00
|
|
|
// Some special case pandn patterns.
|
|
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
|
|
|
|
VR128:$src2)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
2006-04-13 05:21:57 +08:00
|
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
|
|
|
|
VR128:$src2)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
2006-04-13 05:21:57 +08:00
|
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
|
|
|
|
VR128:$src2)),
|
2006-06-20 08:25:29 +08:00
|
|
|
(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
2006-04-13 05:21:57 +08:00
|
|
|
|
|
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src2))),
|
2006-06-20 08:25:29 +08:00
|
|
|
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
2006-04-13 05:21:57 +08:00
|
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src2))),
|
2006-06-20 08:25:29 +08:00
|
|
|
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
2006-04-13 05:21:57 +08:00
|
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
|
2008-05-23 08:37:07 +08:00
|
|
|
(memop addr:$src2))),
|
2006-06-20 08:25:29 +08:00
|
|
|
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
llvm-svn: 29042
2006-07-07 16:33:52 +08:00
|
|
|
|
2007-11-17 11:58:34 +08:00
|
|
|
// vector -> vector casts
|
|
|
|
def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
|
|
|
|
(Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
|
|
|
|
(Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
|
2007-07-20 08:27:43 +08:00
|
|
|
// Use movaps / movups for SSE integer load / store (one byte shorter).
|
2007-07-28 01:16:43 +08:00
|
|
|
def : Pat<(alignedloadv4i32 addr:$src),
|
|
|
|
(MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
|
|
|
|
def : Pat<(loadv4i32 addr:$src),
|
|
|
|
(MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
|
2007-07-20 08:27:43 +08:00
|
|
|
def : Pat<(alignedloadv2i64 addr:$src),
|
|
|
|
(MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(loadv2i64 addr:$src),
|
|
|
|
(MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
|
|
|
|
|
|
|
|
def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
|
|
|
|
(MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
|
|
|
|
(MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
|
|
|
|
(MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
|
|
|
|
(MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(store (v2i64 VR128:$src), addr:$dst),
|
|
|
|
(MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(store (v4i32 VR128:$src), addr:$dst),
|
|
|
|
(MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(store (v8i16 VR128:$src), addr:$dst),
|
|
|
|
(MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(store (v16i8 VR128:$src), addr:$dst),
|
|
|
|
(MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
|
2008-02-03 15:18:54 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SSE4.1 Instructions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
|
|
|
|
bits<8> opcsd, bits<8> opcpd,
|
|
|
|
string OpcodeStr,
|
|
|
|
Intrinsic F32Int,
|
|
|
|
Intrinsic V4F32Int,
|
|
|
|
Intrinsic F64Int,
|
2008-02-04 13:34:34 +08:00
|
|
|
Intrinsic V2F64Int> {
|
2008-02-03 15:18:54 +08:00
|
|
|
// Intrinsic operation, reg.
|
2008-03-14 15:39:27 +08:00
|
|
|
def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
|
2008-02-04 14:00:24 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
2008-02-03 15:18:54 +08:00
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
2008-02-04 13:34:34 +08:00
|
|
|
[(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
|
|
|
|
OpSize;
|
2008-02-03 15:18:54 +08:00
|
|
|
|
|
|
|
// Intrinsic operation, mem.
|
2008-03-14 15:39:27 +08:00
|
|
|
def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
|
2008-02-04 14:00:24 +08:00
|
|
|
(outs VR128:$dst), (ins ssmem:$src1, i32i8imm:$src2),
|
2008-02-03 15:18:54 +08:00
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
2008-02-04 13:34:34 +08:00
|
|
|
[(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
|
|
|
|
OpSize;
|
2008-02-03 15:18:54 +08:00
|
|
|
|
|
|
|
// Vector intrinsic operation, reg
|
2008-03-14 15:39:27 +08:00
|
|
|
def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
|
2008-02-04 14:00:24 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
2008-02-03 15:18:54 +08:00
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
2008-02-04 13:34:34 +08:00
|
|
|
[(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
|
|
|
|
OpSize;
|
2008-02-03 15:18:54 +08:00
|
|
|
|
|
|
|
// Vector intrinsic operation, mem
|
2008-03-14 15:39:27 +08:00
|
|
|
def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
|
2008-02-04 14:00:24 +08:00
|
|
|
(outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
|
2008-02-03 15:18:54 +08:00
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
2008-05-23 08:37:07 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
|
2008-02-04 13:34:34 +08:00
|
|
|
OpSize;
|
2008-02-03 15:18:54 +08:00
|
|
|
|
|
|
|
// Intrinsic operation, reg.
|
2008-03-14 15:39:27 +08:00
|
|
|
def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
|
2008-02-04 14:00:24 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
2008-02-03 15:18:54 +08:00
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
2008-02-04 13:34:34 +08:00
|
|
|
[(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
|
|
|
|
OpSize;
|
2008-02-03 15:18:54 +08:00
|
|
|
|
|
|
|
// Intrinsic operation, mem.
|
2008-03-14 15:39:27 +08:00
|
|
|
def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
|
2008-02-04 14:00:24 +08:00
|
|
|
(outs VR128:$dst), (ins sdmem:$src1, i32i8imm:$src2),
|
2008-02-03 15:18:54 +08:00
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
2008-02-04 13:34:34 +08:00
|
|
|
[(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
|
|
|
|
OpSize;
|
2008-02-03 15:18:54 +08:00
|
|
|
|
|
|
|
// Vector intrinsic operation, reg
|
2008-03-14 15:39:27 +08:00
|
|
|
def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
|
2008-02-04 14:00:24 +08:00
|
|
|
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
2008-02-03 15:18:54 +08:00
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
2008-02-04 13:34:34 +08:00
|
|
|
[(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
|
|
|
|
OpSize;
|
2008-02-03 15:18:54 +08:00
|
|
|
|
|
|
|
// Vector intrinsic operation, mem
|
2008-03-14 15:39:27 +08:00
|
|
|
def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
|
2008-02-04 14:00:24 +08:00
|
|
|
(outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
|
2008-02-03 15:18:54 +08:00
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
2008-05-23 08:37:07 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
|
2008-02-04 13:34:34 +08:00
|
|
|
OpSize;
|
2008-02-03 15:18:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// FP round - roundss, roundps, roundsd, roundpd
|
|
|
|
defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
|
|
|
|
int_x86_sse41_round_ss, int_x86_sse41_round_ps,
|
|
|
|
int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
|
2008-02-04 13:34:34 +08:00
|
|
|
|
|
|
|
// SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
|
|
|
|
multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
|
|
|
|
Intrinsic IntId128> {
|
|
|
|
def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
|
|
|
|
def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins i128mem:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId128
|
|
|
|
(bitconvert (memopv8i16 addr:$src))))]>, OpSize;
|
|
|
|
}
|
|
|
|
|
|
|
|
defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
|
|
|
|
int_x86_sse41_phminposuw>;
|
|
|
|
|
|
|
|
/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2008-02-04 13:34:34 +08:00
|
|
|
multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
|
|
|
|
Intrinsic IntId128, bit Commutable = 0> {
|
2008-02-10 07:46:37 +08:00
|
|
|
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
|
|
OpSize {
|
2008-02-04 13:34:34 +08:00
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
2008-02-10 07:46:37 +08:00
|
|
|
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId128 VR128:$src1,
|
|
|
|
(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
|
2008-02-04 13:34:34 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
|
|
|
|
int_x86_sse41_pcmpeqq, 1>;
|
|
|
|
defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
|
|
|
|
int_x86_sse41_packusdw, 0>;
|
|
|
|
defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
|
|
|
|
int_x86_sse41_pminsb, 1>;
|
|
|
|
defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
|
|
|
|
int_x86_sse41_pminsd, 1>;
|
|
|
|
defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
|
|
|
|
int_x86_sse41_pminud, 1>;
|
|
|
|
defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
|
|
|
|
int_x86_sse41_pminuw, 1>;
|
|
|
|
defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
|
|
|
|
int_x86_sse41_pmaxsb, 1>;
|
|
|
|
defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
|
|
|
|
int_x86_sse41_pmaxsd, 1>;
|
|
|
|
defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
|
|
|
|
int_x86_sse41_pmaxud, 1>;
|
|
|
|
defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
|
|
|
|
int_x86_sse41_pmaxuw, 1>;
|
2008-02-04 14:00:24 +08:00
|
|
|
|
2008-02-09 09:38:08 +08:00
|
|
|
|
|
|
|
/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2008-05-24 01:49:40 +08:00
|
|
|
multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
|
|
|
|
SDNode OpNode, Intrinsic IntId128,
|
|
|
|
bit Commutable = 0> {
|
2008-02-09 09:38:08 +08:00
|
|
|
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
2008-05-24 01:49:40 +08:00
|
|
|
[(set VR128:$dst, (OpNode (OpVT VR128:$src1),
|
|
|
|
VR128:$src2))]>, OpSize {
|
2008-02-09 09:38:08 +08:00
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
|
|
OpSize {
|
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
|
|
|
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst,
|
2008-05-23 08:37:07 +08:00
|
|
|
(OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
|
2008-02-09 09:38:08 +08:00
|
|
|
def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
|
|
[(set VR128:$dst,
|
2008-05-23 08:37:07 +08:00
|
|
|
(IntId128 VR128:$src1, (memop addr:$src2)))]>,
|
2008-02-09 09:38:08 +08:00
|
|
|
OpSize;
|
|
|
|
}
|
|
|
|
}
|
2008-05-24 01:49:40 +08:00
|
|
|
defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
|
2008-02-09 09:38:08 +08:00
|
|
|
int_x86_sse41_pmulld, 1>;
|
2008-05-24 01:49:40 +08:00
|
|
|
defm PMULDQ : SS41I_binop_patint<0x28, "pmuldq", v2i64, mul,
|
|
|
|
int_x86_sse41_pmuldq, 1>;
|
2008-02-09 09:38:08 +08:00
|
|
|
|
|
|
|
|
2008-03-14 15:39:27 +08:00
|
|
|
/// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
|
2008-03-05 16:19:16 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2008-02-04 14:00:24 +08:00
|
|
|
multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
|
|
|
|
Intrinsic IntId128, bit Commutable = 0> {
|
2008-03-14 15:39:27 +08:00
|
|
|
def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
|
2008-02-10 07:46:37 +08:00
|
|
|
(ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
|
|
|
|
!strconcat(OpcodeStr,
|
2008-02-11 02:47:57 +08:00
|
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
2008-02-10 07:46:37 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
|
|
|
|
OpSize {
|
2008-02-04 14:00:24 +08:00
|
|
|
let isCommutable = Commutable;
|
|
|
|
}
|
2008-03-14 15:39:27 +08:00
|
|
|
def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
|
2008-02-10 07:46:37 +08:00
|
|
|
(ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
|
|
|
|
!strconcat(OpcodeStr,
|
2008-02-11 02:47:57 +08:00
|
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
2008-02-10 07:46:37 +08:00
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId128 VR128:$src1,
|
|
|
|
(bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
|
|
|
|
OpSize;
|
2008-02-04 14:00:24 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
|
|
|
|
int_x86_sse41_blendps, 0>;
|
|
|
|
defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
|
|
|
|
int_x86_sse41_blendpd, 0>;
|
|
|
|
defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
|
|
|
|
int_x86_sse41_pblendw, 0>;
|
|
|
|
defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
|
|
|
|
int_x86_sse41_dpps, 1>;
|
|
|
|
defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
|
|
|
|
int_x86_sse41_dppd, 1>;
|
|
|
|
defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
|
|
|
|
int_x86_sse41_mpsadbw, 0>;
|
2008-02-09 09:38:08 +08:00
|
|
|
|
2008-02-10 07:46:37 +08:00
|
|
|
|
2008-03-14 15:39:27 +08:00
|
|
|
/// SS41I_ternary_int - SSE 4.1 ternary operator
|
2008-03-05 16:19:16 +08:00
|
|
|
let Uses = [XMM0], Constraints = "$src1 = $dst" in {
|
2008-02-11 02:47:57 +08:00
|
|
|
multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
|
|
|
|
def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, VR128:$src2),
|
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
|
|
|
|
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
|
|
|
|
OpSize;
|
|
|
|
|
|
|
|
def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId VR128:$src1,
|
|
|
|
(bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
|
|
|
|
defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
|
|
|
|
defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
|
|
|
|
|
|
|
|
|
2008-02-10 07:46:37 +08:00
|
|
|
multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
|
|
|
|
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
|
|
|
|
|
|
|
|
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
|
|
|
|
}
|
|
|
|
|
|
|
|
defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
|
|
|
|
defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
|
|
|
|
defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
|
|
|
|
defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
|
|
|
|
defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
|
|
|
|
defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
|
|
|
|
|
|
|
|
multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
|
|
|
|
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
|
|
|
|
|
|
|
|
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
|
|
|
|
}
|
|
|
|
|
|
|
|
defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
|
|
|
|
defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
|
|
|
|
defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
|
|
|
|
defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
|
|
|
|
|
|
|
|
multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
|
|
|
|
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
|
|
|
|
|
|
|
|
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
|
|
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
|
|
|
|
}
|
|
|
|
|
|
|
|
defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
|
|
|
|
defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
|
|
|
|
|
|
|
|
|
2008-02-11 12:19:36 +08:00
|
|
|
/// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
|
|
|
|
multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
|
2008-03-26 16:11:49 +08:00
|
|
|
def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
|
2008-02-10 07:46:37 +08:00
|
|
|
(ins VR128:$src1, i32i8imm:$src2),
|
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
2008-02-11 12:19:36 +08:00
|
|
|
[(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
|
|
|
|
OpSize;
|
2008-03-14 15:39:27 +08:00
|
|
|
def mr : SS4AIi8<opc, MRMDestMem, (outs),
|
2008-02-10 07:46:37 +08:00
|
|
|
(ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
|
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
2008-02-11 12:19:36 +08:00
|
|
|
[]>, OpSize;
|
|
|
|
// FIXME:
|
|
|
|
// There's an AssertZext in the way of writing the store pattern
|
|
|
|
// (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
|
|
|
|
}
|
|
|
|
|
|
|
|
defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
|
|
|
|
|
|
|
|
|
|
|
|
/// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
|
|
|
|
multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
|
2008-03-14 15:39:27 +08:00
|
|
|
def mr : SS4AIi8<opc, MRMDestMem, (outs),
|
2008-02-11 12:19:36 +08:00
|
|
|
(ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
|
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
|
|
[]>, OpSize;
|
|
|
|
// FIXME:
|
|
|
|
// There's an AssertZext in the way of writing the store pattern
|
|
|
|
// (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
|
2008-02-10 07:46:37 +08:00
|
|
|
}
|
|
|
|
|
2008-02-11 12:19:36 +08:00
|
|
|
defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
|
2008-02-10 07:46:37 +08:00
|
|
|
|
2008-02-11 12:19:36 +08:00
|
|
|
|
|
|
|
/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
|
|
|
|
multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
|
2008-03-26 16:11:49 +08:00
|
|
|
def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
|
2008-02-10 07:46:37 +08:00
|
|
|
(ins VR128:$src1, i32i8imm:$src2),
|
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
|
|
[(set GR32:$dst,
|
|
|
|
(extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
|
2008-03-14 15:39:27 +08:00
|
|
|
def mr : SS4AIi8<opc, MRMDestMem, (outs),
|
2008-02-10 07:46:37 +08:00
|
|
|
(ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
|
|
|
|
!strconcat(OpcodeStr,
|
|
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
|
|
[(store (extractelt (v4i32 VR128:$src1), imm:$src2),
|
|
|
|
addr:$dst)]>, OpSize;
|
2008-02-09 09:38:08 +08:00
|
|
|
}
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2008-02-11 12:19:36 +08:00
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defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
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2008-02-09 09:38:08 +08:00
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2008-03-25 05:52:23 +08:00
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/// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
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/// destination
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2008-02-11 12:19:36 +08:00
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multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
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2008-03-26 16:11:49 +08:00
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def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
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2008-02-10 07:46:37 +08:00
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(ins VR128:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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2008-04-16 10:32:24 +08:00
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[(set GR32:$dst,
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(extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
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2008-03-25 05:52:23 +08:00
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OpSize;
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2008-03-14 15:39:27 +08:00
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def mr : SS4AIi8<opc, MRMDestMem, (outs),
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2008-02-10 07:46:37 +08:00
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(ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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2008-03-25 05:52:23 +08:00
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[(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
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2008-02-10 07:46:37 +08:00
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addr:$dst)]>, OpSize;
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2008-02-09 09:38:08 +08:00
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}
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2008-02-11 12:19:36 +08:00
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defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
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2008-03-05 16:19:16 +08:00
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let Constraints = "$src1 = $dst" in {
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2008-02-11 12:19:36 +08:00
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multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
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2008-03-14 15:39:27 +08:00
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def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
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2008-02-11 12:19:36 +08:00
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(ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
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2008-03-14 15:39:27 +08:00
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def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
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2008-02-11 12:19:36 +08:00
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(ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
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imm:$src3))]>, OpSize;
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}
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}
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defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
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2008-03-05 16:19:16 +08:00
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let Constraints = "$src1 = $dst" in {
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2008-02-11 12:19:36 +08:00
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multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
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2008-03-14 15:39:27 +08:00
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def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
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2008-02-11 12:19:36 +08:00
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(ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
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OpSize;
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2008-03-14 15:39:27 +08:00
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def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
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2008-02-11 12:19:36 +08:00
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(ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
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imm:$src3)))]>, OpSize;
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}
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}
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defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
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2008-03-05 16:19:16 +08:00
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let Constraints = "$src1 = $dst" in {
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2008-02-11 12:19:36 +08:00
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multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
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2008-03-14 15:39:27 +08:00
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def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
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2008-02-11 12:19:36 +08:00
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(ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
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2008-03-14 15:39:27 +08:00
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def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
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2008-02-11 12:19:36 +08:00
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(ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(X86insrtps VR128:$src1, (loadf32 addr:$src2),
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imm:$src3))]>, OpSize;
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}
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}
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2008-02-10 07:46:37 +08:00
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2008-03-26 16:11:49 +08:00
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defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
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2008-03-17 05:14:46 +08:00
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let Defs = [EFLAGS] in {
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def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
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"ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
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def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
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"ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
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}
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def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"movntdqa\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
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