2017-02-23 06:32:51 +08:00
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//===- ScoreboardHazardRecognizer.cpp - Scheduler Support -----------------===//
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2009-08-10 23:55:25 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2010-12-09 04:04:29 +08:00
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// This file implements the ScoreboardHazardRecognizer class, which
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// encapsultes hazard-avoidance heuristics for scheduling, based on the
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// scheduling itineraries specified for the target.
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2009-08-10 23:55:25 +08:00
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//
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//===----------------------------------------------------------------------===//
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2010-12-09 04:04:29 +08:00
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#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
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2010-06-15 05:06:53 +08:00
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#include "llvm/CodeGen/ScheduleDAG.h"
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2017-02-23 06:32:51 +08:00
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#include "llvm/MC/MCInstrDesc.h"
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2011-06-29 09:14:12 +08:00
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#include "llvm/MC/MCInstrItineraries.h"
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2017-02-23 06:32:51 +08:00
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#include "llvm/Support/Compiler.h"
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2009-08-10 23:55:25 +08:00
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#include "llvm/Support/Debug.h"
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2009-08-11 09:44:26 +08:00
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#include "llvm/Support/raw_ostream.h"
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2011-01-21 13:51:33 +08:00
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#include "llvm/Target/TargetInstrInfo.h"
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2017-02-23 06:32:51 +08:00
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#include <cassert>
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2009-08-10 23:55:25 +08:00
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2009-08-23 04:08:44 +08:00
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using namespace llvm;
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2009-08-10 23:55:25 +08:00
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2016-04-20 08:21:24 +08:00
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#define DEBUG_TYPE DebugType
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2014-04-22 10:02:50 +08:00
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2016-04-20 08:21:24 +08:00
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ScoreboardHazardRecognizer::ScoreboardHazardRecognizer(
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const InstrItineraryData *II, const ScheduleDAG *SchedDAG,
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const char *ParentDebugType)
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: ScheduleHazardRecognizer(), DebugType(ParentDebugType), ItinData(II),
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2017-02-23 06:32:51 +08:00
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DAG(SchedDAG) {
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2017-09-28 05:19:56 +08:00
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(void)DebugType;
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2012-06-05 11:44:32 +08:00
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// Determine the maximum depth of any itinerary. This determines the depth of
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// the scoreboard. We always make the scoreboard at least 1 cycle deep to
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// avoid dealing with the boundary condition.
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2010-04-08 02:19:24 +08:00
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unsigned ScoreboardDepth = 1;
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2010-09-10 09:29:16 +08:00
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if (ItinData && !ItinData->isEmpty()) {
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2009-08-10 23:55:25 +08:00
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for (unsigned idx = 0; ; ++idx) {
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2010-09-10 09:29:16 +08:00
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if (ItinData->isEndMarker(idx))
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2009-08-10 23:55:25 +08:00
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break;
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2010-09-10 09:29:16 +08:00
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const InstrStage *IS = ItinData->beginStage(idx);
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const InstrStage *E = ItinData->endStage(idx);
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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unsigned CurCycle = 0;
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2009-08-10 23:55:25 +08:00
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unsigned ItinDepth = 0;
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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for (; IS != E; ++IS) {
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unsigned StageDepth = CurCycle + IS->getCycles();
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if (ItinDepth < StageDepth) ItinDepth = StageDepth;
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CurCycle += IS->getNextCycles();
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}
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2009-08-10 23:55:25 +08:00
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2010-12-09 04:04:29 +08:00
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// Find the next power-of-2 >= ItinDepth
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while (ItinDepth > ScoreboardDepth) {
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ScoreboardDepth *= 2;
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2012-06-05 11:44:32 +08:00
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// Don't set MaxLookAhead until we find at least one nonzero stage.
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// This way, an itinerary with no stages has MaxLookAhead==0, which
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// completely bypasses the scoreboard hazard logic.
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MaxLookAhead = ScoreboardDepth;
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2010-12-09 04:04:29 +08:00
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}
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2009-08-10 23:55:25 +08:00
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}
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}
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2010-04-08 02:19:32 +08:00
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ReservedScoreboard.reset(ScoreboardDepth);
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RequiredScoreboard.reset(ScoreboardDepth);
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2009-08-10 23:55:25 +08:00
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2012-07-07 12:00:00 +08:00
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// If MaxLookAhead is not set above, then we are not enabled.
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2012-06-05 11:44:40 +08:00
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if (!isEnabled())
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2012-06-05 11:44:32 +08:00
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DEBUG(dbgs() << "Disabled scoreboard hazard recognizer\n");
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2012-06-05 11:44:40 +08:00
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else {
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2012-07-07 12:00:00 +08:00
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// A nonempty itinerary must have a SchedModel.
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2014-09-03 01:43:54 +08:00
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IssueWidth = ItinData->SchedModel.IssueWidth;
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2012-06-05 11:44:32 +08:00
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DEBUG(dbgs() << "Using scoreboard hazard recognizer: Depth = "
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<< ScoreboardDepth << '\n');
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2012-06-05 11:44:40 +08:00
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}
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2009-08-10 23:55:25 +08:00
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}
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2010-12-09 04:04:29 +08:00
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void ScoreboardHazardRecognizer::Reset() {
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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IssueCount = 0;
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2010-04-08 02:19:32 +08:00
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RequiredScoreboard.reset();
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ReservedScoreboard.reset();
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2009-08-10 23:55:25 +08:00
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}
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2012-09-12 06:23:19 +08:00
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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2016-01-30 04:50:44 +08:00
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LLVM_DUMP_METHOD void ScoreboardHazardRecognizer::Scoreboard::dump() const {
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2010-01-05 05:26:07 +08:00
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dbgs() << "Scoreboard:\n";
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2010-04-08 02:19:24 +08:00
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unsigned last = Depth - 1;
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while ((last > 0) && ((*this)[last] == 0))
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2009-08-10 23:55:25 +08:00
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last--;
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for (unsigned i = 0; i <= last; i++) {
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2012-06-23 04:27:13 +08:00
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unsigned FUs = (*this)[i];
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2010-01-05 05:26:07 +08:00
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dbgs() << "\t";
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2012-06-23 04:27:13 +08:00
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for (int j = 31; j >= 0; j--)
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dbgs() << ((FUs & (1 << j)) ? '1' : '0');
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2010-01-05 05:26:07 +08:00
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dbgs() << '\n';
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2009-08-10 23:55:25 +08:00
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}
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}
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2012-09-07 03:06:06 +08:00
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#endif
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2009-08-10 23:55:25 +08:00
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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bool ScoreboardHazardRecognizer::atIssueLimit() const {
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if (IssueWidth == 0)
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return false;
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return IssueCount == IssueWidth;
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}
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2010-06-16 15:35:02 +08:00
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ScheduleHazardRecognizer::HazardType
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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ScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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2010-09-10 09:29:16 +08:00
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if (!ItinData || ItinData->isEmpty())
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2009-09-23 00:47:52 +08:00
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return NoHazard;
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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// Note that stalls will be negative for bottom-up scheduling.
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int cycle = Stalls;
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2009-09-23 00:47:52 +08:00
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// Use the itinerary for the underlying instruction to check for
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// free FU's in the scoreboard at the appropriate future cycles.
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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2011-06-29 03:10:37 +08:00
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const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
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2014-04-14 08:51:57 +08:00
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if (!MCID) {
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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// Don't check hazards for non-machineinstr Nodes.
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return NoHazard;
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}
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2011-06-29 03:10:37 +08:00
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unsigned idx = MCID->getSchedClass();
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2010-09-10 09:29:16 +08:00
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for (const InstrStage *IS = ItinData->beginStage(idx),
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*E = ItinData->endStage(idx); IS != E; ++IS) {
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2009-09-23 00:47:52 +08:00
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// We must find one of the stage's units free for every cycle the
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// stage is occupied. FIXME it would be more accurate to find the
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// same unit free in all the cycles.
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for (unsigned int i = 0; i < IS->getCycles(); ++i) {
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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int StageCycle = cycle + (int)i;
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if (StageCycle < 0)
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continue;
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if (StageCycle >= (int)RequiredScoreboard.getDepth()) {
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assert((StageCycle - Stalls) < (int)RequiredScoreboard.getDepth() &&
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"Scoreboard depth exceeded!");
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// This stage was stalled beyond pipeline depth, so cannot conflict.
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break;
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}
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2010-04-08 02:19:24 +08:00
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2012-06-23 04:27:13 +08:00
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unsigned freeUnits = IS->getUnits();
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2010-04-08 02:19:32 +08:00
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switch (IS->getReservationKind()) {
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case InstrStage::Required:
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// Required FUs conflict with both reserved and required ones
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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freeUnits &= ~ReservedScoreboard[StageCycle];
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2016-08-17 13:10:15 +08:00
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LLVM_FALLTHROUGH;
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2010-04-08 02:19:32 +08:00
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case InstrStage::Reserved:
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// Reserved FUs can conflict only with required ones.
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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freeUnits &= ~RequiredScoreboard[StageCycle];
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2010-04-08 02:19:32 +08:00
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break;
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}
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2009-09-23 00:47:52 +08:00
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if (!freeUnits) {
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2012-05-26 19:37:37 +08:00
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DEBUG(dbgs() << "*** Hazard in cycle +" << StageCycle << ", ");
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2010-01-05 05:26:07 +08:00
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DEBUG(dbgs() << "SU(" << SU->NodeNum << "): ");
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
DEBUG(DAG->dumpNode(SU));
|
2009-09-23 00:47:52 +08:00
|
|
|
return Hazard;
|
|
|
|
}
|
2009-08-10 23:55:25 +08:00
|
|
|
}
|
2010-04-08 02:19:24 +08:00
|
|
|
|
2009-09-23 00:47:52 +08:00
|
|
|
// Advance the cycle to the next stage.
|
|
|
|
cycle += IS->getNextCycles();
|
2009-08-10 23:55:25 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return NoHazard;
|
|
|
|
}
|
2010-04-08 02:19:24 +08:00
|
|
|
|
2010-12-09 04:04:29 +08:00
|
|
|
void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) {
|
2010-09-10 09:29:16 +08:00
|
|
|
if (!ItinData || ItinData->isEmpty())
|
2009-09-23 00:47:52 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
// Use the itinerary for the underlying instruction to reserve FU's
|
|
|
|
// in the scoreboard at the appropriate future cycles.
|
2011-06-29 03:10:37 +08:00
|
|
|
const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
|
|
|
|
assert(MCID && "The scheduler must filter non-machineinstrs");
|
|
|
|
if (DAG->TII->isZeroCost(MCID->Opcode))
|
2011-01-21 13:51:33 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
++IssueCount;
|
|
|
|
|
|
|
|
unsigned cycle = 0;
|
|
|
|
|
2011-06-29 03:10:37 +08:00
|
|
|
unsigned idx = MCID->getSchedClass();
|
2010-09-10 09:29:16 +08:00
|
|
|
for (const InstrStage *IS = ItinData->beginStage(idx),
|
|
|
|
*E = ItinData->endStage(idx); IS != E; ++IS) {
|
2009-09-23 00:47:52 +08:00
|
|
|
// We must reserve one of the stage's units for every cycle the
|
|
|
|
// stage is occupied. FIXME it would be more accurate to reserve
|
|
|
|
// the same unit free in all the cycles.
|
|
|
|
for (unsigned int i = 0; i < IS->getCycles(); ++i) {
|
2010-04-08 02:19:32 +08:00
|
|
|
assert(((cycle + i) < RequiredScoreboard.getDepth()) &&
|
2009-09-23 00:47:52 +08:00
|
|
|
"Scoreboard depth exceeded!");
|
2010-04-08 02:19:24 +08:00
|
|
|
|
2012-06-23 04:27:13 +08:00
|
|
|
unsigned freeUnits = IS->getUnits();
|
2010-04-08 02:19:32 +08:00
|
|
|
switch (IS->getReservationKind()) {
|
|
|
|
case InstrStage::Required:
|
|
|
|
// Required FUs conflict with both reserved and required ones
|
|
|
|
freeUnits &= ~ReservedScoreboard[cycle + i];
|
2016-08-17 13:10:15 +08:00
|
|
|
LLVM_FALLTHROUGH;
|
2010-04-08 02:19:32 +08:00
|
|
|
case InstrStage::Reserved:
|
|
|
|
// Reserved FUs can conflict only with required ones.
|
|
|
|
freeUnits &= ~RequiredScoreboard[cycle + i];
|
|
|
|
break;
|
|
|
|
}
|
2010-04-08 02:19:24 +08:00
|
|
|
|
2009-09-23 00:47:52 +08:00
|
|
|
// reduce to a single unit
|
2012-06-23 04:27:13 +08:00
|
|
|
unsigned freeUnit = 0;
|
2009-09-23 00:47:52 +08:00
|
|
|
do {
|
|
|
|
freeUnit = freeUnits;
|
|
|
|
freeUnits = freeUnit & (freeUnit - 1);
|
|
|
|
} while (freeUnits);
|
2010-04-08 02:19:24 +08:00
|
|
|
|
2010-04-08 02:19:32 +08:00
|
|
|
if (IS->getReservationKind() == InstrStage::Required)
|
|
|
|
RequiredScoreboard[cycle + i] |= freeUnit;
|
|
|
|
else
|
|
|
|
ReservedScoreboard[cycle + i] |= freeUnit;
|
2009-08-10 23:55:25 +08:00
|
|
|
}
|
2010-04-08 02:19:24 +08:00
|
|
|
|
2009-09-23 00:47:52 +08:00
|
|
|
// Advance the cycle to the next stage.
|
|
|
|
cycle += IS->getNextCycles();
|
2009-08-10 23:55:25 +08:00
|
|
|
}
|
2010-04-08 02:19:24 +08:00
|
|
|
|
2010-04-08 02:19:32 +08:00
|
|
|
DEBUG(ReservedScoreboard.dump());
|
|
|
|
DEBUG(RequiredScoreboard.dump());
|
2009-08-10 23:55:25 +08:00
|
|
|
}
|
2010-04-08 02:19:24 +08:00
|
|
|
|
2010-12-09 04:04:29 +08:00
|
|
|
void ScoreboardHazardRecognizer::AdvanceCycle() {
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
IssueCount = 0;
|
2010-04-08 02:19:32 +08:00
|
|
|
ReservedScoreboard[0] = 0; ReservedScoreboard.advance();
|
|
|
|
RequiredScoreboard[0] = 0; RequiredScoreboard.advance();
|
2009-08-10 23:55:25 +08:00
|
|
|
}
|
2010-12-09 04:04:29 +08:00
|
|
|
|
|
|
|
void ScoreboardHazardRecognizer::RecedeCycle() {
|
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
|
|
|
IssueCount = 0;
|
2010-12-09 04:04:29 +08:00
|
|
|
ReservedScoreboard[ReservedScoreboard.getDepth()-1] = 0;
|
|
|
|
ReservedScoreboard.recede();
|
|
|
|
RequiredScoreboard[RequiredScoreboard.getDepth()-1] = 0;
|
|
|
|
RequiredScoreboard.recede();
|
|
|
|
}
|