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llvm-project/llvm/docs/AMDGPU/gfx8_vdst_15.rst

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[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
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[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 22:16:22 +08:00
.. _amdgpu_synid_gfx8_vdst_15:
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
vdst
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 22:16:22 +08:00
====
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
Instruction output: data read from a memory buffer.
*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`