Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/*===--------- avx512vlbf16intrin.h - AVX512_BF16 intrinsics ---------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __IMMINTRIN_H
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#error "Never use <avx512vlbf16intrin.h> directly; include <immintrin.h> instead."
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#endif
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#ifndef __AVX512VLBF16INTRIN_H
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#define __AVX512VLBF16INTRIN_H
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typedef short __m128bh __attribute__((__vector_size__(16), __aligned__(16)));
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#define __DEFAULT_FN_ATTRS128 \
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__attribute__((__always_inline__, __nodebug__, \
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__target__("avx512vl, avx512bf16"), __min_vector_width__(128)))
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#define __DEFAULT_FN_ATTRS256 \
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__attribute__((__always_inline__, __nodebug__, \
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__target__("avx512vl, avx512bf16"), __min_vector_width__(256)))
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/// Convert Two Packed Single Data to One Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 128-bit vector of [4 x float].
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/// \param __B
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/// A 128-bit vector of [4 x float].
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/// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __B, and higher 64 bits come from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m128bh __DEFAULT_FN_ATTRS128
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_mm_cvtne2ps_pbh(__m128 __A, __m128 __B) {
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return (__m128bh)__builtin_ia32_cvtne2ps2bf16_128((__v4sf) __A,
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(__v4sf) __B);
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}
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/// Convert Two Packed Single Data to One Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 128-bit vector of [4 x float].
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/// \param __B
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/// A 128-bit vector of [4 x float].
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/// \param __W
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/// A 128-bit vector of [8 x bfloat].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 8-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A or __B. A 0 means element from __W.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __B, and higher 64 bits come from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m128bh __DEFAULT_FN_ATTRS128
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_mm_mask_cvtne2ps_pbh(__m128bh __W, __mmask8 __U, __m128 __A, __m128 __B) {
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return (__m128bh)__builtin_ia32_selectw_128((__mmask8)__U,
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(__v8hi)_mm_cvtne2ps_pbh(__A, __B),
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(__v8hi)__W);
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}
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/// Convert Two Packed Single Data to One Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 128-bit vector of [4 x float].
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/// \param __B
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/// A 128-bit vector of [4 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 8-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A or __B. A 0 means element is zero.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __B, and higher 64 bits come from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m128bh __DEFAULT_FN_ATTRS128
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_mm_maskz_cvtne2ps_pbh(__mmask8 __U, __m128 __A, __m128 __B) {
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return (__m128bh)__builtin_ia32_selectw_128((__mmask8)__U,
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(__v8hi)_mm_cvtne2ps_pbh(__A, __B),
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(__v8hi)_mm_setzero_si128());
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}
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/// Convert Two Packed Single Data to One Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 256-bit vector of [8 x float].
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/// \param __B
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/// A 256-bit vector of [8 x float].
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/// \returns A 256-bit vector of [16 x bfloat] whose lower 128 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __B, and higher 128 bits come from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m256bh __DEFAULT_FN_ATTRS256
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_mm256_cvtne2ps_pbh(__m256 __A, __m256 __B) {
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return (__m256bh)__builtin_ia32_cvtne2ps2bf16_256((__v8sf) __A,
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(__v8sf) __B);
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}
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/// Convert Two Packed Single Data to One Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 256-bit vector of [8 x float].
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/// \param __B
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/// A 256-bit vector of [8 x float].
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/// \param __W
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/// A 256-bit vector of [16 x bfloat].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 16-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A or __B. A 0 means element from __W.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 256-bit vector of [16 x bfloat] whose lower 128 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __B, and higher 128 bits come from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m256bh __DEFAULT_FN_ATTRS256
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_mm256_mask_cvtne2ps_pbh(__m256bh __W, __mmask16 __U, __m256 __A, __m256 __B) {
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return (__m256bh)__builtin_ia32_selectw_256((__mmask16)__U,
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(__v16hi)_mm256_cvtne2ps_pbh(__A, __B),
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(__v16hi)__W);
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}
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/// Convert Two Packed Single Data to One Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 256-bit vector of [8 x float].
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/// \param __B
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/// A 256-bit vector of [8 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 16-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A or __B. A 0 means element is zero.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 256-bit vector of [16 x bfloat] whose lower 128 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __B, and higher 128 bits come from conversion of __A.
|
Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m256bh __DEFAULT_FN_ATTRS256
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_mm256_maskz_cvtne2ps_pbh(__mmask16 __U, __m256 __A, __m256 __B) {
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return (__m256bh)__builtin_ia32_selectw_256((__mmask16)__U,
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(__v16hi)_mm256_cvtne2ps_pbh(__A, __B),
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(__v16hi)_mm256_setzero_si256());
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}
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/// Convert Packed Single Data to Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 128-bit vector of [4 x float].
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/// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __A, and higher 64 bits are 0.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m128bh __DEFAULT_FN_ATTRS128
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_mm_cvtneps_pbh(__m128 __A) {
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return (__m128bh)__builtin_ia32_cvtneps2bf16_128_mask((__v4sf) __A,
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(__v8hi)_mm_undefined_si128(),
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(__mmask8)-1);
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}
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/// Convert Packed Single Data to Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 128-bit vector of [4 x float].
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/// \param __W
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/// A 128-bit vector of [8 x bfloat].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 4-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A. A 0 means element from __W.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __A, and higher 64 bits are 0.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m128bh __DEFAULT_FN_ATTRS128
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_mm_mask_cvtneps_pbh(__m128bh __W, __mmask8 __U, __m128 __A) {
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return (__m128bh)__builtin_ia32_cvtneps2bf16_128_mask((__v4sf) __A,
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(__v8hi)__W,
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(__mmask8)__U);
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}
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/// Convert Packed Single Data to Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 128-bit vector of [4 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 4-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A. A 0 means element is zero.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __A, and higher 64 bits are 0.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m128bh __DEFAULT_FN_ATTRS128
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_mm_maskz_cvtneps_pbh(__mmask8 __U, __m128 __A) {
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return (__m128bh)__builtin_ia32_cvtneps2bf16_128_mask((__v4sf) __A,
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(__v8hi)_mm_setzero_si128(),
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(__mmask8)__U);
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}
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/// Convert Packed Single Data to Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 256-bit vector of [8 x float].
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2019-05-17 01:34:35 +08:00
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/// \returns A 128-bit vector of [8 x bfloat] comes from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m128bh __DEFAULT_FN_ATTRS256
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_mm256_cvtneps_pbh(__m256 __A) {
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2019-05-17 02:28:17 +08:00
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return (__m128bh)__builtin_ia32_cvtneps2bf16_256_mask((__v8sf)__A,
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(__v8hi)_mm_undefined_si128(),
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(__mmask8)-1);
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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}
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/// Convert Packed Single Data to Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 256-bit vector of [8 x float].
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/// \param __W
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/// A 256-bit vector of [8 x bfloat].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 8-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A. A 0 means element from __W.
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/// \returns A 128-bit vector of [8 x bfloat] comes from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m128bh __DEFAULT_FN_ATTRS256
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_mm256_mask_cvtneps_pbh(__m128bh __W, __mmask8 __U, __m256 __A) {
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2019-05-17 02:28:17 +08:00
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return (__m128bh)__builtin_ia32_cvtneps2bf16_256_mask((__v8sf)__A,
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(__v8hi)__W,
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(__mmask8)__U);
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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}
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/// Convert Packed Single Data to Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 256-bit vector of [8 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 8-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A. A 0 means element is zero.
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/// \returns A 128-bit vector of [8 x bfloat] comes from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m128bh __DEFAULT_FN_ATTRS256
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_mm256_maskz_cvtneps_pbh(__mmask8 __U, __m256 __A) {
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2019-05-17 02:28:17 +08:00
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return (__m128bh)__builtin_ia32_cvtneps2bf16_256_mask((__v8sf)__A,
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(__v8hi)_mm_setzero_si128(),
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(__mmask8)__U);
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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}
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/// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
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///
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/// \param __A
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/// A 128-bit vector of [8 x bfloat].
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/// \param __B
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/// A 128-bit vector of [8 x bfloat].
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/// \param __D
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/// A 128-bit vector of [4 x float].
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/// \returns A 128-bit vector of [4 x float] comes from Dot Product of
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/// __A, __B and __D
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static __inline__ __m128 __DEFAULT_FN_ATTRS128
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_mm_dpbf16_ps(__m128 __D, __m128bh __A, __m128bh __B) {
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return (__m128)__builtin_ia32_dpbf16ps_128((__v4sf)__D,
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(__v4si)__A,
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(__v4si)__B);
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}
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/// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
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///
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/// \param __A
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/// A 128-bit vector of [8 x bfloat].
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/// \param __B
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/// A 128-bit vector of [8 x bfloat].
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/// \param __D
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/// A 128-bit vector of [4 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 8-bit mask value specifying what is chosen for each element.
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/// A 1 means __A and __B's dot product accumulated with __D. A 0 means __D.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 128-bit vector of [4 x float] comes from Dot Product of
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/// __A, __B and __D
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static __inline__ __m128 __DEFAULT_FN_ATTRS128
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_mm_mask_dpbf16_ps(__m128 __D, __mmask8 __U, __m128bh __A, __m128bh __B) {
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return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
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(__v4sf)_mm_dpbf16_ps(__D, __A, __B),
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(__v4sf)__D);
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}
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/// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
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///
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/// \param __A
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/// A 128-bit vector of [8 x bfloat].
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/// \param __B
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/// A 128-bit vector of [8 x bfloat].
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/// \param __D
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/// A 128-bit vector of [4 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 8-bit mask value specifying what is chosen for each element.
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/// A 1 means __A and __B's dot product accumulated with __D. A 0 means 0.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 128-bit vector of [4 x float] comes from Dot Product of
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/// __A, __B and __D
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static __inline__ __m128 __DEFAULT_FN_ATTRS128
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_mm_maskz_dpbf16_ps(__mmask8 __U, __m128 __D, __m128bh __A, __m128bh __B) {
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return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
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(__v4sf)_mm_dpbf16_ps(__D, __A, __B),
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(__v4sf)_mm_setzero_si128());
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}
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/// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
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///
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/// \param __A
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/// A 256-bit vector of [16 x bfloat].
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/// \param __B
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/// A 256-bit vector of [16 x bfloat].
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/// \param __D
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/// A 256-bit vector of [8 x float].
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/// \returns A 256-bit vector of [8 x float] comes from Dot Product of
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/// __A, __B and __D
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static __inline__ __m256 __DEFAULT_FN_ATTRS256
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_mm256_dpbf16_ps(__m256 __D, __m256bh __A, __m256bh __B) {
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return (__m256)__builtin_ia32_dpbf16ps_256((__v8sf)__D,
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(__v8si)__A,
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(__v8si)__B);
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}
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/// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
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///
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/// \param __A
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/// A 256-bit vector of [16 x bfloat].
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/// \param __B
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/// A 256-bit vector of [16 x bfloat].
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/// \param __D
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/// A 256-bit vector of [8 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 16-bit mask value specifying what is chosen for each element.
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/// A 1 means __A and __B's dot product accumulated with __D. A 0 means __D.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 256-bit vector of [8 x float] comes from Dot Product of
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/// __A, __B and __D
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static __inline__ __m256 __DEFAULT_FN_ATTRS256
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_mm256_mask_dpbf16_ps(__m256 __D, __mmask8 __U, __m256bh __A, __m256bh __B) {
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return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
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(__v8sf)_mm256_dpbf16_ps(__D, __A, __B),
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(__v8sf)__D);
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}
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/// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
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///
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/// \param __A
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/// A 256-bit vector of [16 x bfloat].
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/// \param __B
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/// A 256-bit vector of [16 x bfloat].
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/// \param __D
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/// A 256-bit vector of [8 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 8-bit mask value specifying what is chosen for each element.
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/// A 1 means __A and __B's dot product accumulated with __D. A 0 means 0.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 256-bit vector of [8 x float] comes from Dot Product of
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/// __A, __B and __D
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static __inline__ __m256 __DEFAULT_FN_ATTRS256
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_mm256_maskz_dpbf16_ps(__mmask8 __U, __m256 __D, __m256bh __A, __m256bh __B) {
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return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
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(__v8sf)_mm256_dpbf16_ps(__D, __A, __B),
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(__v8sf)_mm256_setzero_si256());
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}
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2019-05-17 01:34:35 +08:00
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2019-06-11 09:17:28 +08:00
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/// Convert One Single float Data to One BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
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///
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/// \param __A
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/// A float data.
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/// \returns A bf16 data whose sign field and exponent field keep unchanged,
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/// and fraction field is truncated to 7 bits.
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static __inline__ __bfloat16 __DEFAULT_FN_ATTRS128 _mm_cvtness_sbh(float __A) {
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__v4sf __V = {__A, 0, 0, 0};
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__v8hi __R = __builtin_ia32_cvtneps2bf16_128_mask(
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(__v4sf)__V, (__v8hi)_mm_undefined_si128(), (__mmask8)-1);
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return __R[0];
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}
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/// Convert Packed BF16 Data to Packed float Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// \param __A
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/// A 128-bit vector of [8 x bfloat].
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/// \returns A 256-bit vector of [8 x float] come from convertion of __A
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static __inline__ __m256 __DEFAULT_FN_ATTRS256 _mm256_cvtpbh_ps(__m128bh __A) {
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return _mm256_castsi256_ps((__m256i)_mm256_slli_epi32(
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(__m256i)_mm256_cvtepi16_epi32((__m128i)__A), 16));
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}
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/// Convert Packed BF16 Data to Packed float Data using zeroing mask.
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///
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/// \headerfile <x86intrin.h>
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///
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/// \param __U
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/// A 8-bit mask. Elements are zeroed out when the corresponding mask
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/// bit is not set.
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/// \param __A
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/// A 128-bit vector of [8 x bfloat].
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/// \returns A 256-bit vector of [8 x float] come from convertion of __A
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static __inline__ __m256 __DEFAULT_FN_ATTRS256
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_mm256_maskz_cvtpbh_ps(__mmask8 __U, __m128bh __A) {
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return _mm256_castsi256_ps((__m256i)_mm256_slli_epi32(
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(__m256i)_mm256_maskz_cvtepi16_epi32((__mmask8)__U, (__m128i)__A), 16));
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}
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/// Convert Packed BF16 Data to Packed float Data using merging mask.
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///
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/// \headerfile <x86intrin.h>
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///
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/// \param __S
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/// A 256-bit vector of [8 x float]. Elements are copied from __S when
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/// the corresponding mask bit is not set.
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/// \param __U
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/// A 8-bit mask. Elements are zeroed out when the corresponding mask
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/// bit is not set.
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/// \param __A
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/// A 128-bit vector of [8 x bfloat].
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/// \returns A 256-bit vector of [8 x float] come from convertion of __A
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static __inline__ __m256 __DEFAULT_FN_ATTRS256
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_mm256_mask_cvtpbh_ps(__m256 __S, __mmask8 __U, __m128bh __A) {
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return _mm256_castsi256_ps((__m256i)_mm256_mask_slli_epi32(
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(__m256i)__S, (__mmask8)__U, (__m256i)_mm256_cvtepi16_epi32((__m128i)__A),
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16));
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}
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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#undef __DEFAULT_FN_ATTRS128
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#undef __DEFAULT_FN_ATTRS256
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#endif
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