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llvm-project/llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir

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[Hexagon] Add implicit uses even when untied explicit uses are present An explicit untied use is not sufficient to maintain liveness of a register redefined in a predicated instruction. For example %1 = COPY %0 ... %1 = A2_paddif %2, %1, 1 could become $r1 = COPY $r0 ... $r1 = A2_paddif $p0, $r1, 1 and later $r1 = COPY $r0 ;; this is not really dead! ... $r1 = A2_paddif $p0, $r0, 1 llvm-svn: 336662
2018-07-10 20:57:49 +08:00
# RUN: llc -march=hexagon -run-pass=expand-condsets %s -o - | FileCheck %s
# Check that there is a tied implicit use despite having an explicit (but
# untied) use:
# CHECK: %[[R:[0-9]+]]:intregs = A2_paddif killed %{{[0-9]+}}, %[[R]], 1, implicit %[[R]](tied-def 0)
name: f0
tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1
liveins: $r0, $r1
%0:intregs = COPY $r0
[Hexagon] Change .mir testcase to make sure function is not in SSA form If a machine function satisfies SSA, the IsSSA property is assumed even if the pass to be executed runs after existing from SSA. If the pass output then does not conform to SSA, a verifier error will be flagged (with expensive checks enabled). llvm-svn: 336682
2018-07-10 22:49:54 +08:00
%0:intregs = COPY $r0 ; defeat IsSSA detection
[Hexagon] Add implicit uses even when untied explicit uses are present An explicit untied use is not sufficient to maintain liveness of a register redefined in a predicated instruction. For example %1 = COPY %0 ... %1 = A2_paddif %2, %1, 1 could become $r1 = COPY $r0 ... $r1 = A2_paddif $p0, $r1, 1 and later $r1 = COPY $r0 ;; this is not really dead! ... $r1 = A2_paddif $p0, $r0, 1 llvm-svn: 336662
2018-07-10 20:57:49 +08:00
%1:intregs = COPY $r1
%2:intregs = COPY $r0
%3:intregs = M2_mpyi %2, %1
%4:intregs = A2_sub %0, %3
%5:predregs = C2_cmpeqi %4, 0
%6:intregs = A2_addi %2, 1
%7:intregs = C2_mux %5, %2, %6
bb.1:
...