2017-10-20 05:37:38 +08:00
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//===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2017-10-20 05:37:38 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCV specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVSubtarget.h"
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#include "RISCV.h"
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
Summary:
Add an initial GlobalISel skeleton for RISCV. It can only run ir translator for `ret void`.
Patch by Andrew Wei
Reviewers: asb, sabuasal, apazos, lenary, simoncook, lewis-revill, edward-jones, rogfer01, xiangzhai, rovka, Petar.Avramovic, mgorny, dsanders
Reviewed By: dsanders
Subscribers: pzheng, s.egerton, dsanders, hiraditya, rbar, johnrusso, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65219
llvm-svn: 369467
2019-08-21 06:53:24 +08:00
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#include "RISCVCallLowering.h"
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2017-10-20 05:37:38 +08:00
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#include "RISCVFrameLowering.h"
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
Summary:
Add an initial GlobalISel skeleton for RISCV. It can only run ir translator for `ret void`.
Patch by Andrew Wei
Reviewers: asb, sabuasal, apazos, lenary, simoncook, lewis-revill, edward-jones, rogfer01, xiangzhai, rovka, Petar.Avramovic, mgorny, dsanders
Reviewed By: dsanders
Subscribers: pzheng, s.egerton, dsanders, hiraditya, rbar, johnrusso, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65219
llvm-svn: 369467
2019-08-21 06:53:24 +08:00
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#include "RISCVLegalizerInfo.h"
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#include "RISCVRegisterBankInfo.h"
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#include "RISCVTargetMachine.h"
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2017-10-20 05:37:38 +08:00
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "RISCVGenSubtargetInfo.inc"
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2021-02-10 02:47:19 +08:00
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static cl::opt<unsigned> RVVVectorBitsMax(
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"riscv-v-vector-bits-max",
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cl::desc("Assume V extension vector registers are at most this big, "
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"with zero meaning no maximum size is assumed."),
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cl::init(0), cl::Hidden);
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2021-02-09 02:32:32 +08:00
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static cl::opt<unsigned> RVVVectorBitsMin(
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"riscv-v-vector-bits-min",
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cl::desc("Assume V extension vector registers are at least this big, "
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"with zero meaning no minimum size is assumed."),
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cl::init(0), cl::Hidden);
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static cl::opt<unsigned> RVVVectorLMULMax(
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"riscv-v-fixed-length-vector-lmul-max",
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cl::desc("The maximum LMUL value to use for fixed length vectors. "
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"Fractional LMUL values are not supported."),
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cl::init(8), cl::Hidden);
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2017-10-20 05:37:38 +08:00
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void RISCVSubtarget::anchor() {}
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2019-03-09 17:28:06 +08:00
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RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
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2020-10-06 14:33:43 +08:00
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const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {
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2017-10-20 05:37:38 +08:00
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// Determine default and user-specified characteristics
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2019-03-09 17:28:06 +08:00
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bool Is64Bit = TT.isArch64Bit();
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2020-01-29 03:23:46 +08:00
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std::string CPUName = std::string(CPU);
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2020-10-06 14:33:43 +08:00
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std::string TuneCPUName = std::string(TuneCPU);
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2017-10-20 05:37:38 +08:00
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if (CPUName.empty())
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CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
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2020-10-06 14:33:43 +08:00
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if (TuneCPUName.empty())
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TuneCPUName = CPUName;
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ParseSubtargetFeatures(CPUName, TuneCPUName, FS);
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2017-10-20 05:37:38 +08:00
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if (Is64Bit) {
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XLenVT = MVT::i64;
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XLen = 64;
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}
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2019-03-09 17:28:06 +08:00
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TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
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2019-03-22 19:21:40 +08:00
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RISCVFeatures::validate(TT, getFeatureBits());
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2017-10-20 05:37:38 +08:00
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return *this;
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}
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2020-10-06 14:33:43 +08:00
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RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
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StringRef TuneCPU, StringRef FS,
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2019-03-09 17:28:06 +08:00
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StringRef ABIName, const TargetMachine &TM)
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2020-10-06 14:33:43 +08:00
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: RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
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2019-10-23 04:25:01 +08:00
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UserReservedRegister(RISCV::NUM_TARGET_REGS),
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2020-10-06 14:33:43 +08:00
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FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
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[RISCV] Add MachineInstr immediate verification
Summary:
This patch implements the `TargetInstrInfo::verifyInstruction` hook for RISC-V. Currently the hook verifies the machine instruction's immediate operands, to check if the immediates are within the expected bounds. Without the hook invalid immediates are not detected except when doing assembly parsing, so they are silently emitted (including being truncated when emitting object code).
The bounds information is specified in tablegen by using the `OperandType` definition, which sets the `MCOperandInfo`'s `OperandType` field. Several RISC-V-specific immediate operand types were created, which extend the `MCInstrDesc`'s `OperandType` `enum`.
To have the hook called with `llc` pass it the `-verify-machineinstrs` option. For Clang add the cmake build config `-DLLVM_ENABLE_EXPENSIVE_CHECKS=True`, or temporarily patch `TargetPassConfig::addVerifyPass`.
Review concerns:
- The patch adds immediate operand type checks that cover at least the base ISA. There are several other operand types for the C extension and one type for the F/D extensions that were left out of this initial patch because they introduced further design concerns that I felt were best evaluated separately.
- Invalid register classes (e.g. passing a GPR register where a GPRC is expected) are already caught, so were not included.
- This design makes the more abstract `MachineInstr` verification depend on MC layer definitions, which arguably is not the cleanest design, but is in line with how things are done in other parts of the target and LLVM in general.
- There is some duplication of logic already present in the `MCOperandPredicate`s. Since the `MachineInstr` and `MCInstr` notions of immediates are fundamentally different, this is currently necessary.
Reviewers: asb, lenary
Reviewed By: lenary
Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67397
llvm-svn: 375006
2019-10-16 23:06:02 +08:00
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InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
Summary:
Add an initial GlobalISel skeleton for RISCV. It can only run ir translator for `ret void`.
Patch by Andrew Wei
Reviewers: asb, sabuasal, apazos, lenary, simoncook, lewis-revill, edward-jones, rogfer01, xiangzhai, rovka, Petar.Avramovic, mgorny, dsanders
Reviewed By: dsanders
Subscribers: pzheng, s.egerton, dsanders, hiraditya, rbar, johnrusso, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65219
llvm-svn: 369467
2019-08-21 06:53:24 +08:00
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CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
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Legalizer.reset(new RISCVLegalizerInfo(*this));
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2020-03-20 18:02:50 +08:00
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auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
Summary:
Add an initial GlobalISel skeleton for RISCV. It can only run ir translator for `ret void`.
Patch by Andrew Wei
Reviewers: asb, sabuasal, apazos, lenary, simoncook, lewis-revill, edward-jones, rogfer01, xiangzhai, rovka, Petar.Avramovic, mgorny, dsanders
Reviewed By: dsanders
Subscribers: pzheng, s.egerton, dsanders, hiraditya, rbar, johnrusso, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65219
llvm-svn: 369467
2019-08-21 06:53:24 +08:00
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RegBankInfo.reset(RBI);
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InstSelector.reset(createRISCVInstructionSelector(
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*static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
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}
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const CallLowering *RISCVSubtarget::getCallLowering() const {
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return CallLoweringInfo.get();
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}
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InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
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return InstSelector.get();
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}
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const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
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return Legalizer.get();
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}
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const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
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return RegBankInfo.get();
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}
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2021-02-09 02:32:32 +08:00
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2021-02-10 02:47:19 +08:00
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unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
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assert(hasStdExtV() && "Tried to get vector length without V support!");
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if (RVVVectorBitsMax == 0)
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return 0;
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assert(RVVVectorBitsMax >= 128 && isPowerOf2_32(RVVVectorBitsMax) &&
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"V extension requires vector length to be at least 128 and a power of "
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"2!");
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assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
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"Minimum V extension vector length should not be larger than its "
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"maximum!");
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unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
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return PowerOf2Floor(Max < 128 ? 0 : Max);
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}
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2021-02-09 02:32:32 +08:00
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unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
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assert(hasStdExtV() &&
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"Tried to get vector length without V extension support!");
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assert((RVVVectorBitsMin == 0 ||
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(RVVVectorBitsMin >= 128 && isPowerOf2_32(RVVVectorBitsMin))) &&
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"V extension requires vector length to be at least 128 and a power of "
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"2!");
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2021-02-10 02:47:19 +08:00
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assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
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"Minimum V extension vector length should not be larger than its "
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"maximum!");
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unsigned Min = RVVVectorBitsMin;
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if (RVVVectorBitsMax != 0)
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Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
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return PowerOf2Floor(Min < 128 ? 0 : Min);
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2021-02-09 02:32:32 +08:00
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}
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unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
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assert(hasStdExtV() &&
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"Tried to get maximum LMUL without V extension support!");
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assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) &&
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"V extension requires a LMUL to be at most 8 and a power of 2!");
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return PowerOf2Floor(std::max<unsigned>(RVVVectorLMULMax, 1));
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}
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bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
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return hasStdExtV() && getMinRVVVectorSizeInBits() != 0;
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}
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unsigned RISCVSubtarget::getLMULForFixedLengthVector(MVT VT) const {
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unsigned MinVLen = getMinRVVVectorSizeInBits();
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2021-02-12 01:13:15 +08:00
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// Masks only occupy a single register. An LMUL==1 operation can only use
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// at most 1/8 of the register. Only an LMUL==8 operaton on i8 types can
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// use the whole register.
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if (VT.getVectorElementType() == MVT::i1)
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MinVLen /= 8;
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2021-02-09 02:32:32 +08:00
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return divideCeil(VT.getSizeInBits(), MinVLen);
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}
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