2017-11-09 23:45:42 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
2017-10-20 05:37:38 +08:00
|
|
|
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
|
|
|
|
; RUN: | FileCheck %s -check-prefix=RV32I
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
|
|
|
|
; RUN: | FileCheck %s -check-prefix=RV64I
|
2017-10-20 05:37:38 +08:00
|
|
|
|
[RISCV] Add support for the various RISC-V FMA instruction variants
Adds support for the various RISC-V FMA instructions (fmadd, fmsub, fnmsub, fnmadd).
The criteria for choosing whether a fused add or subtract is used, as well as
whether the product is negated or not, is whether some of the arguments to the
llvm.fma.* intrinsic are negated or not. In the tests, extraneous fadd
instructions were added to avoid the negation being performed using a xor
trick, which prevented the proper FMA forms from being selected and thus
tested.
The FMA instruction patterns might seem incorrect (e.g., fnmadd: -rs1 * rs2 -
rs3), but they should be correct. The misleading names were inherited from
MIPS, where the negation happens after computing the sum.
The llvm.fmuladd.* intrinsics still do not generate RISC-V FMA instructions,
as that depends on TargetLowering::isFMAFasterthanFMulAndFAdd.
Some comments in the test files about what type of instructions are there
tested were updated, to better reflect the current content of those test
files.
Differential Revision: https://reviews.llvm.org/D54205
Patch by Luís Marques.
llvm-svn: 349023
2018-12-13 18:49:05 +08:00
|
|
|
; These tests are each targeted at a particular RISC-V ALU instruction. Most
|
|
|
|
; other files in this folder exercise LLVM IR instructions that don't directly
|
|
|
|
; match a RISC-V instruction.
|
[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
2017-11-21 16:11:03 +08:00
|
|
|
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
; Register-immediate instructions.
|
|
|
|
|
|
|
|
; TODO: Sign-extension would also work when promoting the operands of
|
|
|
|
; sltu/sltiu on RV64 and is cheaper than zero-extension (1 instruction vs 2).
|
2017-10-20 05:37:38 +08:00
|
|
|
|
|
|
|
define i32 @addi(i32 %a) nounwind {
|
|
|
|
; RV32I-LABEL: addi:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: addi a0, a0, 1
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: addi:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: addi a0, a0, 1
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = add i32 %a, 1
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @slti(i32 %a) nounwind {
|
|
|
|
; RV32I-LABEL: slti:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: slti a0, a0, 2
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: slti:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: sext.w a0, a0
|
|
|
|
; RV64I-NEXT: slti a0, a0, 2
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = icmp slt i32 %a, 2
|
|
|
|
%2 = zext i1 %1 to i32
|
|
|
|
ret i32 %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @sltiu(i32 %a) nounwind {
|
|
|
|
; RV32I-LABEL: sltiu:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: sltiu a0, a0, 3
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: sltiu:
|
|
|
|
; RV64I: # %bb.0:
|
2018-11-30 17:56:54 +08:00
|
|
|
; RV64I-NEXT: sext.w a0, a0
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
; RV64I-NEXT: sltiu a0, a0, 3
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = icmp ult i32 %a, 3
|
|
|
|
%2 = zext i1 %1 to i32
|
|
|
|
ret i32 %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @xori(i32 %a) nounwind {
|
|
|
|
; RV32I-LABEL: xori:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: xori a0, a0, 4
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: xori:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: xori a0, a0, 4
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = xor i32 %a, 4
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @ori(i32 %a) nounwind {
|
|
|
|
; RV32I-LABEL: ori:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: ori a0, a0, 5
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: ori:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: ori a0, a0, 5
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = or i32 %a, 5
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @andi(i32 %a) nounwind {
|
|
|
|
; RV32I-LABEL: andi:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: andi a0, a0, 6
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: andi:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: andi a0, a0, 6
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = and i32 %a, 6
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @slli(i32 %a) nounwind {
|
|
|
|
; RV32I-LABEL: slli:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: slli a0, a0, 7
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: slli:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: slli a0, a0, 7
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = shl i32 %a, 7
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @srli(i32 %a) nounwind {
|
|
|
|
; RV32I-LABEL: srli:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: srli a0, a0, 8
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: srli:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: srliw a0, a0, 8
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = lshr i32 %a, 8
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @srai(i32 %a) nounwind {
|
|
|
|
; RV32I-LABEL: srai:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: srai a0, a0, 9
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: srai:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: sraiw a0, a0, 9
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = ashr i32 %a, 9
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
; Register-register instructions
|
|
|
|
|
|
|
|
define i32 @add(i32 %a, i32 %b) nounwind {
|
|
|
|
; RV32I-LABEL: add:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: add a0, a0, a1
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: add:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: add a0, a0, a1
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = add i32 %a, %b
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @sub(i32 %a, i32 %b) nounwind {
|
|
|
|
; RV32I-LABEL: sub:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: sub a0, a0, a1
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: sub:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: sub a0, a0, a1
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = sub i32 %a, %b
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @sll(i32 %a, i32 %b) nounwind {
|
|
|
|
; RV32I-LABEL: sll:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: sll a0, a0, a1
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: sll:
|
|
|
|
; RV64I: # %bb.0:
|
2019-01-12 15:32:31 +08:00
|
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = shl i32 %a, %b
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @slt(i32 %a, i32 %b) nounwind {
|
|
|
|
; RV32I-LABEL: slt:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: slt a0, a0, a1
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: slt:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: sext.w a1, a1
|
|
|
|
; RV64I-NEXT: sext.w a0, a0
|
|
|
|
; RV64I-NEXT: slt a0, a0, a1
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = icmp slt i32 %a, %b
|
|
|
|
%2 = zext i1 %1 to i32
|
|
|
|
ret i32 %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @sltu(i32 %a, i32 %b) nounwind {
|
|
|
|
; RV32I-LABEL: sltu:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: sltu a0, a0, a1
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: sltu:
|
|
|
|
; RV64I: # %bb.0:
|
2018-11-30 17:56:54 +08:00
|
|
|
; RV64I-NEXT: sext.w a1, a1
|
|
|
|
; RV64I-NEXT: sext.w a0, a0
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
; RV64I-NEXT: sltu a0, a0, a1
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = icmp ult i32 %a, %b
|
|
|
|
%2 = zext i1 %1 to i32
|
|
|
|
ret i32 %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @xor(i32 %a, i32 %b) nounwind {
|
|
|
|
; RV32I-LABEL: xor:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: xor a0, a0, a1
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: xor:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: xor a0, a0, a1
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = xor i32 %a, %b
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @srl(i32 %a, i32 %b) nounwind {
|
|
|
|
; RV32I-LABEL: srl:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: srl a0, a0, a1
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: srl:
|
|
|
|
; RV64I: # %bb.0:
|
2019-01-12 15:32:31 +08:00
|
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = lshr i32 %a, %b
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @sra(i32 %a, i32 %b) nounwind {
|
|
|
|
; RV32I-LABEL: sra:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: sra a0, a0, a1
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: sra:
|
|
|
|
; RV64I: # %bb.0:
|
2019-01-12 15:32:31 +08:00
|
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = ashr i32 %a, %b
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @or(i32 %a, i32 %b) nounwind {
|
|
|
|
; RV32I-LABEL: or:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: or a0, a0, a1
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: or:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: or a0, a0, a1
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = or i32 %a, %b
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @and(i32 %a, i32 %b) nounwind {
|
|
|
|
; RV32I-LABEL: and:
|
2017-12-05 01:18:51 +08:00
|
|
|
; RV32I: # %bb.0:
|
2017-11-09 23:45:42 +08:00
|
|
|
; RV32I-NEXT: and a0, a0, a1
|
2017-12-15 17:47:01 +08:00
|
|
|
; RV32I-NEXT: ret
|
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
As discussed in the RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit
RISC-V has i64 as the only legal integer type. This patch introduces patterns
to support codegen of the new instructions
introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw,
sraiw, ld, sd.
Custom selection code is needed for srliw as SimplifyDemandedBits will remove
lower bits from the mask, meaning the obvious pattern won't work:
def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
This is sufficient to compile and execute all of the GCC torture suite for
RV64I other than those files using frameaddr or returnaddr intrinsics
(LegalizeDAG doesn't know how to promote the operands - a future patch
addresses this).
When promoting i32 sltu/sltiu operands, it would be more efficient to use
sign-extension rather than zero-extension for RV64. A future patch adds a hook
to allow this.
Differential Revision: https://reviews.llvm.org/D52977
llvm-svn: 347973
2018-11-30 17:38:44 +08:00
|
|
|
;
|
|
|
|
; RV64I-LABEL: and:
|
|
|
|
; RV64I: # %bb.0:
|
|
|
|
; RV64I-NEXT: and a0, a0, a1
|
|
|
|
; RV64I-NEXT: ret
|
2017-10-20 05:37:38 +08:00
|
|
|
%1 = and i32 %a, %b
|
|
|
|
ret i32 %1
|
|
|
|
}
|