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llvm-project/clang/test/Driver/arm-cde.c

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[ARM,CDE] Cosmetic changes, additonal driver tests Summary: This is a follow-up patch addressing post-commit comments in https://reviews.llvm.org/D74044: * Add more Clang driver tests (-march=armv8.1m.main and -march=armv8.1m.main+mve.fp) * Clang-format a chunk in ARMAsmParser.cpp * Add a missing copyright header to ARMInstrCDE.td Reviewers: SjoerdMeijer, simon_tatham, dmgreen Reviewed By: SjoerdMeijer Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74732
2020-02-18 18:22:37 +08:00
// RUN: %clang -target arm-none-none-eabi -march=armv8m.main %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-NOCDE,CHECK-NOCDE-V8
// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-NOCDE,CHECK-NOCDE-V81
// CHECK-NOCDE-V8: "-triple" "thumbv8m.main-none-none-eabi"
// CHECK-NOCDE-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
[ARM] Add initial support for Custom Datapath Extension (CDE) Summary: This patch adds assembly-level support for a new Arm M-profile architecture extension, Custom Datapath Extension (CDE). A brief description of the extension is available at https://developer.arm.com/architectures/instruction-sets/custom-instructions The latest specification for CDE is currently a beta release and is available at https://static.docs.arm.com/ddi0607/aa/DDI0607A_a_armv8m_arm_supplement_cde.pdf CDE allows chip vendors to add custom CPU instructions. The CDE instructions re-use the same encoding space as existing coprocessor instructions (such as MRC, MCR, CDP etc.). Each coprocessor in range cp0-cp7 can be configured as either general purpose (GCP) or custom datapath (CDEv1). This configuration is defined by the CPU vendor and is provided to LLVM using 8 subtarget features: cdecp0 ... cdecp7. The semantics of CDE instructions are implementation-defined, but the instructions are guaranteed to be pure (that is, they are stateless, they do not access memory or any registers except their explicit inputs/outputs). CDE requires the CPU to support at least Armv8.0-M mainline architecture. CDE includes 3 sets of instructions: * Instructions that operate on general purpose registers and NZCV flags * Instructions that operate on the S or D register file (require either FP or MVE extension) * Instructions that operate on the Q register file, require MVE The user-facing names that can be specified on the command line are the same as the 8 subtarget feature names. For example: $ clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 tells the compiler that the coprocessors 0 and 3 are configured as CDEv1 and the remaining coprocessors are configured as GCP (which is the default). Reviewers: simon_tatham, ostannard, dmgreen, eli.friedman Reviewed By: simon_tatham Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74044
2020-02-17 23:37:49 +08:00
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp0"
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp1"
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp2"
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp3"
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp4"
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp5"
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp6"
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp7"
[ARM,CDE] Cosmetic changes, additonal driver tests Summary: This is a follow-up patch addressing post-commit comments in https://reviews.llvm.org/D74044: * Add more Clang driver tests (-march=armv8.1m.main and -march=armv8.1m.main+mve.fp) * Clang-format a chunk in ARMAsmParser.cpp * Add a missing copyright header to ARMInstrCDE.td Reviewers: SjoerdMeijer, simon_tatham, dmgreen Reviewed By: SjoerdMeijer Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74732
2020-02-18 18:22:37 +08:00
// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE1,CHECK-CDE1-V8
// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE1,CHECK-CDE1-V81
// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main+mve.fp+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE1,CHECK-CDE1-V81MVE
// CHECK-CDE1-V8: "-triple" "thumbv8m.main-none-none-eabi"
// CHECK-CDE1-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
// CHECK-CDE1-V81MVE: "-triple" "thumbv8.1m.main-none-none-eabi"
// CHECK-CDE1-V81MVE-DAG: "-target-feature" "+mve.fp"
[ARM] Add initial support for Custom Datapath Extension (CDE) Summary: This patch adds assembly-level support for a new Arm M-profile architecture extension, Custom Datapath Extension (CDE). A brief description of the extension is available at https://developer.arm.com/architectures/instruction-sets/custom-instructions The latest specification for CDE is currently a beta release and is available at https://static.docs.arm.com/ddi0607/aa/DDI0607A_a_armv8m_arm_supplement_cde.pdf CDE allows chip vendors to add custom CPU instructions. The CDE instructions re-use the same encoding space as existing coprocessor instructions (such as MRC, MCR, CDP etc.). Each coprocessor in range cp0-cp7 can be configured as either general purpose (GCP) or custom datapath (CDEv1). This configuration is defined by the CPU vendor and is provided to LLVM using 8 subtarget features: cdecp0 ... cdecp7. The semantics of CDE instructions are implementation-defined, but the instructions are guaranteed to be pure (that is, they are stateless, they do not access memory or any registers except their explicit inputs/outputs). CDE requires the CPU to support at least Armv8.0-M mainline architecture. CDE includes 3 sets of instructions: * Instructions that operate on general purpose registers and NZCV flags * Instructions that operate on the S or D register file (require either FP or MVE extension) * Instructions that operate on the Q register file, require MVE The user-facing names that can be specified on the command line are the same as the 8 subtarget feature names. For example: $ clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 tells the compiler that the coprocessors 0 and 3 are configured as CDEv1 and the remaining coprocessors are configured as GCP (which is the default). Reviewers: simon_tatham, ostannard, dmgreen, eli.friedman Reviewed By: simon_tatham Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74044
2020-02-17 23:37:49 +08:00
// CHECK-CDE1-DAG: "-target-feature" "+cdecp0"
// CHECK-CDE1-DAG: "-target-feature" "+cdecp3"
[ARM,CDE] Cosmetic changes, additonal driver tests Summary: This is a follow-up patch addressing post-commit comments in https://reviews.llvm.org/D74044: * Add more Clang driver tests (-march=armv8.1m.main and -march=armv8.1m.main+mve.fp) * Clang-format a chunk in ARMAsmParser.cpp * Add a missing copyright header to ARMInstrCDE.td Reviewers: SjoerdMeijer, simon_tatham, dmgreen Reviewed By: SjoerdMeijer Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74732
2020-02-18 18:22:37 +08:00
// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE2,CHECK-CDE2-V8
// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE2,CHECK-CDE2-V81
// CHECK-CDE2-V8: "-triple" "thumbv8m.main-none-none-eabi"
// CHECK-CDE2-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
[ARM] Add initial support for Custom Datapath Extension (CDE) Summary: This patch adds assembly-level support for a new Arm M-profile architecture extension, Custom Datapath Extension (CDE). A brief description of the extension is available at https://developer.arm.com/architectures/instruction-sets/custom-instructions The latest specification for CDE is currently a beta release and is available at https://static.docs.arm.com/ddi0607/aa/DDI0607A_a_armv8m_arm_supplement_cde.pdf CDE allows chip vendors to add custom CPU instructions. The CDE instructions re-use the same encoding space as existing coprocessor instructions (such as MRC, MCR, CDP etc.). Each coprocessor in range cp0-cp7 can be configured as either general purpose (GCP) or custom datapath (CDEv1). This configuration is defined by the CPU vendor and is provided to LLVM using 8 subtarget features: cdecp0 ... cdecp7. The semantics of CDE instructions are implementation-defined, but the instructions are guaranteed to be pure (that is, they are stateless, they do not access memory or any registers except their explicit inputs/outputs). CDE requires the CPU to support at least Armv8.0-M mainline architecture. CDE includes 3 sets of instructions: * Instructions that operate on general purpose registers and NZCV flags * Instructions that operate on the S or D register file (require either FP or MVE extension) * Instructions that operate on the Q register file, require MVE The user-facing names that can be specified on the command line are the same as the 8 subtarget feature names. For example: $ clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 tells the compiler that the coprocessors 0 and 3 are configured as CDEv1 and the remaining coprocessors are configured as GCP (which is the default). Reviewers: simon_tatham, ostannard, dmgreen, eli.friedman Reviewed By: simon_tatham Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74044
2020-02-17 23:37:49 +08:00
// CHECK-CDE2-NOT: "-target-feature" "+cdecp1"
// CHECK-CDE2-NOT: "-target-feature" "+cdecp2"
// CHECK-CDE2-NOT: "-target-feature" "+cdecp4"
// CHECK-CDE2-NOT: "-target-feature" "+cdecp5"
// CHECK-CDE2-NOT: "-target-feature" "+cdecp6"
// CHECK-CDE2-NOT: "-target-feature" "+cdecp7"