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llvm-project/lld/ELF/Arch/RISCV.cpp

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Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
//===- RISCV.cpp ----------------------------------------------------------===//
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 16:50:56 +08:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
//
//===----------------------------------------------------------------------===//
#include "InputFiles.h"
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-02 01:12:18 +08:00
#include "SyntheticSections.h"
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
#include "Target.h"
using namespace llvm;
using namespace llvm::object;
using namespace llvm::support::endian;
using namespace llvm::ELF;
using namespace lld;
using namespace lld::elf;
namespace {
class RISCV final : public TargetInfo {
public:
[ELF] - Do not fail on R_*_NONE relocations when parsing the debug info. This is https://bugs.llvm.org//show_bug.cgi?id=38919. Currently, LLD may report "unsupported relocation target while parsing debug info" when parsing the debug information. At the same time LLD does that for zeroed R_X86_64_NONE relocations, which obviously has "invalid" targets. The nature of R_*_NONE relocation assumes them should be ignored. This patch teaches LLD to stop reporting the debug information parsing errors for them. Differential revision: https://reviews.llvm.org/D52408 llvm-svn: 343078
2018-09-26 16:11:34 +08:00
RISCV();
Omit "virtual" if overridden. llvm-svn: 345886
2018-11-02 04:08:39 +08:00
uint32_t calcEFlags() const override;
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-02 01:12:18 +08:00
void writeGotHeader(uint8_t *Buf) const override;
void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
void writePltHeader(uint8_t *Buf) const override;
void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
int32_t Index, unsigned RelOff) const override;
RelType getDynRel(RelType Type) const override;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
RelExpr getRelExpr(RelType Type, const Symbol &S,
const uint8_t *Loc) const override;
void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
};
} // end anonymous namespace
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-02 01:12:18 +08:00
enum Op {
ADDI = 0x13,
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x40000033,
};
enum Reg {
X_RA = 1,
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
X_T3 = 28,
};
static uint32_t hi20(uint32_t Val) { return (Val + 0x800) >> 12; }
static uint32_t lo12(uint32_t Val) { return Val & 4095; }
static uint32_t itype(uint32_t Op, uint32_t Rd, uint32_t Rs1, uint32_t Imm) {
return Op | (Rd << 7) | (Rs1 << 15) | (Imm << 20);
}
static uint32_t rtype(uint32_t Op, uint32_t Rd, uint32_t Rs1, uint32_t Rs2) {
return Op | (Rd << 7) | (Rs1 << 15) | (Rs2 << 20);
}
static uint32_t utype(uint32_t Op, uint32_t Rd, uint32_t Imm) {
return Op | (Rd << 7) | (Imm << 12);
}
RISCV::RISCV() {
CopyRel = R_RISCV_COPY;
NoneRel = R_RISCV_NONE;
PltRel = R_RISCV_JUMP_SLOT;
RelativeRel = R_RISCV_RELATIVE;
SymbolicRel = Config->Is64 ? R_RISCV_64 : R_RISCV_32;
GotRel = SymbolicRel;
// .got[0] = _DYNAMIC
GotBaseSymInGotPlt = false;
GotHeaderEntriesNum = 1;
// .got.plt[0] = _dl_runtime_resolve, .got.plt[1] = link_map
GotPltHeaderEntriesNum = 2;
PltEntrySize = 16;
PltHeaderSize = 32;
}
[ELF] - Do not fail on R_*_NONE relocations when parsing the debug info. This is https://bugs.llvm.org//show_bug.cgi?id=38919. Currently, LLD may report "unsupported relocation target while parsing debug info" when parsing the debug information. At the same time LLD does that for zeroed R_X86_64_NONE relocations, which obviously has "invalid" targets. The nature of R_*_NONE relocation assumes them should be ignored. This patch teaches LLD to stop reporting the debug information parsing errors for them. Differential revision: https://reviews.llvm.org/D52408 llvm-svn: 343078
2018-09-26 16:11:34 +08:00
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
static uint32_t getEFlags(InputFile *F) {
if (Config->Is64)
return cast<ObjFile<ELF64LE>>(F)->getObj().getHeader()->e_flags;
Remove `else` after `return`. llvm-svn: 344302
2018-10-12 05:57:52 +08:00
return cast<ObjFile<ELF32LE>>(F)->getObj().getHeader()->e_flags;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
}
uint32_t RISCV::calcEFlags() const {
assert(!ObjectFiles.empty());
uint32_t Target = getEFlags(ObjectFiles.front());
for (InputFile *F : ObjectFiles) {
uint32_t EFlags = getEFlags(F);
if (EFlags & EF_RISCV_RVC)
Target |= EF_RISCV_RVC;
if ((EFlags & EF_RISCV_FLOAT_ABI) != (Target & EF_RISCV_FLOAT_ABI))
error(toString(F) +
": cannot link object files with different floating-point ABI");
if ((EFlags & EF_RISCV_RVE) != (Target & EF_RISCV_RVE))
error(toString(F) +
": cannot link object files with different EF_RISCV_RVE");
}
return Target;
}
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-02 01:12:18 +08:00
void RISCV::writeGotHeader(uint8_t *Buf) const {
if (Config->Is64)
write64le(Buf, Main->Dynamic->getVA());
else
write32le(Buf, Main->Dynamic->getVA());
}
void RISCV::writeGotPlt(uint8_t *Buf, const Symbol &S) const {
if (Config->Is64)
write64le(Buf, In.Plt->getVA());
else
write32le(Buf, In.Plt->getVA());
}
void RISCV::writePltHeader(uint8_t *Buf) const {
// 1: auipc t2, %pcrel_hi(.got.plt)
// sub t1, t1, t3
// l[wd] t3, %pcrel_lo(1b)(t2); t3 = _dl_runtime_resolve
// addi t1, t1, -PltHeaderSize-12; t1 = &.plt[i] - &.plt[0]
// addi t0, t2, %pcrel_lo(1b)
// srli t1, t1, (rv64?1:2); t1 = &.got.plt[i] - &.got.plt[0]
// l[wd] t0, Wordsize(t0); t0 = link_map
// jr t3
uint32_t Offset = In.GotPlt->getVA() - In.Plt->getVA();
uint32_t Load = Config->Is64 ? LD : LW;
write32le(Buf + 0, utype(AUIPC, X_T2, hi20(Offset)));
write32le(Buf + 4, rtype(SUB, X_T1, X_T1, X_T3));
write32le(Buf + 8, itype(Load, X_T3, X_T2, lo12(Offset)));
write32le(Buf + 12, itype(ADDI, X_T1, X_T1, -Target->PltHeaderSize - 12));
write32le(Buf + 16, itype(ADDI, X_T0, X_T2, lo12(Offset)));
write32le(Buf + 20, itype(SRLI, X_T1, X_T1, Config->Is64 ? 1 : 2));
write32le(Buf + 24, itype(Load, X_T0, X_T0, Config->Wordsize));
write32le(Buf + 28, itype(JALR, 0, X_T3, 0));
}
void RISCV::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
uint64_t PltEntryAddr, int32_t Index,
unsigned RelOff) const {
// 1: auipc t3, %pcrel_hi(f@.got.plt)
// l[wd] t3, %pcrel_lo(1b)(t3)
// jalr t1, t3
// nop
uint32_t Offset = GotPltEntryAddr - PltEntryAddr;
write32le(Buf + 0, utype(AUIPC, X_T3, hi20(Offset)));
write32le(Buf + 4, itype(Config->Is64 ? LD : LW, X_T3, X_T3, lo12(Offset)));
write32le(Buf + 8, itype(JALR, X_T1, X_T3, 0));
write32le(Buf + 12, itype(ADDI, 0, 0, 0));
}
RelType RISCV::getDynRel(RelType Type) const {
return Type == Target->SymbolicRel ? Type : R_RISCV_NONE;
}
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
RelExpr RISCV::getRelExpr(const RelType Type, const Symbol &S,
const uint8_t *Loc) const {
switch (Type) {
[ELF][RISCV] Treat R_RISCV_{ADD,SET,SUB}* as link-time constants R_RISCV_{ADD,SET,SUB}* are used for local label computation. Add a new RelExpr member R_RISCV_ADD to represent them. R_RISCV_ADD is treated as a link-time constant because otherwise R_RISCV_{ADD,SET,SUB}* are not allowed in -pie/-shared mode. In glibc Scrt1.o, .rela.eh_frame contains such relocations. Because .eh_frame is not writable, we get this error: ld.lld: error: can't create dynamic relocation R_RISCV_ADD32 against symbol: .L0 in readonly segment; recompil object files with -fPIC or pass '-Wl,-z,notext' to allow text relocations in the output >>> defined in ..../riscv64-linux-gnu/lib/Scrt1.o With D63076 and this patch, I can run -pie/-shared programs linked against glibc. Note llvm-mc cannot currently produce R_RISCV_SET* so they are not tested. Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D63183 llvm-svn: 363128
2019-06-12 15:53:06 +08:00
case R_RISCV_ADD8:
case R_RISCV_ADD16:
case R_RISCV_ADD32:
case R_RISCV_ADD64:
case R_RISCV_SET6:
case R_RISCV_SET8:
case R_RISCV_SET16:
case R_RISCV_SET32:
case R_RISCV_SUB6:
case R_RISCV_SUB8:
case R_RISCV_SUB16:
case R_RISCV_SUB32:
case R_RISCV_SUB64:
return R_RISCV_ADD;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
case R_RISCV_JAL:
case R_RISCV_BRANCH:
case R_RISCV_PCREL_HI20:
case R_RISCV_RVC_BRANCH:
case R_RISCV_RVC_JUMP:
case R_RISCV_32_PCREL:
return R_PC;
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-02 01:12:18 +08:00
case R_RISCV_CALL:
case R_RISCV_CALL_PLT:
return R_PLT_PC;
case R_RISCV_GOT_HI20:
return R_GOT_PC;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
case R_RISCV_RELAX:
case R_RISCV_ALIGN:
return R_HINT;
default:
return R_ABS;
}
}
// Extract bits V[Begin:End], where range is inclusive, and Begin must be < 63.
static uint32_t extractBits(uint64_t V, uint32_t Begin, uint32_t End) {
return (V & ((1ULL << (Begin + 1)) - 1)) >> End;
}
void RISCV::relocateOne(uint8_t *Loc, const RelType Type,
const uint64_t Val) const {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 19:39:23 +08:00
const unsigned Bits = Config->Wordsize * 8;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
switch (Type) {
case R_RISCV_32:
write32le(Loc, Val);
return;
case R_RISCV_64:
write64le(Loc, Val);
return;
case R_RISCV_RVC_BRANCH: {
checkInt(Loc, static_cast<int64_t>(Val) >> 1, 8, Type);
checkAlignment(Loc, Val, 2, Type);
uint16_t Insn = read16le(Loc) & 0xE383;
uint16_t Imm8 = extractBits(Val, 8, 8) << 12;
uint16_t Imm4_3 = extractBits(Val, 4, 3) << 10;
uint16_t Imm7_6 = extractBits(Val, 7, 6) << 5;
uint16_t Imm2_1 = extractBits(Val, 2, 1) << 3;
uint16_t Imm5 = extractBits(Val, 5, 5) << 2;
Insn |= Imm8 | Imm4_3 | Imm7_6 | Imm2_1 | Imm5;
write16le(Loc, Insn);
return;
}
case R_RISCV_RVC_JUMP: {
checkInt(Loc, static_cast<int64_t>(Val) >> 1, 11, Type);
checkAlignment(Loc, Val, 2, Type);
uint16_t Insn = read16le(Loc) & 0xE003;
uint16_t Imm11 = extractBits(Val, 11, 11) << 12;
uint16_t Imm4 = extractBits(Val, 4, 4) << 11;
uint16_t Imm9_8 = extractBits(Val, 9, 8) << 9;
uint16_t Imm10 = extractBits(Val, 10, 10) << 8;
uint16_t Imm6 = extractBits(Val, 6, 6) << 7;
uint16_t Imm7 = extractBits(Val, 7, 7) << 6;
uint16_t Imm3_1 = extractBits(Val, 3, 1) << 3;
uint16_t Imm5 = extractBits(Val, 5, 5) << 2;
Insn |= Imm11 | Imm4 | Imm9_8 | Imm10 | Imm6 | Imm7 | Imm3_1 | Imm5;
write16le(Loc, Insn);
return;
}
case R_RISCV_RVC_LUI: {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 19:39:23 +08:00
int64_t Imm = SignExtend64(Val + 0x800, Bits) >> 12;
checkInt(Loc, Imm, 6, Type);
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
if (Imm == 0) { // `c.lui rd, 0` is illegal, convert to `c.li rd, 0`
write16le(Loc, (read16le(Loc) & 0x0F83) | 0x4000);
} else {
uint16_t Imm17 = extractBits(Val + 0x800, 17, 17) << 12;
uint16_t Imm16_12 = extractBits(Val + 0x800, 16, 12) << 2;
write16le(Loc, (read16le(Loc) & 0xEF83) | Imm17 | Imm16_12);
}
return;
}
case R_RISCV_JAL: {
checkInt(Loc, static_cast<int64_t>(Val) >> 1, 20, Type);
checkAlignment(Loc, Val, 2, Type);
uint32_t Insn = read32le(Loc) & 0xFFF;
uint32_t Imm20 = extractBits(Val, 20, 20) << 31;
uint32_t Imm10_1 = extractBits(Val, 10, 1) << 21;
uint32_t Imm11 = extractBits(Val, 11, 11) << 20;
uint32_t Imm19_12 = extractBits(Val, 19, 12) << 12;
Insn |= Imm20 | Imm10_1 | Imm11 | Imm19_12;
write32le(Loc, Insn);
return;
}
case R_RISCV_BRANCH: {
checkInt(Loc, static_cast<int64_t>(Val) >> 1, 12, Type);
checkAlignment(Loc, Val, 2, Type);
uint32_t Insn = read32le(Loc) & 0x1FFF07F;
uint32_t Imm12 = extractBits(Val, 12, 12) << 31;
uint32_t Imm10_5 = extractBits(Val, 10, 5) << 25;
uint32_t Imm4_1 = extractBits(Val, 4, 1) << 8;
uint32_t Imm11 = extractBits(Val, 11, 11) << 7;
Insn |= Imm12 | Imm10_5 | Imm4_1 | Imm11;
write32le(Loc, Insn);
return;
}
// auipc + jalr pair
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-02 01:12:18 +08:00
case R_RISCV_CALL:
case R_RISCV_CALL_PLT: {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 19:39:23 +08:00
int64_t Hi = SignExtend64(Val + 0x800, Bits) >> 12;
checkInt(Loc, Hi, 20, Type);
if (isInt<20>(Hi)) {
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
relocateOne(Loc, R_RISCV_PCREL_HI20, Val);
relocateOne(Loc + 4, R_RISCV_PCREL_LO12_I, Val);
}
return;
}
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-02 01:12:18 +08:00
case R_RISCV_GOT_HI20:
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
case R_RISCV_PCREL_HI20:
case R_RISCV_HI20: {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 19:39:23 +08:00
uint64_t Hi = Val + 0x800;
checkInt(Loc, SignExtend64(Hi, Bits) >> 12, 20, Type);
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
write32le(Loc, (read32le(Loc) & 0xFFF) | (Hi & 0xFFFFF000));
return;
}
case R_RISCV_PCREL_LO12_I:
case R_RISCV_LO12_I: {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 19:39:23 +08:00
uint64_t Hi = (Val + 0x800) >> 12;
uint64_t Lo = Val - (Hi << 12);
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
write32le(Loc, (read32le(Loc) & 0xFFFFF) | ((Lo & 0xFFF) << 20));
return;
}
case R_RISCV_PCREL_LO12_S:
case R_RISCV_LO12_S: {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 19:39:23 +08:00
uint64_t Hi = (Val + 0x800) >> 12;
uint64_t Lo = Val - (Hi << 12);
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-10 01:59:56 +08:00
uint32_t Imm11_5 = extractBits(Lo, 11, 5) << 25;
uint32_t Imm4_0 = extractBits(Lo, 4, 0) << 7;
write32le(Loc, (read32le(Loc) & 0x1FFF07F) | Imm11_5 | Imm4_0);
return;
}
case R_RISCV_ADD8:
*Loc += Val;
return;
case R_RISCV_ADD16:
write16le(Loc, read16le(Loc) + Val);
return;
case R_RISCV_ADD32:
write32le(Loc, read32le(Loc) + Val);
return;
case R_RISCV_ADD64:
write64le(Loc, read64le(Loc) + Val);
return;
case R_RISCV_SUB6:
*Loc = (*Loc & 0xc0) | (((*Loc & 0x3f) - Val) & 0x3f);
return;
case R_RISCV_SUB8:
*Loc -= Val;
return;
case R_RISCV_SUB16:
write16le(Loc, read16le(Loc) - Val);
return;
case R_RISCV_SUB32:
write32le(Loc, read32le(Loc) - Val);
return;
case R_RISCV_SUB64:
write64le(Loc, read64le(Loc) - Val);
return;
case R_RISCV_SET6:
*Loc = (*Loc & 0xc0) | (Val & 0x3f);
return;
case R_RISCV_SET8:
*Loc = Val;
return;
case R_RISCV_SET16:
write16le(Loc, Val);
return;
case R_RISCV_SET32:
case R_RISCV_32_PCREL:
write32le(Loc, Val);
return;
case R_RISCV_ALIGN:
case R_RISCV_RELAX:
return; // Ignored (for now)
case R_RISCV_NONE:
return; // Do nothing
// These are handled by the dynamic linker
case R_RISCV_RELATIVE:
case R_RISCV_COPY:
case R_RISCV_JUMP_SLOT:
// GP-relative relocations are only produced after relaxation, which
// we don't support for now
case R_RISCV_GPREL_I:
case R_RISCV_GPREL_S:
default:
error(getErrorLocation(Loc) +
"unimplemented relocation: " + toString(Type));
return;
}
}
TargetInfo *elf::getRISCVTargetInfo() {
static RISCV Target;
return &Target;
}