2017-12-19 20:19:08 +08:00
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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2020-07-28 04:42:13 +08:00
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# RUN: llc -run-pass=thumb2-reduce-size %s -o - | FileCheck %s
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2017-12-19 20:19:08 +08:00
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--- |
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8m.main-arm-none-eabi"
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; Function Attrs: norecurse nounwind readnone
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define i32 @test(i32 %x, i32 %y) local_unnamed_addr #0 {
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entry:
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%cmp6 = icmp sgt i32 %y, 0
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br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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%sum.0.lcssa = phi i32 [ 1, %entry ], [ %mul, %for.body ]
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ret i32 %sum.0.lcssa
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for.body: ; preds = %for.body, %for.body.preheader
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%lsr.iv1 = phi i32 [ %lsr.iv.next2, %for.body ], [ %x, %for.body.preheader ]
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%lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ %y, %for.body.preheader ]
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%sum.07 = phi i32 [ %mul, %for.body ], [ 1, %for.body.preheader ]
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%mul = mul nsw i32 %lsr.iv1, %sum.07
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%lsr.iv.next = add i32 %lsr.iv, -1
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%lsr.iv.next2 = add i32 %lsr.iv1, 1
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%exitcond = icmp eq i32 %lsr.iv.next, 0
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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2021-05-25 01:43:40 +08:00
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attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m7" "target-features"="-d32,+dsp,+fp-armv8,-fp64,+hwdiv,+strict-align,+thumb-mode,-crc,-dotprod,-hwdiv-arm,-ras" "unsafe-fp-math"="false" "use-soft-float"="false" }
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2017-12-19 20:19:08 +08:00
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...
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---
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name: test
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tracksRegLiveness: true
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liveins:
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2018-02-01 06:04:26 +08:00
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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2017-12-19 20:19:08 +08:00
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body: |
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; CHECK-LABEL: name: test
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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2018-02-01 06:04:26 +08:00
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; CHECK: liveins: $r0, $r1
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[MIR][ARM] MachineOperand comments
This adds infrastructure to print and parse MIR MachineOperand comments.
The motivation for the ARM backend is to print condition code names instead of
magic constants that are difficult to read (for human beings). For example,
instead of this:
dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg
t2Bcc %bb.4, 0, killed $cpsr
we now print this:
dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg
t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr
This shows that MachineOperand comments are enclosed between /* and */. In this
example, the EOR instruction is not conditionally executed (i.e. it is "always
executed"), which is encoded by the 14 immediate machine operand. Thus, now
this machine operand has /* CC::always */ as a comment. The 0 on the next
conditional branch instruction represents the equal condition code, thus now
this operand has /* CC:eq */ as a comment.
As it is a comment, the MI lexer/parser completely ignores it. The benefit is
that this keeps the change in the lexer extremely minimal and no target
specific parsing needs to be done. The changes on the MIPrinter side are also
minimal, as there is only one target hooks that is used to create the machine
operand comments.
Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 22:19:21 +08:00
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; CHECK: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
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; CHECK: $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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; CHECK: tCMPi8 $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, killed $cpsr
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2017-12-19 20:19:08 +08:00
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; CHECK: bb.1.for.body:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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2018-02-01 06:04:26 +08:00
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; CHECK: liveins: $r0, $r1, $r2
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[MIR][ARM] MachineOperand comments
This adds infrastructure to print and parse MIR MachineOperand comments.
The motivation for the ARM backend is to print condition code names instead of
magic constants that are difficult to read (for human beings). For example,
instead of this:
dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg
t2Bcc %bb.4, 0, killed $cpsr
we now print this:
dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg
t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr
This shows that MachineOperand comments are enclosed between /* and */. In this
example, the EOR instruction is not conditionally executed (i.e. it is "always
executed"), which is encoded by the 14 immediate machine operand. Thus, now
this machine operand has /* CC::always */ as a comment. The 0 on the next
conditional branch instruction represents the equal condition code, thus now
this operand has /* CC:eq */ as a comment.
As it is a comment, the MI lexer/parser completely ignores it. The benefit is
that this keeps the change in the lexer extremely minimal and no target
specific parsing needs to be done. The changes on the MIPrinter side are also
minimal, as there is only one target hooks that is used to create the machine
operand comments.
Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 22:19:21 +08:00
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; CHECK: $r0, dead $cpsr = tMUL $r2, killed $r0, 14 /* CC::al */, $noreg
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; CHECK: $r2, dead $cpsr = tADDi8 killed $r2, 1, 14 /* CC::al */, $noreg
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; CHECK: $r1, $cpsr = tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg
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; CHECK: t2Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
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2017-12-19 20:19:08 +08:00
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; CHECK: bb.2.for.cond.cleanup:
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2018-02-01 06:04:26 +08:00
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; CHECK: liveins: $r0
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[MIR][ARM] MachineOperand comments
This adds infrastructure to print and parse MIR MachineOperand comments.
The motivation for the ARM backend is to print condition code names instead of
magic constants that are difficult to read (for human beings). For example,
instead of this:
dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg
t2Bcc %bb.4, 0, killed $cpsr
we now print this:
dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg
t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr
This shows that MachineOperand comments are enclosed between /* and */. In this
example, the EOR instruction is not conditionally executed (i.e. it is "always
executed"), which is encoded by the 14 immediate machine operand. Thus, now
this machine operand has /* CC::always */ as a comment. The 0 on the next
conditional branch instruction represents the equal condition code, thus now
this operand has /* CC:eq */ as a comment.
As it is a comment, the MI lexer/parser completely ignores it. The benefit is
that this keeps the change in the lexer extremely minimal and no target
specific parsing needs to be done. The changes on the MIPrinter side are also
minimal, as there is only one target hooks that is used to create the machine
operand comments.
Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 22:19:21 +08:00
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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2017-12-19 20:19:08 +08:00
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bb.0.entry:
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successors: %bb.1.for.body, %bb.2.for.cond.cleanup
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2018-02-01 06:04:26 +08:00
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liveins: $r0, $r1
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2017-12-19 20:19:08 +08:00
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2018-02-01 06:04:26 +08:00
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$r2 = tMOVr $r0, 14, _
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$r0 = t2MOVi 1, 14, _, _
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t2CMPri $r1, 1, 14, _, implicit-def $cpsr
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t2Bcc %bb.2.for.cond.cleanup, 11, killed $cpsr
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2017-12-19 20:19:08 +08:00
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bb.1.for.body:
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successors: %bb.2.for.cond.cleanup, %bb.1.for.body
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2018-02-01 06:04:26 +08:00
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liveins: $r0, $r1, $r2
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2017-12-19 20:19:08 +08:00
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2018-02-01 06:04:26 +08:00
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$r0 = t2MUL $r2, killed $r0, 14, _
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$r2 = t2ADDri killed $r2, 1, 14, _, _
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$r1 = t2SUBri killed $r1, 1, 14, _, def $cpsr
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t2Bcc %bb.1.for.body, 1, killed $cpsr
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2017-12-19 20:19:08 +08:00
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bb.2.for.cond.cleanup:
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2018-02-01 06:04:26 +08:00
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liveins: $r0
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2017-12-19 20:19:08 +08:00
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2018-02-01 06:04:26 +08:00
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tBX_RET 14, _, implicit $r0
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2017-12-19 20:19:08 +08:00
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...
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