2019-01-07 20:20:35 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
|
|
|
; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
|
|
|
|
|
; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
|
|
|
|
|
define amdgpu_kernel void @widen_i16_constant_load(i16 addrspace(4)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: widen_i16_constant_load:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_addk_i32 s0, 0x3e7
|
|
|
|
|
; SI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: widen_i16_constant_load:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_addk_i32 s0, 0x3e7
|
|
|
|
|
; VI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s0
|
|
|
|
|
; VI-NEXT: flat_store_short v[0:1], v2
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%load = load i16, i16 addrspace(4)* %arg, align 4
|
|
|
|
|
%add = add i16 %load, 999
|
|
|
|
|
%or = or i16 %add, 4
|
|
|
|
|
store i16 %or, i16 addrspace(1)* null
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @widen_i16_constant_load_zext_i32(i16 addrspace(4)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: widen_i16_constant_load_zext_i32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_and_b32 s0, s0, 0xffff
|
|
|
|
|
; SI-NEXT: s_addk_i32 s0, 0x3e7
|
|
|
|
|
; SI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: widen_i16_constant_load_zext_i32:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_and_b32 s0, s0, 0xffff
|
|
|
|
|
; VI-NEXT: s_addk_i32 s0, 0x3e7
|
|
|
|
|
; VI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s0
|
|
|
|
|
; VI-NEXT: flat_store_dword v[0:1], v2
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%load = load i16, i16 addrspace(4)* %arg, align 4
|
|
|
|
|
%ext = zext i16 %load to i32
|
|
|
|
|
%add = add i32 %ext, 999
|
|
|
|
|
%or = or i32 %add, 4
|
|
|
|
|
store i32 %or, i32 addrspace(1)* null
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @widen_i16_constant_load_sext_i32(i16 addrspace(4)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: widen_i16_constant_load_sext_i32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_sext_i32_i16 s0, s0
|
|
|
|
|
; SI-NEXT: s_addk_i32 s0, 0x3e7
|
|
|
|
|
; SI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: widen_i16_constant_load_sext_i32:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_sext_i32_i16 s0, s0
|
|
|
|
|
; VI-NEXT: s_addk_i32 s0, 0x3e7
|
|
|
|
|
; VI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s0
|
|
|
|
|
; VI-NEXT: flat_store_dword v[0:1], v2
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%load = load i16, i16 addrspace(4)* %arg, align 4
|
|
|
|
|
%ext = sext i16 %load to i32
|
|
|
|
|
%add = add i32 %ext, 999
|
|
|
|
|
%or = or i32 %add, 4
|
|
|
|
|
store i32 %or, i32 addrspace(1)* null
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @widen_i17_constant_load(i17 addrspace(4)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: widen_i17_constant_load:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_add_i32 s0, s0, 34
|
|
|
|
|
; SI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: s_bfe_u32 s0, s0, 0x10010
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 2
|
|
|
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: widen_i17_constant_load:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, 2
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, 0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_add_i32 s0, s0, 34
|
|
|
|
|
; VI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, s0
|
|
|
|
|
; VI-NEXT: s_bfe_u32 s0, s0, 0x10010
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s0
|
|
|
|
|
; VI-NEXT: flat_store_short v[0:1], v4
|
|
|
|
|
; VI-NEXT: flat_store_byte v[2:3], v5
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%load = load i17, i17 addrspace(4)* %arg, align 4
|
|
|
|
|
%add = add i17 %load, 34
|
|
|
|
|
%or = or i17 %add, 4
|
|
|
|
|
store i17 %or, i17 addrspace(1)* null
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @widen_f16_constant_load(half addrspace(4)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: widen_f16_constant_load:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s1, 0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s0, 0
|
|
|
|
|
; SI-NEXT: v_add_f32_e32 v0, 4.0, v0
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: widen_f16_constant_load:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_add_f16_e64 v2, s0, 4.0
|
|
|
|
|
; VI-NEXT: flat_store_short v[0:1], v2
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%load = load half, half addrspace(4)* %arg, align 4
|
|
|
|
|
%add = fadd half %load, 4.0
|
|
|
|
|
store half %add, half addrspace(1)* null
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FIXME: valu usage on VI
|
|
|
|
|
define amdgpu_kernel void @widen_v2i8_constant_load(<2 x i8> addrspace(4)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: widen_v2i8_constant_load:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_and_b32 s1, s0, 0xff00
|
|
|
|
|
; SI-NEXT: s_add_i32 s0, s0, 12
|
|
|
|
|
; SI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; SI-NEXT: s_and_b32 s0, s0, 0xff
|
[DAG] Refactor DAGCombiner::ReassociateOps
Summary:
Extract the logic for doing reassociations
from DAGCombiner::reassociateOps into a helper
function DAGCombiner::reassociateOpsCommutative,
and use that helper to trigger reassociation
on the original operand order, or the commuted
operand order.
Codegen is not identical since the operand order will
be different when doing the reassociations for the
commuted case. That causes some unfortunate churn in
some test cases. Apart from that this should be NFC.
Reviewers: spatel, craig.topper, tstellar
Reviewed By: spatel
Subscribers: dmgreen, dschuff, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, hiraditya, aheejin, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61199
llvm-svn: 359476
2019-04-30 01:50:10 +08:00
|
|
|
; SI-NEXT: s_or_b32 s0, s1, s0
|
[DAGCombiner] Combine OR as ADD when no common bits are set
Summary:
The DAGCombiner is rewriting (canonicalizing) an ISD::ADD
with no common bits set in the operands as an ISD::OR node.
This could sometimes result in "missing out" on some
combines that normally are performed for ADD. To be more
specific this could happen if we already have rewritten an
ADD into OR, and later (after legalizations or combines)
we expose patterns that could have been optimized if we
had seen the OR as an ADD (e.g. reassociations based on ADD).
To make the DAG combiner less sensitive to if ADD or OR is
used for these "no common bits set" ADD/OR operations we
now apply most of the ADD combines also to an OR operation,
when value tracking indicates that the operands have no
common bits set.
Reviewers: spatel, RKSimon, craig.topper, kparzysz
Reviewed By: spatel
Subscribers: arsenm, rampitec, lebedev.ri, jvesely, nhaehnle, hiraditya, javed.absar, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59758
llvm-svn: 358965
2019-04-23 18:01:08 +08:00
|
|
|
; SI-NEXT: s_addk_i32 s0, 0x2c00
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-NEXT: s_or_b32 s0, s0, 0x300
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: widen_v2i8_constant_load:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 44
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 3
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_and_b32 s1, s0, 0xffff
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s0
|
|
|
|
|
; VI-NEXT: s_add_i32 s1, s1, 12
|
|
|
|
|
; VI-NEXT: v_add_u32_sdwa v0, vcc, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
|
|
|
|
|
; VI-NEXT: s_or_b32 s0, s1, 4
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: s_and_b32 s0, s0, 0xff
|
|
|
|
|
; VI-NEXT: v_or_b32_e32 v2, s0, v0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; VI-NEXT: flat_store_short v[0:1], v2
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%load = load <2 x i8>, <2 x i8> addrspace(4)* %arg, align 4
|
|
|
|
|
%add = add <2 x i8> %load, <i8 12, i8 44>
|
|
|
|
|
%or = or <2 x i8> %add, <i8 4, i8 3>
|
|
|
|
|
store <2 x i8> %or, <2 x i8> addrspace(1)* null
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @no_widen_i16_constant_divergent_load(i16 addrspace(4)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: no_widen_i16_constant_divergent_load:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64
|
|
|
|
|
; SI-NEXT: s_mov_b32 s1, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s0, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3e7, v0
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, 4, v0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: no_widen_i16_constant_divergent_load:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
[AMDGPU] Remove dubious logic in bidirectional list scheduler
Summary:
pickNodeBidirectional tried to compare the best top candidate and the
best bottom candidate by examining TopCand.Reason and BotCand.Reason.
This is unsound because, after calling pickNodeFromQueue, Cand.Reason
does not reflect the most important reason why Cand was chosen. Rather
it reflects the most recent reason why it beat some other potential
candidate, which could have been for some low priority tie breaker
reason.
I have seen this cause problems where TopCand is a good candidate, but
because TopCand.Reason is ORDER (which is very low priority) it is
repeatedly ignored in favour of a mediocre BotCand. This is not how
bidirectional scheduling is supposed to work.
To fix this I changed the code to always compare TopCand and BotCand
directly, like the generic implementation of pickNodeBidirectional does.
This removes some uncommented AMDGPU-specific logic; if this logic turns
out to be important then perhaps it could be moved into an override of
tryCandidate instead.
Graphics shader benchmarking on gfx10 shows a lot more positive than
negative effects from this change.
Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB
Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
|
|
|
; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
|
2019-01-07 20:20:35 +08:00
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
[AMDGPU] Remove dubious logic in bidirectional list scheduler
Summary:
pickNodeBidirectional tried to compare the best top candidate and the
best bottom candidate by examining TopCand.Reason and BotCand.Reason.
This is unsound because, after calling pickNodeFromQueue, Cand.Reason
does not reflect the most important reason why Cand was chosen. Rather
it reflects the most recent reason why it beat some other potential
candidate, which could have been for some low priority tie breaker
reason.
I have seen this cause problems where TopCand is a good candidate, but
because TopCand.Reason is ORDER (which is very low priority) it is
repeatedly ignored in favour of a mediocre BotCand. This is not how
bidirectional scheduling is supposed to work.
To fix this I changed the code to always compare TopCand and BotCand
directly, like the generic implementation of pickNodeBidirectional does.
This removes some uncommented AMDGPU-specific logic; if this logic turns
out to be important then perhaps it could be moved into an override of
tryCandidate instead.
Graphics shader benchmarking on gfx10 shows a lot more positive than
negative effects from this change.
Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB
Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s1
|
|
|
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
|
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
|
|
; VI-NEXT: flat_load_ushort v0, v[0:1]
|
2019-01-07 20:20:35 +08:00
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
[AMDGPU] Remove dubious logic in bidirectional list scheduler
Summary:
pickNodeBidirectional tried to compare the best top candidate and the
best bottom candidate by examining TopCand.Reason and BotCand.Reason.
This is unsound because, after calling pickNodeFromQueue, Cand.Reason
does not reflect the most important reason why Cand was chosen. Rather
it reflects the most recent reason why it beat some other potential
candidate, which could have been for some low priority tie breaker
reason.
I have seen this cause problems where TopCand is a good candidate, but
because TopCand.Reason is ORDER (which is very low priority) it is
repeatedly ignored in favour of a mediocre BotCand. This is not how
bidirectional scheduling is supposed to work.
To fix this I changed the code to always compare TopCand and BotCand
directly, like the generic implementation of pickNodeBidirectional does.
This removes some uncommented AMDGPU-specific logic; if this logic turns
out to be important then perhaps it could be moved into an override of
tryCandidate instead.
Graphics shader benchmarking on gfx10 shows a lot more positive than
negative effects from this change.
Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB
Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
|
|
|
; VI-NEXT: v_add_u16_e32 v0, 0x3e7, v0
|
|
|
|
|
; VI-NEXT: v_or_b32_e32 v2, 4, v0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
2019-01-07 20:20:35 +08:00
|
|
|
; VI-NEXT: flat_store_short v[0:1], v2
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
|
|
%tid.ext = zext i32 %tid to i64
|
|
|
|
|
%gep.arg = getelementptr inbounds i16, i16 addrspace(4)* %arg, i64 %tid.ext
|
|
|
|
|
%load = load i16, i16 addrspace(4)* %gep.arg, align 4
|
|
|
|
|
%add = add i16 %load, 999
|
|
|
|
|
%or = or i16 %add, 4
|
|
|
|
|
store i16 %or, i16 addrspace(1)* null
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @widen_i1_constant_load(i1 addrspace(4)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: widen_i1_constant_load:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_and_b32 s0, s0, 1
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: widen_i1_constant_load:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_and_b32 s0, s0, 1
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s0
|
|
|
|
|
; VI-NEXT: flat_store_byte v[0:1], v2
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%load = load i1, i1 addrspace(4)* %arg, align 4
|
|
|
|
|
%and = and i1 %load, true
|
|
|
|
|
store i1 %and, i1 addrspace(1)* null
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @widen_i16_zextload_i64_constant_load(i16 addrspace(4)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: widen_i16_zextload_i64_constant_load:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_and_b32 s0, s0, 0xffff
|
|
|
|
|
; SI-NEXT: s_addk_i32 s0, 0x3e7
|
|
|
|
|
; SI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: widen_i16_zextload_i64_constant_load:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_and_b32 s0, s0, 0xffff
|
|
|
|
|
; VI-NEXT: s_addk_i32 s0, 0x3e7
|
|
|
|
|
; VI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s0
|
|
|
|
|
; VI-NEXT: flat_store_dword v[0:1], v2
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%load = load i16, i16 addrspace(4)* %arg, align 4
|
|
|
|
|
%zext = zext i16 %load to i32
|
|
|
|
|
%add = add i32 %zext, 999
|
|
|
|
|
%or = or i32 %add, 4
|
|
|
|
|
store i32 %or, i32 addrspace(1)* null
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @widen_i1_zext_to_i64_constant_load(i1 addrspace(4)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: widen_i1_zext_to_i64_constant_load:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_and_b32 s0, s0, 1
|
|
|
|
|
; SI-NEXT: s_add_u32 s0, s0, 0x3e7
|
|
|
|
|
; SI-NEXT: s_addc_u32 s1, 0, 0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s1
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: widen_i1_zext_to_i64_constant_load:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_and_b32 s0, s0, 1
|
|
|
|
|
; VI-NEXT: s_add_u32 s0, s0, 0x3e7
|
|
|
|
|
; VI-NEXT: s_addc_u32 s1, 0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s0
|
|
|
|
|
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%load = load i1, i1 addrspace(4)* %arg, align 4
|
|
|
|
|
%zext = zext i1 %load to i64
|
|
|
|
|
%add = add i64 %zext, 999
|
|
|
|
|
store i64 %add, i64 addrspace(1)* null
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @widen_i16_constant32_load(i16 addrspace(6)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: widen_i16_constant32_load:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s1, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_addk_i32 s0, 0x3e7
|
|
|
|
|
; SI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: widen_i16_constant32_load:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_addk_i32 s0, 0x3e7
|
|
|
|
|
; VI-NEXT: s_or_b32 s0, s0, 4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s0
|
|
|
|
|
; VI-NEXT: flat_store_short v[0:1], v2
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%load = load i16, i16 addrspace(6)* %arg, align 4
|
|
|
|
|
%add = add i16 %load, 999
|
|
|
|
|
%or = or i16 %add, 4
|
|
|
|
|
store i16 %or, i16 addrspace(1)* null
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @widen_i16_global_invariant_load(i16 addrspace(1)* %arg) {
|
2019-01-07 20:20:35 +08:00
|
|
|
; SI-LABEL: widen_i16_global_invariant_load:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_addk_i32 s0, 0x3e7
|
|
|
|
|
; SI-NEXT: s_or_b32 s0, s0, 1
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: widen_i16_global_invariant_load:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_addk_i32 s0, 0x3e7
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; VI-NEXT: s_or_b32 s0, s0, 1
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; VI-NEXT: v_mov_b32_e32 v2, s0
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; VI-NEXT: flat_store_short v[0:1], v2
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; VI-NEXT: s_endpgm
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AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
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%load = load i16, i16 addrspace(1)* %arg, align 4, !invariant.load !0
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%add = add i16 %load, 999
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%or = or i16 %add, 1
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store i16 %or, i16 addrspace(1)* null
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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!0 = !{}
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