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llvm-project/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll

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AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefix=CI %s
R600/SI: Custom lower fround This fixes it for SI. It also removes the pattern used previously for Evergreen for f32. I'm not sure if the the new R600 output is better or not, but it uses 1 fewer instructions if BFI is available. llvm-svn: 226682
2015-01-22 02:18:25 +08:00
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @round_f64(double addrspace(1)* %out, double %x) #0 {
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-LABEL: round_f64:
; SI: ; %bb.0:
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: s_mov_b32 s6, -1
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_mov_b32 s3, 0xfffff
; SI-NEXT: s_mov_b32 s2, s6
; SI-NEXT: v_mov_b32_e32 v4, 0x3ff00000
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
; SI-NEXT: s_add_i32 s5, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s5
; SI-NEXT: s_andn2_b64 s[2:3], s[10:11], s[0:1]
; SI-NEXT: s_and_b32 s0, s11, 0x80000000
; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: v_mov_b32_e32 v0, s3
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s5, 0
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s5, 51
; SI-NEXT: v_mov_b32_e32 v1, s11
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v2, s10
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
; SI-NEXT: s_brev_b32 s0, -2
; SI-NEXT: v_mov_b32_e32 v5, s11
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
; SI-NEXT: v_bfi_b32 v4, s0, v4, v5
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s4, s8
; SI-NEXT: s_mov_b32 s5, s9
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; CI-LABEL: round_f64:
; CI: ; %bb.0:
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_brev_b32 s8, -2
; CI-NEXT: v_mov_b32_e32 v4, 0x3ff00000
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, -1
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_trunc_f64_e32 v[0:1], s[6:7]
; CI-NEXT: v_mov_b32_e32 v5, s7
; CI-NEXT: v_add_f64 v[2:3], s[6:7], -v[0:1]
; CI-NEXT: v_bfi_b32 v4, s8, v4, v5
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
; CI-NEXT: v_mov_b32_e32 v2, 0
; CI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; CI-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
; CI-NEXT: s_mov_b32 s0, s4
; CI-NEXT: s_mov_b32 s1, s5
; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: s_endpgm
R600/SI: Custom lower fround This fixes it for SI. It also removes the pattern used previously for Evergreen for f32. I'm not sure if the the new R600 output is better or not, but it uses 1 fewer instructions if BFI is available. llvm-svn: 226682
2015-01-22 02:18:25 +08:00
%result = call double @llvm.round.f64(double %x) #1
store double %result, double addrspace(1)* %out
ret void
}
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @v_round_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-LABEL: v_round_f64:
; SI: ; %bb.0:
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, 0
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_mov_b64 s[0:1], s[6:7]
; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_movk_i32 s9, 0xfc01
; SI-NEXT: s_mov_b32 s7, 0xfffff
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_brev_b32 s8, -2
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_mov_b32_e32 v8, 0x3ff00000
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_bfe_u32 v4, v3, 20, 11
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_add_i32_e32 v6, vcc, s9, v4
; SI-NEXT: v_lshr_b64 v[4:5], s[6:7], v6
; SI-NEXT: v_and_b32_e32 v7, 0x80000000, v3
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_not_b32_e32 v4, v4
; SI-NEXT: v_not_b32_e32 v5, v5
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_and_b32_e32 v5, v3, v5
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v6
; SI-NEXT: v_and_b32_e32 v4, v2, v4
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 51, v6
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
; SI-NEXT: v_add_f64 v[6:7], v[2:3], -v[4:5]
; SI-NEXT: v_bfi_b32 v2, s8, v8, v3
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]
; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: s_endpgm
;
; CI-LABEL: v_round_f64:
; CI: ; %bb.0:
[AMDGPU] Remove dubious logic in bidirectional list scheduler Summary: pickNodeBidirectional tried to compare the best top candidate and the best bottom candidate by examining TopCand.Reason and BotCand.Reason. This is unsound because, after calling pickNodeFromQueue, Cand.Reason does not reflect the most important reason why Cand was chosen. Rather it reflects the most recent reason why it beat some other potential candidate, which could have been for some low priority tie breaker reason. I have seen this cause problems where TopCand is a good candidate, but because TopCand.Reason is ORDER (which is very low priority) it is repeatedly ignored in favour of a mediocre BotCand. This is not how bidirectional scheduling is supposed to work. To fix this I changed the code to always compare TopCand and BotCand directly, like the generic implementation of pickNodeBidirectional does. This removes some uncommented AMDGPU-specific logic; if this logic turns out to be important then perhaps it could be moved into an override of tryCandidate instead. Graphics shader benchmarking on gfx10 shows a lot more positive than negative effects from this change. Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Remove dubious logic in bidirectional list scheduler Summary: pickNodeBidirectional tried to compare the best top candidate and the best bottom candidate by examining TopCand.Reason and BotCand.Reason. This is unsound because, after calling pickNodeFromQueue, Cand.Reason does not reflect the most important reason why Cand was chosen. Rather it reflects the most recent reason why it beat some other potential candidate, which could have been for some low priority tie breaker reason. I have seen this cause problems where TopCand is a good candidate, but because TopCand.Reason is ORDER (which is very low priority) it is repeatedly ignored in favour of a mediocre BotCand. This is not how bidirectional scheduling is supposed to work. To fix this I changed the code to always compare TopCand and BotCand directly, like the generic implementation of pickNodeBidirectional does. This removes some uncommented AMDGPU-specific logic; if this logic turns out to be important then perhaps it could be moved into an override of tryCandidate instead. Graphics shader benchmarking on gfx10 shows a lot more positive than negative effects from this change. Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_brev_b32 s6, -2
; CI-NEXT: v_mov_b32_e32 v8, 0x3ff00000
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: s_waitcnt vmcnt(0)
[AMDGPU] Remove dubious logic in bidirectional list scheduler Summary: pickNodeBidirectional tried to compare the best top candidate and the best bottom candidate by examining TopCand.Reason and BotCand.Reason. This is unsound because, after calling pickNodeFromQueue, Cand.Reason does not reflect the most important reason why Cand was chosen. Rather it reflects the most recent reason why it beat some other potential candidate, which could have been for some low priority tie breaker reason. I have seen this cause problems where TopCand is a good candidate, but because TopCand.Reason is ORDER (which is very low priority) it is repeatedly ignored in favour of a mediocre BotCand. This is not how bidirectional scheduling is supposed to work. To fix this I changed the code to always compare TopCand and BotCand directly, like the generic implementation of pickNodeBidirectional does. This removes some uncommented AMDGPU-specific logic; if this logic turns out to be important then perhaps it could be moved into an override of tryCandidate instead. Graphics shader benchmarking on gfx10 shows a lot more positive than negative effects from this change. Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68338
2019-10-07 22:33:59 +08:00
; CI-NEXT: v_trunc_f64_e32 v[4:5], v[2:3]
; CI-NEXT: v_add_f64 v[6:7], v[2:3], -v[4:5]
; CI-NEXT: v_bfi_b32 v2, s6, v8, v3
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc
; CI-NEXT: v_mov_b32_e32 v2, 0
; CI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]
; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: s_endpgm
AMDGPU: Remove some old intrinsic uses from tests llvm-svn: 260493
2016-02-11 14:02:01 +08:00
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction One of several parallel first steps to remove the target type of pointers, replacing them with a single opaque pointer type. This adds an explicit type parameter to the gep instruction so that when the first parameter becomes an opaque pointer type, the type to gep through is still available to the instructions. * This doesn't modify gep operators, only instructions (operators will be handled separately) * Textual IR changes only. Bitcode (including upgrade) and changing the in-memory representation will be in separate changes. * geps of vectors are transformed as: getelementptr <4 x float*> %x, ... ->getelementptr float, <4 x float*> %x, ... Then, once the opaque pointer type is introduced, this will ultimately look like: getelementptr float, <4 x ptr> %x with the unambiguous interpretation that it is a vector of pointers to float. * address spaces remain on the pointer, not the type: getelementptr float addrspace(1)* %x ->getelementptr float, float addrspace(1)* %x Then, eventually: getelementptr float, ptr addrspace(1) %x Importantly, the massive amount of test case churn has been automated by same crappy python code. I had to manually update a few test cases that wouldn't fit the script's model (r228970,r229196,r229197,r229198). The python script just massages stdin and writes the result to stdout, I then wrapped that in a shell script to handle replacing files, then using the usual find+xargs to migrate all the files. update.py: import fileinput import sys import re ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") def conv(match, line): if not match: return line line = match.groups()[0] if len(match.groups()[5]) == 0: line += match.groups()[2] line += match.groups()[3] line += ", " line += match.groups()[1] line += "\n" return line for line in sys.stdin: if line.find("getelementptr ") == line.find("getelementptr inbounds"): if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("): line = conv(re.match(ibrep, line), line) elif line.find("getelementptr ") != line.find("getelementptr ("): line = conv(re.match(normrep, line), line) sys.stdout.write(line) apply.sh: for name in "$@" do python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name" rm -f "$name.tmp" done The actual commands: From llvm/src: find test/ -name *.ll | xargs ./apply.sh From llvm/src/tools/clang: find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}" From llvm/src/tools/polly: find test/ -name *.ll | xargs ./apply.sh After that, check-all (with llvm, clang, clang-tools-extra, lld, compiler-rt, and polly all checked out). The extra 'rm' in the apply.sh script is due to a few files in clang's test suite using interesting unicode stuff that my python script was throwing exceptions on. None of those files needed to be migrated, so it seemed sufficient to ignore those cases. Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7636 llvm-svn: 230786
2015-02-28 03:29:02 +08:00
%gep = getelementptr double, double addrspace(1)* %in, i32 %tid
%out.gep = getelementptr double, double addrspace(1)* %out, i32 %tid
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load double, double addrspace(1)* %gep
R600/SI: Custom lower fround This fixes it for SI. It also removes the pattern used previously for Evergreen for f32. I'm not sure if the the new R600 output is better or not, but it uses 1 fewer instructions if BFI is available. llvm-svn: 226682
2015-01-22 02:18:25 +08:00
%result = call double @llvm.round.f64(double %x) #1
store double %result, double addrspace(1)* %out.gep
ret void
}
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @round_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) #0 {
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-LABEL: round_v2f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s6, -1
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_movk_i32 s7, 0xfc01
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: s_mov_b32 s3, 0xfffff
; SI-NEXT: s_mov_b32 s2, s6
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_add_i32 s14, s0, s7
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s14
; SI-NEXT: s_brev_b32 s15, 1
; SI-NEXT: s_andn2_b64 s[12:13], s[10:11], s[0:1]
; SI-NEXT: s_and_b32 s0, s11, s15
; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: v_mov_b32_e32 v0, s13
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s14, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v1, s11
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s14, 51
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
; SI-NEXT: v_mov_b32_e32 v0, s12
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v2, s10
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: s_bfe_u32 s0, s9, 0xb0014
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_add_i32 s7, s0, s7
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
; SI-NEXT: s_brev_b32 s10, -2
; SI-NEXT: v_mov_b32_e32 v6, 0x3ff00000
; SI-NEXT: v_mov_b32_e32 v4, s11
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s7
; SI-NEXT: v_bfi_b32 v4, s10, v6, v4
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_andn2_b64 s[2:3], s[8:9], s[0:1]
; SI-NEXT: s_and_b32 s0, s9, s15
; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: v_mov_b32_e32 v0, s3
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s7, 0
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s7, 51
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_add_f64 v[4:5], s[8:9], -v[0:1]
; SI-NEXT: v_mov_b32_e32 v7, s9
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
; SI-NEXT: v_bfi_b32 v6, s10, v6, v7
; SI-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[4:5]
; SI-NEXT: s_mov_b32 s7, 0xf000
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; CI-LABEL: round_v2f64:
; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
; CI-NEXT: s_brev_b32 s6, -2
; CI-NEXT: v_mov_b32_e32 v6, 0x3ff00000
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: s_mov_b32 s7, 0xf000
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_trunc_f64_e32 v[0:1], s[2:3]
; CI-NEXT: v_mov_b32_e32 v4, s3
; CI-NEXT: v_add_f64 v[2:3], s[2:3], -v[0:1]
; CI-NEXT: v_bfi_b32 v4, s6, v6, v4
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
; CI-NEXT: v_mov_b32_e32 v2, 0
; CI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; CI-NEXT: v_trunc_f64_e32 v[4:5], s[0:1]
; CI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
; CI-NEXT: v_add_f64 v[0:1], s[0:1], -v[4:5]
; CI-NEXT: v_mov_b32_e32 v7, s1
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
; CI-NEXT: v_bfi_b32 v6, s6, v6, v7
; CI-NEXT: v_cndmask_b32_e32 v1, 0, v6, vcc
; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: v_add_f64 v[0:1], v[4:5], v[0:1]
; CI-NEXT: s_mov_b32 s6, -1
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; CI-NEXT: s_endpgm
R600/SI: Custom lower fround This fixes it for SI. It also removes the pattern used previously for Evergreen for f32. I'm not sure if the the new R600 output is better or not, but it uses 1 fewer instructions if BFI is available. llvm-svn: 226682
2015-01-22 02:18:25 +08:00
%result = call <2 x double> @llvm.round.v2f64(<2 x double> %in) #1
store <2 x double> %result, <2 x double> addrspace(1)* %out
ret void
}
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @round_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) #0 {
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-LABEL: round_v4f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0x11
; SI-NEXT: s_mov_b32 s6, -1
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_movk_i32 s18, 0xfc01
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: s_mov_b32 s3, 0xfffff
; SI-NEXT: s_mov_b32 s2, s6
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_add_i32 s19, s0, s18
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s19
; SI-NEXT: s_brev_b32 s20, 1
; SI-NEXT: s_andn2_b64 s[16:17], s[10:11], s[0:1]
; SI-NEXT: s_and_b32 s0, s11, s20
; SI-NEXT: v_mov_b32_e32 v1, s0
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_mov_b32_e32 v0, s17
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s19, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v1, s11
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s19, 51
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v2, s10
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
; SI-NEXT: s_bfe_u32 s0, s9, 0xb0014
; SI-NEXT: s_add_i32 s17, s0, s18
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
; SI-NEXT: s_brev_b32 s16, -2
; SI-NEXT: v_mov_b32_e32 v12, 0x3ff00000
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v4, s11
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_bfi_b32 v4, s16, v12, v4
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s17
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_andn2_b64 s[10:11], s[8:9], s[0:1]
; SI-NEXT: s_and_b32 s0, s9, s20
; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s17, 0
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v1, s9
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s17, 51
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
; SI-NEXT: v_add_f64 v[4:5], s[8:9], -v[0:1]
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: s_bfe_u32 s0, s15, 0xb0014
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_add_i32 s10, s0, s18
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v6, s9
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s10
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
; SI-NEXT: s_andn2_b64 s[8:9], s[14:15], s[0:1]
; SI-NEXT: v_bfi_b32 v6, s16, v12, v6
; SI-NEXT: s_and_b32 s0, s15, s20
; SI-NEXT: v_cndmask_b32_e32 v9, 0, v6, vcc
; SI-NEXT: v_mov_b32_e32 v5, s0
; SI-NEXT: v_mov_b32_e32 v4, s9
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s10, 0
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v5, s15
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s10, 51
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[0:1]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; SI-NEXT: v_mov_b32_e32 v6, s14
; SI-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1]
; SI-NEXT: v_add_f64 v[6:7], s[14:15], -v[4:5]
; SI-NEXT: s_bfe_u32 s0, s13, 0xb0014
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v10, s15
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_add_i32 s8, s0, s18
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s8
; SI-NEXT: v_bfi_b32 v10, s16, v12, v10
; SI-NEXT: v_cndmask_b32_e32 v7, 0, v10, vcc
; SI-NEXT: v_mov_b32_e32 v6, 0
; SI-NEXT: s_andn2_b64 s[2:3], s[12:13], s[0:1]
; SI-NEXT: s_and_b32 s0, s13, s20
; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7]
; SI-NEXT: v_mov_b32_e32 v5, s0
; SI-NEXT: v_mov_b32_e32 v4, s3
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s8, 0
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v5, s13
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s8, 51
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[0:1]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v4, s2
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; SI-NEXT: v_mov_b32_e32 v10, s12
; SI-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[0:1]
; SI-NEXT: v_add_f64 v[10:11], s[12:13], -v[4:5]
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v13, s13
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[10:11]|, 0.5
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_bfi_b32 v12, s16, v12, v13
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cndmask_b32_e32 v11, 0, v12, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v10, 0
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v8, 0
; SI-NEXT: v_add_f64 v[4:5], v[4:5], v[10:11]
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: s_mov_b32 s7, 0xf000
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[8:9]
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; CI-LABEL: round_v4f64:
; CI: ; %bb.0:
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; CI-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0x11
; CI-NEXT: s_brev_b32 s2, -2
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_mov_b32_e32 v12, 0x3ff00000
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
; CI-NEXT: s_mov_b32 s7, 0xf000
; CI-NEXT: s_mov_b32 s6, -1
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: s_waitcnt lgkmcnt(0)
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
; CI-NEXT: v_trunc_f64_e32 v[0:1], s[10:11]
; CI-NEXT: v_mov_b32_e32 v4, s11
; CI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
; CI-NEXT: v_bfi_b32 v4, s2, v12, v4
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
; CI-NEXT: v_trunc_f64_e32 v[8:9], s[8:9]
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; CI-NEXT: v_mov_b32_e32 v2, 0
; CI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
; CI-NEXT: v_add_f64 v[0:1], s[8:9], -v[8:9]
; CI-NEXT: v_mov_b32_e32 v4, s9
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
; CI-NEXT: v_bfi_b32 v4, s2, v12, v4
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
; CI-NEXT: v_trunc_f64_e32 v[4:5], s[14:15]
; CI-NEXT: v_mov_b32_e32 v10, s15
; CI-NEXT: v_add_f64 v[6:7], s[14:15], -v[4:5]
; CI-NEXT: v_bfi_b32 v10, s2, v12, v10
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
; CI-NEXT: v_mov_b32_e32 v6, 0
; CI-NEXT: v_cndmask_b32_e32 v7, 0, v10, vcc
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
; CI-NEXT: v_trunc_f64_e32 v[10:11], s[12:13]
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7]
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
; CI-NEXT: v_add_f64 v[4:5], s[12:13], -v[10:11]
; CI-NEXT: v_mov_b32_e32 v13, s13
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
; CI-NEXT: v_bfi_b32 v12, s2, v12, v13
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_cndmask_b32_e32 v5, 0, v12, vcc
; CI-NEXT: v_mov_b32_e32 v4, 0
[AMDGPU] Bundle loads before post-RA scheduler We are relying on atrificial DAG edges inserted by the MemOpClusterMutation to keep loads and stores together in the post-RA scheduler. This does not work all the time since it allows to schedule a completely independent instruction in the middle of the cluster. Removed the DAG mutation and added pass to bundle already clustered instructions. These bundles are unpacked before the memory legalizer because it does not work with bundles but also because it allows to insert waitcounts in the middle of a store cluster. Removing artificial edges also allows a more relaxed scheduling. Differential Revision: https://reviews.llvm.org/D72737
2020-01-14 06:54:17 +08:00
; CI-NEXT: v_mov_b32_e32 v0, 0
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_add_f64 v[4:5], v[10:11], v[4:5]
; CI-NEXT: v_add_f64 v[0:1], v[8:9], v[0:1]
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
; CI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: s_endpgm
R600/SI: Custom lower fround This fixes it for SI. It also removes the pattern used previously for Evergreen for f32. I'm not sure if the the new R600 output is better or not, but it uses 1 fewer instructions if BFI is available. llvm-svn: 226682
2015-01-22 02:18:25 +08:00
%result = call <4 x double> @llvm.round.v4f64(<4 x double> %in) #1
store <4 x double> %result, <4 x double> addrspace(1)* %out
ret void
}
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @round_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %in) #0 {
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-LABEL: round_v8f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx16 s[8:23], s[0:1], 0x19
; SI-NEXT: s_mov_b32 s6, -1
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_movk_i32 s7, 0xfc01
; SI-NEXT: s_mov_b32 s5, 0xfffff
; SI-NEXT: s_mov_b32 s4, s6
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_bfe_u32 s2, s11, 0xb0014
; SI-NEXT: s_add_i32 s26, s2, s7
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s26
; SI-NEXT: s_brev_b32 s27, 1
; SI-NEXT: s_andn2_b64 s[24:25], s[10:11], s[2:3]
; SI-NEXT: s_and_b32 s2, s11, s27
; SI-NEXT: v_mov_b32_e32 v1, s2
; SI-NEXT: v_mov_b32_e32 v0, s25
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s26, 0
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v1, s11
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s26, 51
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[2:3]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v0, s24
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v2, s10
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3]
; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
; SI-NEXT: s_bfe_u32 s2, s9, 0xb0014
; SI-NEXT: s_add_i32 s25, s2, s7
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
; SI-NEXT: s_brev_b32 s24, -2
; SI-NEXT: v_mov_b32_e32 v18, 0x3ff00000
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v4, s11
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_bfi_b32 v4, s24, v18, v4
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s25
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_andn2_b64 s[10:11], s[8:9], s[2:3]
; SI-NEXT: s_and_b32 s2, s9, s27
; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
; SI-NEXT: v_mov_b32_e32 v1, s2
; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s25, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v1, s9
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s25, 51
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[2:3]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[2:3]
; SI-NEXT: v_add_f64 v[4:5], s[8:9], -v[0:1]
; SI-NEXT: s_bfe_u32 s2, s15, 0xb0014
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v6, s9
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_add_i32 s10, s2, s7
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
; SI-NEXT: v_bfi_b32 v6, s24, v18, v6
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s10
; SI-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: s_andn2_b64 s[8:9], s[14:15], s[2:3]
; SI-NEXT: s_and_b32 s2, s15, s27
; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[4:5]
; SI-NEXT: v_mov_b32_e32 v5, s2
; SI-NEXT: v_mov_b32_e32 v4, s9
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s10, 0
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v5, s15
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s10, 51
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[2:3]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; SI-NEXT: v_mov_b32_e32 v6, s14
; SI-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[2:3]
; SI-NEXT: v_add_f64 v[6:7], s[14:15], -v[4:5]
; SI-NEXT: s_bfe_u32 s2, s13, 0xb0014
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v8, s15
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_add_i32 s10, s2, s7
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
; SI-NEXT: v_bfi_b32 v8, s24, v18, v8
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s10
; SI-NEXT: v_cndmask_b32_e32 v7, 0, v8, vcc
; SI-NEXT: v_mov_b32_e32 v6, 0
; SI-NEXT: s_andn2_b64 s[8:9], s[12:13], s[2:3]
; SI-NEXT: s_and_b32 s2, s13, s27
; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7]
; SI-NEXT: v_mov_b32_e32 v5, s2
; SI-NEXT: v_mov_b32_e32 v4, s9
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s10, 0
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v5, s13
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s10, 51
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[2:3]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_mov_b32_e32 v8, s12
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cndmask_b32_e64 v4, v4, v8, s[2:3]
; SI-NEXT: v_add_f64 v[8:9], s[12:13], -v[4:5]
; SI-NEXT: s_bfe_u32 s2, s19, 0xb0014
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v10, s13
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_add_i32 s10, s2, s7
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[8:9]|, 0.5
; SI-NEXT: v_bfi_b32 v10, s24, v18, v10
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s10
; SI-NEXT: v_cndmask_b32_e32 v9, 0, v10, vcc
; SI-NEXT: v_mov_b32_e32 v8, 0
; SI-NEXT: s_andn2_b64 s[8:9], s[18:19], s[2:3]
; SI-NEXT: s_and_b32 s2, s19, s27
; SI-NEXT: v_add_f64 v[4:5], v[4:5], v[8:9]
; SI-NEXT: v_mov_b32_e32 v9, s2
; SI-NEXT: v_mov_b32_e32 v8, s9
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s10, 0
; SI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v9, s19
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s10, 51
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_cndmask_b32_e64 v13, v8, v9, s[2:3]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v8, s8
; SI-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_mov_b32_e32 v9, s18
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cndmask_b32_e64 v12, v8, v9, s[2:3]
; SI-NEXT: s_bfe_u32 s2, s17, 0xb0014
; SI-NEXT: s_add_i32 s12, s2, s7
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s12
; SI-NEXT: s_andn2_b64 s[8:9], s[16:17], s[2:3]
; SI-NEXT: s_bfe_u32 s2, s23, 0xb0014
; SI-NEXT: s_add_i32 s14, s2, s7
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s14
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v8, s19
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: s_andn2_b64 s[10:11], s[22:23], s[2:3]
; SI-NEXT: s_and_b32 s2, s23, s27
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_bfi_b32 v19, s24, v18, v8
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v9, s2
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_mov_b32_e32 v8, s11
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s14, 0
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v9, s23
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s14, 51
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_cndmask_b32_e64 v9, v8, v9, s[2:3]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v8, s10
; SI-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
; SI-NEXT: v_mov_b32_e32 v10, s22
; SI-NEXT: v_cndmask_b32_e64 v8, v8, v10, s[2:3]
; SI-NEXT: s_bfe_u32 s2, s21, 0xb0014
; SI-NEXT: s_add_i32 s7, s2, s7
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s7
; SI-NEXT: s_andn2_b64 s[4:5], s[20:21], s[2:3]
; SI-NEXT: s_and_b32 s2, s21, s27
; SI-NEXT: v_mov_b32_e32 v11, s2
; SI-NEXT: v_mov_b32_e32 v10, s5
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s7, 0
; SI-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s7, 51
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v11, s21
; SI-NEXT: v_cndmask_b32_e64 v15, v10, v11, s[2:3]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v10, s4
; SI-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc
; SI-NEXT: v_mov_b32_e32 v11, s20
; SI-NEXT: v_cndmask_b32_e64 v14, v10, v11, s[2:3]
; SI-NEXT: v_add_f64 v[10:11], s[20:21], -v[14:15]
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v17, s23
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[10:11]|, 0.5
; SI-NEXT: v_add_f64 v[10:11], s[22:23], -v[8:9]
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v16, s21
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_ge_f64_e64 s[2:3], |v[10:11]|, 0.5
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_bfi_b32 v17, s24, v18, v17
; SI-NEXT: v_cndmask_b32_e64 v11, 0, v17, s[2:3]
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v10, 0
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_bfi_b32 v16, s24, v18, v16
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_add_f64 v[10:11], v[8:9], v[10:11]
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_cndmask_b32_e32 v9, 0, v16, vcc
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_mov_b32_e32 v8, 0
; SI-NEXT: s_and_b32 s13, s17, s27
; SI-NEXT: v_add_f64 v[8:9], v[14:15], v[8:9]
; SI-NEXT: v_mov_b32_e32 v14, s9
; SI-NEXT: v_mov_b32_e32 v15, s13
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s12, 0
; SI-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc
; SI-NEXT: v_mov_b32_e32 v15, s17
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s12, 51
; SI-NEXT: v_cndmask_b32_e64 v17, v14, v15, s[2:3]
; SI-NEXT: v_mov_b32_e32 v14, s8
; SI-NEXT: v_cndmask_b32_e64 v14, v14, 0, vcc
[AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal We can produce such vectors in the Promote Alloca pass, but we are unable to use movrel to operate it and lower via scratch. Making it legal makes SI_INDIRECT patterns work. There is more work to do in subsequent changes: 1. We initialize m0 twice to access each dword. It shall be possible to only do it once and increment base register number instead. 2. We also need v16i64/v16f64 but these first need to be added to tablegen. Differential Revision: https://reviews.llvm.org/D79808
2020-05-13 05:18:53 +08:00
; SI-NEXT: v_mov_b32_e32 v15, s16
; SI-NEXT: v_cndmask_b32_e64 v16, v14, v15, s[2:3]
; SI-NEXT: v_mov_b32_e32 v14, s17
; SI-NEXT: v_bfi_b32 v18, s24, v18, v14
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_add_f64 v[14:15], s[16:17], -v[16:17]
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5
; SI-NEXT: v_add_f64 v[14:15], s[18:19], -v[12:13]
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: s_mov_b32 s7, 0xf000
AMDGPU: Drop special case f64 fround lowering The result is better if ftrunc is emitted and separately legalized when unavailable.
2019-12-25 00:22:18 +08:00
; SI-NEXT: v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5
; SI-NEXT: v_mov_b32_e32 v14, 0
; SI-NEXT: v_cndmask_b32_e64 v15, 0, v19, s[0:1]
; SI-NEXT: v_add_f64 v[14:15], v[12:13], v[14:15]
; SI-NEXT: v_cndmask_b32_e32 v13, 0, v18, vcc
; SI-NEXT: v_mov_b32_e32 v12, 0
; SI-NEXT: v_add_f64 v[12:13], v[16:17], v[12:13]
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:48
; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:32
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; CI-LABEL: round_v8f64:
; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; CI-NEXT: s_load_dwordx16 s[8:23], s[0:1], 0x19
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_mov_b32_e32 v16, 0x3ff00000
; CI-NEXT: s_mov_b32 s7, 0xf000
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: s_mov_b32 s6, -1
; CI-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_trunc_f64_e32 v[0:1], s[10:11]
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: v_mov_b32_e32 v4, s11
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
; CI-NEXT: v_bfi_b32 v4, s2, v16, v4
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
; CI-NEXT: v_mov_b32_e32 v2, 0
; CI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; CI-NEXT: v_trunc_f64_e32 v[4:5], s[8:9]
; CI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
; CI-NEXT: v_add_f64 v[0:1], s[8:9], -v[4:5]
; CI-NEXT: v_mov_b32_e32 v6, s9
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
; CI-NEXT: v_bfi_b32 v6, s2, v16, v6
; CI-NEXT: v_cndmask_b32_e32 v1, 0, v6, vcc
; CI-NEXT: v_trunc_f64_e32 v[6:7], s[14:15]
; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: v_add_f64 v[0:1], v[4:5], v[0:1]
; CI-NEXT: v_add_f64 v[4:5], s[14:15], -v[6:7]
; CI-NEXT: v_mov_b32_e32 v8, s15
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
; CI-NEXT: v_bfi_b32 v8, s2, v16, v8
; CI-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
; CI-NEXT: v_trunc_f64_e32 v[8:9], s[12:13]
; CI-NEXT: v_mov_b32_e32 v4, 0
; CI-NEXT: v_add_f64 v[6:7], v[6:7], v[4:5]
; CI-NEXT: v_add_f64 v[4:5], s[12:13], -v[8:9]
; CI-NEXT: v_mov_b32_e32 v10, s13
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
; CI-NEXT: v_bfi_b32 v10, s2, v16, v10
; CI-NEXT: v_cndmask_b32_e32 v5, 0, v10, vcc
; CI-NEXT: v_mov_b32_e32 v4, 0
; CI-NEXT: v_add_f64 v[4:5], v[8:9], v[4:5]
; CI-NEXT: v_mov_b32_e32 v8, s19
; CI-NEXT: v_bfi_b32 v18, s2, v16, v8
; CI-NEXT: v_trunc_f64_e32 v[8:9], s[20:21]
; CI-NEXT: v_trunc_f64_e32 v[10:11], s[22:23]
; CI-NEXT: v_add_f64 v[14:15], s[20:21], -v[8:9]
; CI-NEXT: v_mov_b32_e32 v19, s23
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5
; CI-NEXT: v_add_f64 v[14:15], s[22:23], -v[10:11]
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: v_mov_b32_e32 v17, s21
AMDGPU: Improve llvm.round.f64 lowering for CI+ The path already used for f16/f32 works a lot better when v_trunc_f64 is available.
2019-12-25 00:07:45 +08:00
; CI-NEXT: v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5
; CI-NEXT: v_bfi_b32 v19, s2, v16, v19
; CI-NEXT: v_trunc_f64_e32 v[12:13], s[16:17]
; CI-NEXT: v_bfi_b32 v17, s2, v16, v17
; CI-NEXT: v_cndmask_b32_e64 v15, 0, v19, s[0:1]
; CI-NEXT: v_mov_b32_e32 v14, 0
; CI-NEXT: v_add_f64 v[10:11], v[10:11], v[14:15]
; CI-NEXT: v_cndmask_b32_e32 v15, 0, v17, vcc
; CI-NEXT: v_mov_b32_e32 v14, 0
; CI-NEXT: v_mov_b32_e32 v17, s17
; CI-NEXT: v_add_f64 v[8:9], v[8:9], v[14:15]
; CI-NEXT: v_add_f64 v[14:15], s[16:17], -v[12:13]
; CI-NEXT: v_bfi_b32 v19, s2, v16, v17
; CI-NEXT: v_trunc_f64_e32 v[16:17], s[18:19]
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5
; CI-NEXT: v_add_f64 v[14:15], s[18:19], -v[16:17]
; CI-NEXT: v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5
; CI-NEXT: v_mov_b32_e32 v14, 0
; CI-NEXT: v_cndmask_b32_e64 v15, 0, v18, s[0:1]
; CI-NEXT: v_add_f64 v[14:15], v[16:17], v[14:15]
; CI-NEXT: v_cndmask_b32_e32 v17, 0, v19, vcc
; CI-NEXT: v_mov_b32_e32 v16, 0
; CI-NEXT: v_add_f64 v[12:13], v[12:13], v[16:17]
; CI-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:48
; CI-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:32
AMDGPU: Generate check lines
2019-12-25 00:24:30 +08:00
; CI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; CI-NEXT: s_endpgm
R600/SI: Custom lower fround This fixes it for SI. It also removes the pattern used previously for Evergreen for f32. I'm not sure if the the new R600 output is better or not, but it uses 1 fewer instructions if BFI is available. llvm-svn: 226682
2015-01-22 02:18:25 +08:00
%result = call <8 x double> @llvm.round.v8f64(<8 x double> %in) #1
store <8 x double> %result, <8 x double> addrspace(1)* %out
ret void
}
AMDGPU: Remove some old intrinsic uses from tests llvm-svn: 260493
2016-02-11 14:02:01 +08:00
declare i32 @llvm.amdgcn.workitem.id.x() #1
R600/SI: Custom lower fround This fixes it for SI. It also removes the pattern used previously for Evergreen for f32. I'm not sure if the the new R600 output is better or not, but it uses 1 fewer instructions if BFI is available. llvm-svn: 226682
2015-01-22 02:18:25 +08:00
declare double @llvm.round.f64(double) #1
declare <2 x double> @llvm.round.v2f64(<2 x double>) #1
declare <4 x double> @llvm.round.v4f64(<4 x double>) #1
declare <8 x double> @llvm.round.v8f64(<8 x double>) #1
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }