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llvm-project/llvm/lib/Target/Mips/MipsISelLowering.cpp

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remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
//
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-30 04:36:04 +08:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
//
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
//
// This file defines the interfaces that Mips uses to lower LLVM code into a
// selection DAG.
//
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
#include "MipsISelLowering.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "InstPrinter/MipsInstPrinter.h"
#include "MCTargetDesc/MipsBaseInfo.h"
Changed stack allocation On LowerFORMAL_ARGUMENTS. Added comments about new stack allocation. Expand SelectCC for i32 results llvm-svn: 41527
2007-08-28 13:08:16 +08:00
#include "MipsMachineFunction.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "MipsSubtarget.h"
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
#include "MipsTargetMachine.h"
reintroduce support for Mips "small" section handling. This is implemented somewhat differently than before, but it should have the same functionality and the previous testcase passes again. llvm-svn: 78900
2009-08-13 14:28:06 +08:00
#include "MipsTargetObjectFile.h"
[mips] Add code to do tail call optimization. Currently, it is enabled only if option "enable-mips-tail-calls" is given and all of the callee's arguments are passed in registers. llvm-svn: 166342
2012-10-20 05:47:33 +08:00
#include "llvm/ADT/Statistic.h"
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
#include "llvm/ADT/StringSwitch.h"
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
2007-12-31 12:13:23 +08:00
#include "llvm/CodeGen/MachineRegisterInfo.h"
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/ValueTypes.h"
Move all of the header files which are involved in modelling the LLVM IR into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
2013-01-02 19:36:10 +08:00
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/GlobalVariable.h"
[mips] Add code to do tail call optimization. Currently, it is enabled only if option "enable-mips-tail-calls" is given and all of the callee's arguments are passed in registers. llvm-svn: 166342
2012-10-20 05:47:33 +08:00
#include "llvm/Support/CommandLine.h"
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
#include "llvm/Support/Debug.h"
assert(0) -> LLVM_UNREACHABLE. Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
2009-07-12 04:10:48 +08:00
#include "llvm/Support/ErrorHandling.h"
llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC. Thanks to Andy Gibbs, to report the issue. llvm-svn: 155287
2012-04-21 23:31:45 +08:00
#include "llvm/Support/raw_ostream.h"
[mips] Properly parse registers that appear in inline-asm constraints. llvm-svn: 188336
2013-08-14 08:21:25 +08:00
#include <cctype>
llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC. Thanks to Andy Gibbs, to report the issue. llvm-svn: 155287
2012-04-21 23:31:45 +08:00
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
using namespace llvm;
[Modules] Fix potential ODR violations by sinking the DEBUG_TYPE definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
2014-04-22 10:41:26 +08:00
#define DEBUG_TYPE "mips-lower"
[mips] Add code to do tail call optimization. Currently, it is enabled only if option "enable-mips-tail-calls" is given and all of the callee's arguments are passed in registers. llvm-svn: 166342
2012-10-20 05:47:33 +08:00
STATISTIC(NumTailCalls, "Number of tail calls");
[mips] Add command line option "-mxgot". llvm-svn: 168455
2012-11-22 04:21:11 +08:00
static cl::opt<bool>
LargeGOT("mxgot", cl::Hidden,
cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
[mips] Trap on integer division by zero. By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. llvm-svn: 182306
2013-05-21 02:07:43 +08:00
static cl::opt<bool>
[mips] Rename option to make it compatible with gcc. llvm-svn: 182397
2013-05-22 01:17:59 +08:00
NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
[mips] Trap on integer division by zero. By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. llvm-svn: 182306
2013-05-21 02:07:43 +08:00
cl::desc("MIPS: Don't trap on integer division by zero."),
cl::init(false));
Start pushing changes for Mips Fast-Isel llvm-svn: 206505
2014-04-18 06:15:34 +08:00
cl::opt<bool>
EnableMipsFastISel("mips-fast-isel", cl::Hidden,
cl::desc("Allow mips-fast-isel to be used"),
cl::init(false));
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
static const MCPhysReg O32IntRegs[4] = {
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
Mips::A0, Mips::A1, Mips::A2, Mips::A3
};
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
static const MCPhysReg Mips64IntRegs[8] = {
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
};
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
static const MCPhysReg Mips64DPRegs[8] = {
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
};
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
// If I is a shifted mask, set the size (Size) and the first bit of the
Make IsShiftedMask a static function rather than defining it in an anonymous namespace. llvm-svn: 137975
2011-08-19 04:07:42 +08:00
// mask (Pos), and return true.
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
if (!isShiftedMask_64(I))
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
return false;
Add support for ext and ins. llvm-svn: 137804
2011-08-17 10:05:42 +08:00
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
Size = CountPopulation_64(I);
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. llvm-svn: 182680
2013-05-25 06:23:49 +08:00
Pos = countTrailingZeros(I);
Make IsShiftedMask a static function rather than defining it in an anonymous namespace. llvm-svn: 137975
2011-08-19 04:07:42 +08:00
return true;
Add support for ext and ins. llvm-svn: 137804
2011-08-17 10:05:42 +08:00
}
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
Add an option to use a virtual register as the global base register instead of reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
2012-02-25 06:34:47 +08:00
MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
}
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
SelectionDAG &DAG,
unsigned Flag) const {
return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
}
[mips] Define getTargetNode as a template function. No intended functionality change. llvm-svn: 191350
2013-09-25 08:30:25 +08:00
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
SelectionDAG &DAG,
unsigned Flag) const {
return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
[mips] Define getTargetNode as a template function. No intended functionality change. llvm-svn: 191350
2013-09-25 08:30:25 +08:00
}
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
SelectionDAG &DAG,
unsigned Flag) const {
return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
[mips] Add helper functions that create nodes for computing address. llvm-svn: 168456
2012-11-22 04:26:38 +08:00
}
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
SelectionDAG &DAG,
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
unsigned Flag) const {
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
[mips] Add helper functions that create nodes for computing address. llvm-svn: 168456
2012-11-22 04:26:38 +08:00
}
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
SelectionDAG &DAG,
unsigned Flag) const {
return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
N->getOffset(), Flag);
[mips] Add helper functions that create nodes for computing address. llvm-svn: 168456
2012-11-22 04:26:38 +08:00
}
Rip all of the global variable lowering logic out of TargetAsmInfo. Since it is highly specific to the object file that will be generated in the end, this introduces a new TargetLoweringObjectFile interface that is implemented for each of ELF/MachO/COFF/Alpha/PIC16 and XCore. Though still is still a brutal and ugly refactoring, this is a major step towards goodness. This patch also: 1. fixes a bunch of dangling pointer problems in the PIC16 backend. 2. disables the TargetLowering copy ctor which PIC16 was accidentally using. 3. gets us closer to xcore having its own crazy target section flags and pic16 not having to shadow sections with its own objects. 4. fixes wierdness where ELF targets would set CStringSection but not CStringSection_. Factor the code better. 5. fixes some bugs in string lowering on ELF targets. llvm-svn: 77294
2009-07-28 11:13:23 +08:00
const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
Fixes related to coding style. llvm-svn: 131922
2011-05-24 05:13:59 +08:00
case MipsISD::JmpLink: return "MipsISD::JmpLink";
Add node and enum for mips tail call. llvm-svn: 166318
2012-10-20 04:59:39 +08:00
case MipsISD::TailCall: return "MipsISD::TailCall";
Fixes related to coding style. llvm-svn: 131922
2011-05-24 05:13:59 +08:00
case MipsISD::Hi: return "MipsISD::Hi";
case MipsISD::Lo: return "MipsISD::Lo";
case MipsISD::GPRel: return "MipsISD::GPRel";
This patch implements the thread local storage. Implemented are General Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
2011-05-31 10:53:58 +08:00
case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
Fixes related to coding style. llvm-svn: 131922
2011-05-24 05:13:59 +08:00
case MipsISD::Ret: return "MipsISD::Ret";
[mips] Lower EH_RETURN. Patch by Sasa Stankovic. llvm-svn: 173862
2013-01-30 08:26:49 +08:00
case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
Fixes related to coding style. llvm-svn: 131922
2011-05-24 05:13:59 +08:00
case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
case MipsISD::FPCmp: return "MipsISD::FPCmp";
case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
2013-05-17 05:17:15 +08:00
case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
[mips] Rename isel nodes. llvm-svn: 192663
2013-10-15 09:12:50 +08:00
case MipsISD::MFHI: return "MipsISD::MFHI";
case MipsISD::MFLO: return "MipsISD::MFLO";
case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
[mips] Add mips-specific nodes which will be used to select multiply and divide instructions. llvm-svn: 178394
2013-03-30 09:14:04 +08:00
case MipsISD::Mult: return "MipsISD::Mult";
case MipsISD::Multu: return "MipsISD::Multu";
Fixes related to coding style. llvm-svn: 131922
2011-05-24 05:13:59 +08:00
case MipsISD::MAdd: return "MipsISD::MAdd";
case MipsISD::MAddu: return "MipsISD::MAddu";
case MipsISD::MSub: return "MipsISD::MSub";
case MipsISD::MSubu: return "MipsISD::MSubu";
case MipsISD::DivRem: return "MipsISD::DivRem";
case MipsISD::DivRemU: return "MipsISD::DivRemU";
[mips] Add mips-specific nodes which will be used to select multiply and divide instructions. llvm-svn: 178394
2013-03-30 09:14:04 +08:00
case MipsISD::DivRem16: return "MipsISD::DivRem16";
case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
Fixes related to coding style. llvm-svn: 131922
2011-05-24 05:13:59 +08:00
case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
Fix indentation. llvm-svn: 146431
2011-12-13 06:38:19 +08:00
case MipsISD::Wrapper: return "MipsISD::Wrapper";
Lower memory barriers to sync instructions. llvm-svn: 135537
2011-07-20 07:30:50 +08:00
case MipsISD::Sync: return "MipsISD::Sync";
Add support for ext and ins. llvm-svn: 137804
2011-08-17 10:05:42 +08:00
case MipsISD::Ext: return "MipsISD::Ext";
case MipsISD::Ins: return "MipsISD::Ins";
Define Mips specific unaligned load/store nodes. llvm-svn: 157863
2012-06-02 08:03:12 +08:00
case MipsISD::LWL: return "MipsISD::LWL";
case MipsISD::LWR: return "MipsISD::LWR";
case MipsISD::SWL: return "MipsISD::SWL";
case MipsISD::SWR: return "MipsISD::SWR";
case MipsISD::LDL: return "MipsISD::LDL";
case MipsISD::LDR: return "MipsISD::LDR";
case MipsISD::SDL: return "MipsISD::SDL";
case MipsISD::SDR: return "MipsISD::SDR";
SelectionDAG node enums for MIPS DSP nodes. llvm-svn: 164430
2012-09-22 07:52:47 +08:00
case MipsISD::EXTP: return "MipsISD::EXTP";
case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
case MipsISD::SHILO: return "MipsISD::SHILO";
case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
case MipsISD::MULT: return "MipsISD::MULT";
case MipsISD::MULTU: return "MipsISD::MULTU";
Mips ISD typo llvm-svn: 176426
2013-03-04 09:06:54 +08:00
case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
SelectionDAG node enums for MIPS DSP nodes. llvm-svn: 164430
2012-09-22 07:52:47 +08:00
case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
[mips] Instruction selection patterns for DSP-ASE vector shifts. llvm-svn: 179906
2013-04-20 07:21:32 +08:00
case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
[mips] Instruction selection patterns for DSP-ASE vector select and compare instructions. llvm-svn: 180820
2013-05-01 06:37:26 +08:00
case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
[mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
2013-09-24 18:46:19 +08:00
case MipsISD::VCEQ: return "MipsISD::VCEQ";
case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
[mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics) llvm-svn: 191291
2013-09-24 20:18:31 +08:00
case MipsISD::VSMAX: return "MipsISD::VSMAX";
case MipsISD::VSMIN: return "MipsISD::VSMIN";
case MipsISD::VUMAX: return "MipsISD::VUMAX";
case MipsISD::VUMIN: return "MipsISD::VUMIN";
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
[mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics) llvm-svn: 191195
2013-09-23 21:22:24 +08:00
case MipsISD::VNOR: return "MipsISD::VNOR";
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) llvm-svn: 191301
2013-09-24 22:02:15 +08:00
case MipsISD::VSHF: return "MipsISD::VSHF";
[mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics) llvm-svn: 191302
2013-09-24 22:20:00 +08:00
case MipsISD::SHF: return "MipsISD::SHF";
[mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics) llvm-svn: 191304
2013-09-24 22:36:12 +08:00
case MipsISD::ILVEV: return "MipsISD::ILVEV";
case MipsISD::ILVOD: return "MipsISD::ILVOD";
case MipsISD::ILVL: return "MipsISD::ILVL";
case MipsISD::ILVR: return "MipsISD::ILVR";
[mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics) llvm-svn: 191306
2013-09-24 22:53:25 +08:00
case MipsISD::PCKEV: return "MipsISD::PCKEV";
case MipsISD::PCKOD: return "MipsISD::PCKOD";
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
case MipsISD::INSVE: return "MipsISD::INSVE";
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
default: return nullptr;
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
}
[mips] Stop caching the result of hasMips64(), isABI_O32(), isABI_N32(), and isABI_N64() from MipsSubTarget in MipsTargetLowering Summary: The short name is quite convenient so provide an accessor for them instead. No functional change Depends on D3177 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3178 llvm-svn: 204911
2014-03-27 18:46:12 +08:00
MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
: TargetLowering(TM, new MipsTargetObjectFile()),
Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Mips does not have i1 type, so use i32 for
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// setcc operations results (slt, sgt, ...).
Rename SetCCResultContents to BooleanContents. In practice these booleans are mostly produced by SetCC, however the concept is more general. llvm-svn: 59911
2008-11-23 23:47:28 +08:00
setBooleanContents(ZeroOrOneBooleanContent);
[mips] Instruction selection patterns for DSP-ASE vector select and compare instructions. llvm-svn: 180820
2013-05-01 06:37:26 +08:00
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// Load extented operations for i1 types must be promoted
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
One more operation expansion for MIPS, from test/CodeGen/Generic. llvm-svn: 76149
2009-07-17 12:07:24 +08:00
// MIPS doesn't have extending float->double load/store
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Expand a bunch of illegal operations on MIPS (found by inspection and running over CodeGen/Generic). llvm-svn: 76146
2009-07-17 10:28:12 +08:00
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// Used by legalize types to correctly generate the setcc result.
// Without this, every float setcc comes with a AND/OR with the result,
// we don't want this, since the fpcmp result goes to a flag register,
Handle more SELECT corner cases considering legalize types, probabily wont work with the default legalizer. llvm-svn: 54249
2008-08-01 02:31:28 +08:00
// which is used implicitly by brcond and select operations.
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
Handle more SELECT corner cases considering legalize types, probabily wont work with the default legalizer. llvm-svn: 54249
2008-08-01 02:31:28 +08:00
MipsTargetLowering cleanup llvm-svn: 53270
2008-07-09 12:15:08 +08:00
// Mips Custom Operations
[mips] Custom-legalize BR_JT. In N64-static, GOT address is needed to compute the branch address. llvm-svn: 176580
2013-03-07 05:32:03 +08:00
setOperationAction(ISD::BR_JT, MVT::Other, Custom);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka llvm-svn: 127027
2011-03-05 04:01:52 +08:00
setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
setOperationAction(ISD::JumpTable, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
setOperationAction(ISD::SELECT, MVT::f32, Custom);
setOperationAction(ISD::SELECT, MVT::f64, Custom);
setOperationAction(ISD::SELECT, MVT::i32, Custom);
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. llvm-svn: 160064
2012-07-12 03:32:27 +08:00
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass. llvm-svn: 152450
2012-03-10 07:46:03 +08:00
setOperationAction(ISD::SETCC, MVT::f32, Custom);
setOperationAction(ISD::SETCC, MVT::f64, Custom);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::BRCOND, MVT::Other, Custom);
Add suport for VASTART on Mips. llvm-svn: 95506
2010-02-07 05:00:02 +08:00
setOperationAction(ISD::VASTART, MVT::Other, Custom);
Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set operation action of nodes. llvm-svn: 152452
2012-03-10 08:03:50 +08:00
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
2013-05-17 05:17:15 +08:00
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set operation action of nodes. llvm-svn: 152452
2012-03-10 08:03:50 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (Subtarget->isGP64bit()) {
Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set operation action of nodes. llvm-svn: 152452
2012-03-10 08:03:50 +08:00
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
setOperationAction(ISD::JumpTable, MVT::i64, Custom);
setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
setOperationAction(ISD::SELECT, MVT::i64, Custom);
Set operation actions for load/store nodes in the Mips backend. llvm-svn: 157866
2012-06-02 08:04:42 +08:00
setOperationAction(ISD::LOAD, MVT::i64, Custom);
setOperationAction(ISD::STORE, MVT::i64, Custom);
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
2013-05-17 05:17:15 +08:00
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set operation action of nodes. llvm-svn: 152452
2012-03-10 08:03:50 +08:00
}
Add suport for VASTART on Mips. llvm-svn: 95506
2010-02-07 05:00:02 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (!Subtarget->isGP64bit()) {
Expand 64-bit shifts if target ABI is O32. llvm-svn: 156457
2012-05-09 08:55:21 +08:00
setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
}
[mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node. Patch by Sasa Stankovic. llvm-svn: 167548
2012-11-08 03:10:58 +08:00
setOperationAction(ISD::ADD, MVT::i32, Custom);
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (Subtarget->isGP64bit())
[mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node. Patch by Sasa Stankovic. llvm-svn: 167548
2012-11-08 03:10:58 +08:00
setOperationAction(ISD::ADD, MVT::i64, Custom);
Improve div/rem node handling on mips. Patch by Akira Hatanaka llvm-svn: 127034
2011-03-05 05:03:24 +08:00
setOperationAction(ISD::SDIV, MVT::i32, Expand);
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UDIV, MVT::i32, Expand);
setOperationAction(ISD::UREM, MVT::i32, Expand);
Add support for 64-bit divide instructions. llvm-svn: 141024
2011-10-04 05:06:13 +08:00
setOperationAction(ISD::SDIV, MVT::i64, Expand);
setOperationAction(ISD::SREM, MVT::i64, Expand);
setOperationAction(ISD::UDIV, MVT::i64, Expand);
setOperationAction(ISD::UREM, MVT::i64, Expand);
Improve div/rem node handling on mips. Patch by Akira Hatanaka llvm-svn: 127034
2011-03-05 05:03:24 +08:00
MipsTargetLowering cleanup llvm-svn: 53270
2008-07-09 12:15:08 +08:00
// Operations not directly supported by Mips.
DAGCombiner: Use correct value type for checking legality of BR_CC v3 LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. llvm-svn: 176694
2013-03-08 23:36:57 +08:00
setOperationAction(ISD::BR_CC, MVT::f32, Expand);
setOperationAction(ISD::BR_CC, MVT::f64, Expand);
setOperationAction(ISD::BR_CC, MVT::i32, Expand);
setOperationAction(ISD::BR_CC, MVT::i64, Expand);
SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC The SelectionDAG bad a special case for ISD::SELECT_CC, where it would allow targets to specify: setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); to indicate that they wanted to expand ISD::SELECT_CC for all types. This wasn't applied correctly everywhere, and it makes writing new DAG patterns with ISD::SELECT_CC difficult. llvm-svn: 210541
2014-06-11 00:01:29 +08:00
setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
64-bit uint-fp conversion nodes are expanded. llvm-svn: 147014
2011-12-21 07:40:56 +08:00
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
64-bit uint-fp conversion nodes are expanded. llvm-svn: 147014
2011-12-21 07:40:56 +08:00
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
if (Subtarget->hasCnMips()) {
setOperationAction(ISD::CTPOP, MVT::i32, Legal);
setOperationAction(ISD::CTPOP, MVT::i64, Legal);
} else {
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
setOperationAction(ISD::CTPOP, MVT::i64, Expand);
}
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::CTTZ, MVT::i32, Expand);
Expand 64-bit CTPOP and CTTZ. llvm-svn: 147021
2011-12-21 08:14:05 +08:00
setOperationAction(ISD::CTTZ, MVT::i64, Expand);
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
2011-12-13 09:56:10 +08:00
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::ROTL, MVT::i32, Expand);
Add definitions of Mips64 rotate instructions. llvm-svn: 140870
2011-10-01 02:51:46 +08:00
setOperationAction(ISD::ROTL, MVT::i64, Expand);
Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering. The frame object which points to the dynamically allocated area will not be needed after changes are made to cease reserving call frames. llvm-svn: 161076
2012-08-01 04:54:48 +08:00
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka llvm-svn: 121377
2010-12-10 01:32:30 +08:00
Change the names of functions isMips* to hasMips*. llvm-svn: 140214
2011-09-21 07:53:09 +08:00
if (!Subtarget->hasMips32r2())
Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka llvm-svn: 121377
2010-12-10 01:32:30 +08:00
setOperationAction(ISD::ROTR, MVT::i32, Expand);
Add definitions of Mips64 rotate instructions. llvm-svn: 140870
2011-10-01 02:51:46 +08:00
if (!Subtarget->hasMips64r2())
setOperationAction(ISD::ROTR, MVT::i64, Expand);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::FSIN, MVT::f32, Expand);
Expands FCOS and FSIN nodes when type is f64. llvm-svn: 127017
2011-03-05 02:54:14 +08:00
setOperationAction(ISD::FSIN, MVT::f64, Expand);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::FCOS, MVT::f32, Expand);
Expands FCOS and FSIN nodes when type is f64. llvm-svn: 127017
2011-03-05 02:54:14 +08:00
setOperationAction(ISD::FCOS, MVT::f64, Expand);
Teach SDISel to combine fsin / fcos into a fsincos node if the following conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 llvm-svn: 173755
2013-01-29 10:32:37 +08:00
setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::FPOWI, MVT::f32, Expand);
setOperationAction(ISD::FPOW, MVT::f32, Expand);
Expand f64 FPOW. llvm-svn: 131928
2011-05-24 06:23:58 +08:00
setOperationAction(ISD::FPOW, MVT::f64, Expand);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::FLOG, MVT::f32, Expand);
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
setOperationAction(ISD::FLOG10, MVT::f32, Expand);
setOperationAction(ISD::FEXP, MVT::f32, Expand);
Add an intrinsic and codegen support for fused multiply-accumulate. The intent is to use this for architectures that have a native FMA instruction. llvm-svn: 134742
2011-07-09 05:39:21 +08:00
setOperationAction(ISD::FMA, MVT::f32, Expand);
setOperationAction(ISD::FMA, MVT::f64, Expand);
Expand FREM. llvm-svn: 153671
2012-03-30 02:43:11 +08:00
setOperationAction(ISD::FREM, MVT::f32, Expand);
setOperationAction(ISD::FREM, MVT::f64, Expand);
MipsTargetLowering cleanup llvm-svn: 53270
2008-07-09 12:15:08 +08:00
[mips] Lower EH_RETURN. Patch by Sasa Stankovic. llvm-svn: 173862
2013-01-30 08:26:49 +08:00
setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
Improve varags handling, with testcases. Patch by Sasa Stankovic llvm-svn: 127349
2011-03-10 03:22:22 +08:00
setOperationAction(ISD::VAARG, MVT::Other, Expand);
setOperationAction(ISD::VACOPY, MVT::Other, Expand);
setOperationAction(ISD::VAEND, MVT::Other, Expand);
MipsTargetLowering cleanup llvm-svn: 53270
2008-07-09 12:15:08 +08:00
// Use the default for now
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Code generation for 'fence' instruction. llvm-svn: 136283
2011-07-28 06:21:52 +08:00
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. llvm-svn: 138751
2011-08-30 02:23:02 +08:00
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. I think this completes the basic CodeGen for atomicrmw and cmpxchg. llvm-svn: 136813
2011-08-04 05:06:02 +08:00
setInsertFencesForAtomic(true);
[mips] Fold FeatureSEInReg into FeatureMips32r2 Summary: No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3693 llvm-svn: 208543
2014-05-12 20:28:15 +08:00
if (!Subtarget->hasMips32r2()) {
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
}
[mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64 Summary: DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no effect on the CodeGen tests since expansion of i64 prevented their use anyway. The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as well. This is not a functional change since DCLZ is still prohibited by being a MIPS64 instruction (MIPS16 is only compatible with MIPS32). No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3694 llvm-svn: 208544
2014-05-12 20:41:59 +08:00
// MIPS16 lacks MIPS32's clz and clo instructions.
if (!Subtarget->hasMips32() || Subtarget->inMips16Mode())
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
[mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64 Summary: DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no effect on the CodeGen tests since expansion of i64 prevented their use anyway. The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as well. This is not a functional change since DCLZ is still prohibited by being a MIPS64 instruction (MIPS16 is only compatible with MIPS32). No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3694 llvm-svn: 208544
2014-05-12 20:41:59 +08:00
if (!Subtarget->hasMips64())
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test case for DCLO and DCLZ. llvm-svn: 147022
2011-12-21 08:20:27 +08:00
setOperationAction(ISD::CTLZ, MVT::i64, Expand);
Support added for ctlz intrinsic, test case added. llvm-svn: 54516
2008-08-08 14:16:31 +08:00
[mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2 Summary: dsbh and dshd are not available on Mips32r2. No codegen test changes required since expansion of i64 prevented the use of these instructions anyway. Depends on D3690 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3692 llvm-svn: 208542
2014-05-12 20:15:41 +08:00
if (!Subtarget->hasMips32r2())
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
[mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2 Summary: dsbh and dshd are not available on Mips32r2. No codegen test changes required since expansion of i64 prevented the use of these instructions anyway. Depends on D3690 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3692 llvm-svn: 208542
2014-05-12 20:15:41 +08:00
if (!Subtarget->hasMips64r2())
Add definition of DSBH (Double Swap Bytes within Halfwords) and DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces 64-bit bswap with a DSBH and DSHD pair. llvm-svn: 147017
2011-12-21 07:56:43 +08:00
setOperationAction(ISD::BSWAP, MVT::i64, Expand);
Removed SELECT_CC custom lowering. This is not needed anymore, the SELECT node is lowered properly and covers everything LowerSELECT_CC did. Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This avoid the ugly instruction by instruction checking in printOperand. Added a swap instruction present in the allegrex core. Added two conditional instructions present in the allegrex core : MOVZ and MOVN. They both allow a more efficient SELECT operation for integers. Also added SELECT patterns to optimize MOVZ and MOVN usage. The brcond and setcc patterns were cleaned: redundant and suboptimal patterns were removed. The suboptimals were replaced by more efficient ones. Fixed some instructions that were using immZExt16 instead of immSExt16. llvm-svn: 54724
2008-08-13 15:13:40 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (Subtarget->isGP64bit()) {
Set operation actions for load/store nodes in the Mips backend. llvm-svn: 157866
2012-06-02 08:04:42 +08:00
setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
setTruncStoreAction(MVT::i64, MVT::i32, Custom);
}
[mips] Implement llvm.trap intrinsic. Patch by Sasa Stankovic. llvm-svn: 187244
2013-07-27 04:58:55 +08:00
setOperationAction(ISD::TRAP, MVT::Other, Legal);
Improve div/rem node handling on mips. Patch by Akira Hatanaka llvm-svn: 127034
2011-03-05 05:03:24 +08:00
setTargetDAGCombine(ISD::SDIVREM);
setTargetDAGCombine(ISD::UDIVREM);
Invoke setTargetDAGCombine for SELECT. llvm-svn: 152290
2012-03-08 11:26:37 +08:00
setTargetDAGCombine(ISD::SELECT);
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
setTargetDAGCombine(ISD::AND);
setTargetDAGCombine(ISD::OR);
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following pattern: (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) "tjt" is a TargetJumpTable node. llvm-svn: 158419
2012-06-14 04:33:18 +08:00
setTargetDAGCombine(ISD::ADD);
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
setMinFunctionAlignment(Subtarget->isGP64bit() ? 3 : 2);
Make the logic for determining function alignment more explicit. No functionality change. llvm-svn: 131012
2011-05-07 04:34:06 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
setStackPointerRegisterToSaveRestore(Subtarget->isABI_N64() ? Mips::SP_64
: Mips::SP);
Add support for C++ exception handling. llvm-svn: 132131
2011-05-27 02:59:03 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
setExceptionPointerRegister(Subtarget->isABI_N64() ? Mips::A0_64 : Mips::A0);
setExceptionSelectorRegister(Subtarget->isABI_N64() ? Mips::A1_64 : Mips::A1);
Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp. llvm-svn: 158414
2012-06-14 03:33:32 +08:00
Update TargetLowering ivars for name policy. http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly ivars should be camel-case and start with an upper-case letter. A few in TargetLowering were starting with a lower-case letter. No functional change intended. llvm-svn: 175667
2013-02-21 05:13:59 +08:00
MaxStoresPerMemcpy = 16;
Support for microMIPS LL and SC instructions. llvm-svn: 197692
2013-12-20 00:12:56 +08:00
isMicroMips = Subtarget->inMicroMipsMode();
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
if (TM.getSubtargetImpl()->inMips16Mode())
return llvm::createMips16TargetLowering(TM);
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
return llvm::createMipsSETargetLowering(TM);
Define unaligned load and store. llvm-svn: 137515
2011-08-13 05:30:06 +08:00
}
Start pushing changes for Mips Fast-Isel llvm-svn: 206505
2014-04-18 06:15:34 +08:00
// Create a fast isel object.
FastISel *
MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo) const {
if (!EnableMipsFastISel)
return TargetLowering::createFastISel(funcInfo, libInfo);
return Mips::createFastISel(funcInfo, libInfo);
}
Add LLVMContext argument to getSetCCResultType llvm-svn: 182180
2013-05-18 08:21:46 +08:00
EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
[mips] MipsTargetLowering::getSetCCResultType should return a vector type if vectors are being compared. llvm-svn: 171517
2013-01-05 04:06:01 +08:00
if (!VT.isVector())
return MVT::i32;
return VT.changeVectorElementTypeToInteger();
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
2008-03-10 23:42:14 +08:00
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
Improve div/rem node handling on mips. Patch by Akira Hatanaka llvm-svn: 127034
2011-03-05 05:03:24 +08:00
TargetLowering::DAGCombinerInfo &DCI,
Fix coding style violations. Remove white spaces and tabs. llvm-svn: 158471
2012-06-15 05:10:56 +08:00
const MipsSubtarget *Subtarget) {
Improve div/rem node handling on mips. Patch by Akira Hatanaka llvm-svn: 127034
2011-03-05 05:03:24 +08:00
if (DCI.isBeforeLegalizeOps())
return SDValue();
Add support for 64-bit divide instructions. llvm-svn: 141024
2011-10-04 05:06:13 +08:00
EVT Ty = N->getValueType(0);
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions. The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
2013-03-30 09:36:35 +08:00
unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
MipsISD::DivRemU16;
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(N);
Improve div/rem node handling on mips. Patch by Akira Hatanaka llvm-svn: 127034
2011-03-05 05:03:24 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
Improve div/rem node handling on mips. Patch by Akira Hatanaka llvm-svn: 127034
2011-03-05 05:03:24 +08:00
N->getOperand(0), N->getOperand(1));
SDValue InChain = DAG.getEntryNode();
SDValue InGlue = DivRem;
// insert MFLO
if (N->hasAnyUseOfValue(0)) {
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
Improve div/rem node handling on mips. Patch by Akira Hatanaka llvm-svn: 127034
2011-03-05 05:03:24 +08:00
InGlue);
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
InChain = CopyFromLo.getValue(1);
InGlue = CopyFromLo.getValue(2);
}
// insert MFHI
if (N->hasAnyUseOfValue(1)) {
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
Add support for 64-bit divide instructions. llvm-svn: 141024
2011-10-04 05:06:13 +08:00
HI, Ty, InGlue);
Improve div/rem node handling on mips. Patch by Akira Hatanaka llvm-svn: 127034
2011-03-05 05:03:24 +08:00
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
}
return SDValue();
}
[mips] Rename function. llvm-svn: 179741
2013-04-18 09:00:46 +08:00
static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
switch (CC) {
default: llvm_unreachable("Unknown fp condition code!");
case ISD::SETEQ:
case ISD::SETOEQ: return Mips::FCOND_OEQ;
case ISD::SETUNE: return Mips::FCOND_UNE;
case ISD::SETLT:
case ISD::SETOLT: return Mips::FCOND_OLT;
case ISD::SETGT:
case ISD::SETOGT: return Mips::FCOND_OGT;
case ISD::SETLE:
case ISD::SETOLE: return Mips::FCOND_OLE;
case ISD::SETGE:
case ISD::SETOGE: return Mips::FCOND_OGE;
case ISD::SETULT: return Mips::FCOND_ULT;
case ISD::SETULE: return Mips::FCOND_ULE;
case ISD::SETUGT: return Mips::FCOND_UGT;
case ISD::SETUGE: return Mips::FCOND_UGE;
case ISD::SETUO: return Mips::FCOND_UN;
case ISD::SETO: return Mips::FCOND_OR;
case ISD::SETNE:
case ISD::SETONE: return Mips::FCOND_ONE;
case ISD::SETUEQ: return Mips::FCOND_UEQ;
}
}
[mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd. llvm-svn: 178396
2013-03-30 09:16:38 +08:00
/// This function returns true if the floating point conditional branches and
/// conditional moves which use condition code CC should be inverted.
static bool invertFPCondCodeUser(Mips::CondCode CC) {
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
return false;
Tidy up. Simplify logic. No functional change intended. llvm-svn: 146896
2011-12-20 03:52:25 +08:00
assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
"Illegal Condition Code");
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
Tidy up. Simplify logic. No functional change intended. llvm-svn: 146896
2011-12-20 03:52:25 +08:00
return true;
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
}
// Creates and returns an FPCmp node from a setcc node.
// Returns Op if setcc is not a floating point comparison.
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
// must be a SETCC node
if (Op.getOpcode() != ISD::SETCC)
return Op;
SDValue LHS = Op.getOperand(0);
if (!LHS.getValueType().isFloatingPoint())
return Op;
SDValue RHS = Op.getOperand(1);
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. llvm-svn: 129606
2011-04-16 05:00:26 +08:00
// Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
// node if necessary.
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
[mips] Rename function. llvm-svn: 179741
2013-04-18 09:00:46 +08:00
DAG.getConstant(condCodeToFCC(CC), MVT::i32));
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
}
// Creates and returns a CMovFPT/F node.
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDValue False, SDLoc DL) {
[mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd. llvm-svn: 178396
2013-03-30 09:16:38 +08:00
ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
[mips] Fix FP conditional move instructions to have explicit FP condition code register operands. llvm-svn: 187242
2013-07-27 04:51:20 +08:00
SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
[mips] Fix FP conditional move instructions to have explicit FP condition code register operands. llvm-svn: 187242
2013-07-27 04:51:20 +08:00
True.getValueType(), True, FCC0, False, Cond);
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
Swap the operands of a select node if the false (the second) operand is 0. For example, this pattern (select (setcc lhs, rhs, cc), true, 0) is transformed to this one: (select (setcc lhs, rhs, inverse(cc)), 0, true) This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to replace 0 with $zero. llvm-svn: 152285
2012-03-08 10:14:24 +08:00
TargetLowering::DAGCombinerInfo &DCI,
Fix coding style violations. Remove white spaces and tabs. llvm-svn: 158471
2012-06-15 05:10:56 +08:00
const MipsSubtarget *Subtarget) {
Swap the operands of a select node if the false (the second) operand is 0. For example, this pattern (select (setcc lhs, rhs, cc), true, 0) is transformed to this one: (select (setcc lhs, rhs, inverse(cc)), 0, true) This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to replace 0 with $zero. llvm-svn: 152285
2012-03-08 10:14:24 +08:00
if (DCI.isBeforeLegalizeOps())
return SDValue();
SDValue SetCC = N->getOperand(0);
if ((SetCC.getOpcode() != ISD::SETCC) ||
!SetCC.getOperand(0).getValueType().isInteger())
return SDValue();
SDValue False = N->getOperand(2);
EVT FalseTy = False.getValueType();
if (!FalseTy.isInteger())
return SDValue();
[mips] Add some comments related to the optimization performed in performSELECTCombine. The structure of the code was slightly modified so that the next patch is easier to read/review. No functional changes. llvm-svn: 196496
2013-12-05 19:56:56 +08:00
ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
// If the RHS (False) is 0, we swap the order of the operands
// of ISD::SELECT (obviously also inverting the condition) so that we can
// take advantage of conditional moves using the $0 register.
// Example:
// return (a != 0) ? x : 0;
// load $reg, x
// movz $reg, $0, a
if (!FalseC)
Swap the operands of a select node if the false (the second) operand is 0. For example, this pattern (select (setcc lhs, rhs, cc), true, 0) is transformed to this one: (select (setcc lhs, rhs, inverse(cc)), 0, true) This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to replace 0 with $zero. llvm-svn: 152285
2012-03-08 10:14:24 +08:00
return SDValue();
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
const SDLoc DL(N);
Fix coding style violations. Remove white spaces and tabs. llvm-svn: 158471
2012-06-15 05:10:56 +08:00
[mips] Add some comments related to the optimization performed in performSELECTCombine. The structure of the code was slightly modified so that the next patch is easier to read/review. No functional changes. llvm-svn: 196496
2013-12-05 19:56:56 +08:00
if (!FalseC->getZExtValue()) {
ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
SDValue True = N->getOperand(1);
SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
Fix coding style violations. Remove white spaces and tabs. llvm-svn: 158471
2012-06-15 05:10:56 +08:00
[mips] Add some comments related to the optimization performed in performSELECTCombine. The structure of the code was slightly modified so that the next patch is easier to read/review. No functional changes. llvm-svn: 196496
2013-12-05 19:56:56 +08:00
return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
}
[mips] Small code generation improvement for conditional operator (select) in case the operands are constants and its difference is |1|. It should be possible in those cases to rematerialize the result using MIPS's slt and similar instructions. The small update to some of the tests in cmov.ll, sel1c.ll and sel2c.ll was needed otherwise the optimization implemented in this patch would have been triggered (difference between the operands was 1) and that would have changed the semantic of the tests. llvm-svn: 196498
2013-12-05 20:07:05 +08:00
// If both operands are integer constants there's a possibility that we
// can do some interesting optimizations.
SDValue True = N->getOperand(1);
ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
if (!TrueC || !True.getValueType().isInteger())
return SDValue();
// We'll also ignore MVT::i64 operands as this optimizations proves
// to be ineffective because of the required sign extensions as the result
// of a SETCC operator is always MVT::i32 for non-vector types.
if (True.getValueType() == MVT::i64)
return SDValue();
int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
// 1) (a < x) ? y : y-1
// slti $reg1, a, x
// addiu $reg2, $reg1, y-1
if (Diff == 1)
return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
// 2) (a < x) ? y-1 : y
// slti $reg1, a, x
// xor $reg1, $reg1, 1
// addiu $reg2, $reg1, y-1
if (Diff == -1) {
ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
}
[mips] Add some comments related to the optimization performed in performSELECTCombine. The structure of the code was slightly modified so that the next patch is easier to read/review. No functional changes. llvm-svn: 196496
2013-12-05 19:56:56 +08:00
// Couldn't optimize.
return SDValue();
Swap the operands of a select node if the false (the second) operand is 0. For example, this pattern (select (setcc lhs, rhs, cc), true, 0) is transformed to this one: (select (setcc lhs, rhs, inverse(cc)), 0, true) This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to replace 0 with $zero. llvm-svn: 152285
2012-03-08 10:14:24 +08:00
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
TargetLowering::DAGCombinerInfo &DCI,
Fix coding style violations. Remove white spaces and tabs. llvm-svn: 158471
2012-06-15 05:10:56 +08:00
const MipsSubtarget *Subtarget) {
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
// Pattern match EXT.
// $dst = and ((sra or srl) $src , pos), (2**size - 1)
// => ext $dst, $src, size, pos
[mips] Do not generate INS/EXT nodes if target does not have support for ins/ext. llvm-svn: 192330
2013-10-10 07:36:17 +08:00
if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert())
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
return SDValue();
SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
unsigned ShiftRightOpc = ShiftRight.getOpcode();
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
// Op's first operand must be a shift right.
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
return SDValue();
// The second operand of the shift must be an immediate.
ConstantSDNode *CN;
if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
return SDValue();
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
uint64_t Pos = CN->getZExtValue();
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
uint64_t SMPos, SMSize;
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
// Op's second operand must be a shifted mask.
if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
!isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
return SDValue();
// Return if the shifted mask does not start at bit 0 or the sum of its size
// and Pos exceeds the word's size.
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
EVT ValTy = N->getValueType(0);
if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
return SDValue();
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
Tidy up. Simplify logic. No functional change intended. llvm-svn: 146896
2011-12-20 03:52:25 +08:00
ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
Changed definition of EXT and INS per Bruno's comments. llvm-svn: 137892
2011-08-18 06:59:46 +08:00
DAG.getConstant(SMSize, MVT::i32));
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
}
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
TargetLowering::DAGCombinerInfo &DCI,
Fix coding style violations. Remove white spaces and tabs. llvm-svn: 158471
2012-06-15 05:10:56 +08:00
const MipsSubtarget *Subtarget) {
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
// Pattern match INS.
// $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
// where mask1 = (2**size - 1) << pos, mask0 = ~mask1
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
// => ins $dst, $src, size, pos, $src1
[mips] Do not generate INS/EXT nodes if target does not have support for ins/ext. llvm-svn: 192330
2013-10-10 07:36:17 +08:00
if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert())
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
return SDValue();
SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
ConstantSDNode *CN;
// See if Op's first operand matches (and $src1 , mask0).
if (And0.getOpcode() != ISD::AND)
return SDValue();
if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
!isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
return SDValue();
// See if Op's second operand matches (and (shl $src, pos), mask1).
if (And1.getOpcode() != ISD::AND)
return SDValue();
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
!isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
return SDValue();
// The shift masks must have the same position and size.
if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
return SDValue();
SDValue Shl = And1.getOperand(0);
if (Shl.getOpcode() != ISD::SHL)
return SDValue();
if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
return SDValue();
unsigned Shamt = CN->getZExtValue();
// Return if the shift amount and the first bit position of mask are not the
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
// same.
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
EVT ValTy = N->getValueType(0);
if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
return SDValue();
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
DAG.getConstant(SMPos0, MVT::i32),
Tidy up. Simplify logic. No functional change intended. llvm-svn: 146896
2011-12-20 03:52:25 +08:00
DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
}
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following pattern: (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) "tjt" is a TargetJumpTable node. llvm-svn: 158419
2012-06-14 04:33:18 +08:00
TargetLowering::DAGCombinerInfo &DCI,
Fix coding style violations. Remove white spaces and tabs. llvm-svn: 158471
2012-06-15 05:10:56 +08:00
const MipsSubtarget *Subtarget) {
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following pattern: (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) "tjt" is a TargetJumpTable node. llvm-svn: 158419
2012-06-14 04:33:18 +08:00
// (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
if (DCI.isBeforeLegalizeOps())
return SDValue();
SDValue Add = N->getOperand(1);
if (Add.getOpcode() != ISD::ADD)
return SDValue();
SDValue Lo = Add.getOperand(1);
if ((Lo.getOpcode() != MipsISD::Lo) ||
(Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
return SDValue();
EVT ValTy = N->getValueType(0);
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(N);
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following pattern: (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) "tjt" is a TargetJumpTable node. llvm-svn: 158419
2012-06-14 04:33:18 +08:00
SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
Add.getOperand(0));
return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
}
Fix a lot of o32 CC issues and add a bunch of tests. Patch by Akira Hatanaka with some small modifications by me. llvm-svn: 125292
2011-02-11 02:05:10 +08:00
SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
const {
SelectionDAG &DAG = DCI.DAG;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
unsigned Opc = N->getOpcode();
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
switch (Opc) {
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
default: break;
Improve div/rem node handling on mips. Patch by Akira Hatanaka llvm-svn: 127034
2011-03-05 05:03:24 +08:00
case ISD::SDIVREM:
case ISD::UDIVREM:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return performDivRemCombine(N, DAG, DCI, Subtarget);
Swap the operands of a select node if the false (the second) operand is 0. For example, this pattern (select (setcc lhs, rhs, cc), true, 0) is transformed to this one: (select (setcc lhs, rhs, inverse(cc)), 0, true) This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to replace 0 with $zero. llvm-svn: 152285
2012-03-08 10:14:24 +08:00
case ISD::SELECT:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return performSELECTCombine(N, DAG, DCI, Subtarget);
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
case ISD::AND:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return performANDCombine(N, DAG, DCI, Subtarget);
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. llvm-svn: 137831
2011-08-18 01:45:08 +08:00
case ISD::OR:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return performORCombine(N, DAG, DCI, Subtarget);
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following pattern: (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) "tjt" is a TargetJumpTable node. llvm-svn: 158419
2012-06-14 04:33:18 +08:00
case ISD::ADD:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return performADDCombine(N, DAG, DCI, Subtarget);
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
}
return SDValue();
}
Add MIPS DSP register classes. Set actions of DSP vector operations and override TargetLowering's callback functions. llvm-svn: 164431
2012-09-22 07:58:31 +08:00
void
MipsTargetLowering::LowerOperationWrapper(SDNode *N,
SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const {
SDValue Res = LowerOperation(SDValue(N, 0), DAG);
for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
Results.push_back(Res.getValue(I));
}
void
MipsTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const {
[mips] Simplify code. No intended functionality changes. llvm-svn: 180807
2013-05-01 05:17:07 +08:00
return LowerOperationWrapper(N, Results, DAG);
Add MIPS DSP register classes. Set actions of DSP vector operations and override TargetLowering's callback functions. llvm-svn: 164431
2012-09-22 07:58:31 +08:00
}
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue MipsTargetLowering::
Use const qualifiers with TargetLowering. This eliminates several const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
2010-04-17 23:26:15 +08:00
LowerOperation(SDValue Op, SelectionDAG &DAG) const
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
{
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
switch (Op.getOpcode())
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
{
Fix indentation. llvm-svn: 178395
2013-03-30 09:15:17 +08:00
case ISD::BR_JT: return lowerBR_JT(Op, DAG);
case ISD::BRCOND: return lowerBRCOND(Op, DAG);
case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
case ISD::JumpTable: return lowerJumpTable(Op, DAG);
case ISD::SELECT: return lowerSELECT(Op, DAG);
case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
case ISD::SETCC: return lowerSETCC(Op, DAG);
case ISD::VASTART: return lowerVASTART(Op, DAG);
case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
case ISD::LOAD: return lowerLOAD(Op, DAG);
case ISD::STORE: return lowerSTORE(Op, DAG);
case ISD::ADD: return lowerADD(Op, DAG);
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
2013-05-17 05:17:15 +08:00
case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
return SDValue();
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Lower helper functions
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
// addLiveIn - This helper function adds the specified physical register to the
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// MachineFunction as a live in value. It also creates a corresponding
// virtual register for it.
static unsigned
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
{
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
2007-12-31 12:13:23 +08:00
unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
MF.getRegInfo().addLiveIn(PReg, VReg);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
return VReg;
}
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI,
MachineBasicBlock &MBB,
const TargetInstrInfo &TII,
bool Is64Bit) {
[mips] Trap on integer division by zero. By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. llvm-svn: 182306
2013-05-21 02:07:43 +08:00
if (NoZeroDivCheck)
return &MBB;
// Insert instruction "teq $divisor_reg, $zero, 7".
MachineBasicBlock::iterator I(MI);
MachineInstrBuilder MIB;
[mips] Transfer kill flag to the newly created operand. llvm-svn: 192662
2013-10-15 09:06:30 +08:00
MachineOperand &Divisor = MI->getOperand(2);
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev. Remove the old functions. llvm-svn: 202636
2014-03-02 20:27:27 +08:00
MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
[mips] Transfer kill flag to the newly created operand. llvm-svn: 192662
2013-10-15 09:06:30 +08:00
.addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
.addReg(Mips::ZERO).addImm(7);
[mips] Trap on integer division by zero. By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. llvm-svn: 182306
2013-05-21 02:07:43 +08:00
// Use the 32-bit sub-register if this is a 64-bit division.
if (Is64Bit)
MIB->getOperand(0).setSubReg(Mips::sub_32);
[mips] Transfer kill flag to the newly created operand. llvm-svn: 192662
2013-10-15 09:06:30 +08:00
// Clear Divisor's kill flag.
Divisor.setIsKill(false);
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
// We would normally delete the original instruction here but in this case
// we only needed to inject an additional instruction rather than replace it.
[mips] Trap on integer division by zero. By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. llvm-svn: 182306
2013-05-21 02:07:43 +08:00
return &MBB;
}
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
MachineBasicBlock *
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) const {
switch (MI->getOpcode()) {
Expand the sel pseudo/macro. This generates basic blocks where previously there were inline br .+4 instructions. Soon everything can enjoy the full instruction scheduling experience. llvm-svn: 175718
2013-02-21 12:22:38 +08:00
default:
llvm_unreachable("Unexpected instr type to insert");
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_ADD_I8:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_ADD_I16:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_ADD_I32:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
case Mips::ATOMIC_LOAD_ADD_I64:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_AND_I8:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_AND_I16:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_AND_I32:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 4, Mips::AND);
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
case Mips::ATOMIC_LOAD_AND_I64:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 8, Mips::AND64);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_OR_I8:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_OR_I16:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_OR_I32:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 4, Mips::OR);
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
case Mips::ATOMIC_LOAD_OR_I64:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 8, Mips::OR64);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_XOR_I8:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_XOR_I16:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_XOR_I32:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 4, Mips::XOR);
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
case Mips::ATOMIC_LOAD_XOR_I64:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_NAND_I8:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_NAND_I16:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_NAND_I32:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 4, 0, true);
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
case Mips::ATOMIC_LOAD_NAND_I64:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 8, 0, true);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_SUB_I8:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_SUB_I16:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_LOAD_SUB_I32:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
case Mips::ATOMIC_LOAD_SUB_I64:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_SWAP_I8:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 1, 0);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_SWAP_I16:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinaryPartword(MI, BB, 2, 0);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_SWAP_I32:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 4, 0);
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
case Mips::ATOMIC_SWAP_I64:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicBinary(MI, BB, 8, 0);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_CMP_SWAP_I8:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicCmpSwapPartword(MI, BB, 1);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_CMP_SWAP_I16:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicCmpSwapPartword(MI, BB, 2);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
case Mips::ATOMIC_CMP_SWAP_I32:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicCmpSwap(MI, BB, 4);
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
case Mips::ATOMIC_CMP_SWAP_I64:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return emitAtomicCmpSwap(MI, BB, 8);
[mips] Trap on integer division by zero. By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. llvm-svn: 182306
2013-05-21 02:07:43 +08:00
case Mips::PseudoSDIV:
case Mips::PseudoUDIV:
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
case Mips::DIV:
case Mips::DIVU:
case Mips::MOD:
case Mips::MODU:
return insertDivByZeroTrap(MI, *BB, *getTargetMachine().getInstrInfo(),
false);
[mips] Trap on integer division by zero. By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. llvm-svn: 182306
2013-05-21 02:07:43 +08:00
case Mips::PseudoDSDIV:
case Mips::PseudoDUDIV:
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
case Mips::DDIV:
case Mips::DDIVU:
case Mips::DMOD:
case Mips::DMODU:
return insertDivByZeroTrap(MI, *BB, *getTargetMachine().getInstrInfo(),
true);
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
case Mips::SEL_D:
return emitSEL_D(MI, BB);
Refactor MipsTargetLowering::EmitInstrWithCustomInserter. llvm-svn: 132726
2011-06-08 03:28:39 +08:00
}
}
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
MachineBasicBlock *
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
Add a parameter to CCState so that it can access the MachineFunction. No functional change. Part of PR6965 llvm-svn: 132763
2011-06-09 07:55:35 +08:00
unsigned Size, unsigned BinOpcode,
Coding style fixes. - Fix indentation. - Move comments. - Fit lines in 80 columns. - Remove dead code. llvm-svn: 132724
2011-06-08 02:58:42 +08:00
bool Nand) const {
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
DebugLoc DL = MI->getDebugLoc();
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
unsigned LL, SC, AND, NOR, ZERO, BEQ;
if (Size == 4) {
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
if (isMicroMips) {
LL = Mips::LL_MM;
SC = Mips::SC_MM;
} else {
LL = Subtarget->hasMips32r6() ? Mips::LL : Mips::LL_R6;
SC = Subtarget->hasMips32r6() ? Mips::SC : Mips::SC_R6;
}
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
AND = Mips::AND;
NOR = Mips::NOR;
ZERO = Mips::ZERO;
BEQ = Mips::BEQ;
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
} else {
LL = Subtarget->hasMips64r6() ? Mips::LLD : Mips::LLD_R6;
SC = Subtarget->hasMips64r6() ? Mips::SCD : Mips::SCD_R6;
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
AND = Mips::AND64;
NOR = Mips::NOR64;
ZERO = Mips::ZERO_64;
BEQ = Mips::BEQ64;
}
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
unsigned OldVal = MI->getOperand(0).getReg();
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
unsigned Ptr = MI->getOperand(1).getReg();
unsigned Incr = MI->getOperand(2).getReg();
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
unsigned StoreVal = RegInfo.createVirtualRegister(RC);
unsigned AndRes = RegInfo.createVirtualRegister(RC);
unsigned Success = RegInfo.createVirtualRegister(RC);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// insert new blocks after the current block
const BasicBlock *LLVM_BB = BB->getBasicBlock();
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
MachineFunction::iterator It = BB;
++It;
MF->insert(It, loopMBB);
MF->insert(It, exitMBB);
// Transfer the remainder of BB and its successor edges to exitMBB.
exitMBB->splice(exitMBB->begin(), BB,
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev. Remove the old functions. llvm-svn: 202636
2014-03-02 20:27:27 +08:00
std::next(MachineBasicBlock::iterator(MI)), BB->end());
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
// thisMBB:
// ...
// fallthrough --> loopMBB
BB->addSuccessor(loopMBB);
Separate code that modifies control flow from code that adds instruction to basic blocks. llvm-svn: 135490
2011-07-20 01:09:53 +08:00
loopMBB->addSuccessor(loopMBB);
loopMBB->addSuccessor(exitMBB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// loopMBB:
// ll oldval, 0(ptr)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// <binop> storeval, oldval, incr
// sc success, storeval, 0(ptr)
// beq success, $0, loopMBB
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
BB = loopMBB;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
if (Nand) {
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// and andres, oldval, incr
// nor storeval, $0, andres
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
} else if (BinOpcode) {
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// <binop> storeval, oldval, incr
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
} else {
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
StoreVal = Incr;
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
MI->eraseFromParent(); // The instruction is gone now.
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
return exitMBB;
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
}
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
unsigned SrcReg) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
DebugLoc DL = MI->getDebugLoc();
if (Subtarget->hasMips32r2() && Size == 1) {
BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
return BB;
}
if (Subtarget->hasMips32r2() && Size == 2) {
BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
return BB;
}
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
unsigned ScrReg = RegInfo.createVirtualRegister(RC);
assert(Size < 32);
int64_t ShiftImm = 32 - (Size * 8);
BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
return BB;
}
MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
bool Nand) const {
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
assert((Size == 1 || Size == 2) &&
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
"Unsupported size for EmitAtomicBinaryPartial.");
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
DebugLoc DL = MI->getDebugLoc();
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
unsigned Dest = MI->getOperand(0).getReg();
unsigned Ptr = MI->getOperand(1).getReg();
unsigned Incr = MI->getOperand(2).getReg();
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
unsigned Mask = RegInfo.createVirtualRegister(RC);
unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
unsigned NewVal = RegInfo.createVirtualRegister(RC);
unsigned OldVal = RegInfo.createVirtualRegister(RC);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
unsigned Incr2 = RegInfo.createVirtualRegister(RC);
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
unsigned AndRes = RegInfo.createVirtualRegister(RC);
unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
Change variable name. llvm-svn: 135522
2011-07-20 04:56:53 +08:00
unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
unsigned StoreVal = RegInfo.createVirtualRegister(RC);
unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
unsigned SrlRes = RegInfo.createVirtualRegister(RC);
unsigned Success = RegInfo.createVirtualRegister(RC);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// insert new blocks after the current block
const BasicBlock *LLVM_BB = BB->getBasicBlock();
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
MachineFunction::iterator It = BB;
++It;
MF->insert(It, loopMBB);
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
MF->insert(It, sinkMBB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
MF->insert(It, exitMBB);
// Transfer the remainder of BB and its successor edges to exitMBB.
exitMBB->splice(exitMBB->begin(), BB,
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev. Remove the old functions. llvm-svn: 202636
2014-03-02 20:27:27 +08:00
std::next(MachineBasicBlock::iterator(MI)), BB->end());
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
Separate code that modifies control flow from code that adds instruction to basic blocks. llvm-svn: 135490
2011-07-20 01:09:53 +08:00
BB->addSuccessor(loopMBB);
loopMBB->addSuccessor(loopMBB);
loopMBB->addSuccessor(sinkMBB);
sinkMBB->addSuccessor(exitMBB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// thisMBB:
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// addiu masklsb2,$0,-4 # 0xfffffffc
// and alignedaddr,ptr,masklsb2
// andi ptrlsb2,ptr,3
// sll shiftamt,ptrlsb2,3
// ori maskupper,$0,255 # 0xff
// sll mask,maskupper,shiftamt
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// nor mask2,$0,mask
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// sll incr2,incr,shiftamt
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
int64_t MaskImm = (Size == 1) ? 255 : 65535;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(Mips::ZERO).addImm(-4);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(Ptr).addReg(MaskLSB2);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
[mips] Big-endian code generation for atomic instructions. Patch by Jyun-Yan You. llvm-svn: 182984
2013-05-31 11:25:44 +08:00
if (Subtarget->isLittle()) {
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
} else {
unsigned Off = RegInfo.createVirtualRegister(RC);
BuildMI(BB, DL, TII->get(Mips::XORi), Off)
.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(Mips::ZERO).addImm(MaskImm);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
[mips] Reverse the order of source operands of shift and rotate instructions that have three register operands. No intended functionality changes. llvm-svn: 185376
2013-07-02 04:39:53 +08:00
.addReg(MaskUpper).addReg(ShiftAmt);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
[mips] Reverse the order of source operands of shift and rotate instructions that have three register operands. No intended functionality changes. llvm-svn: 185376
2013-07-02 04:39:53 +08:00
BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
Fix uninitialized variables and silence warnings llvm-svn: 132355
2011-06-01 04:25:26 +08:00
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. llvm-svn: 135415
2011-07-19 02:52:12 +08:00
// atomic.load.binop
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// loopMBB:
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// ll oldval,0(alignedaddr)
// binop binopres,oldval,incr2
// and newval,binopres,mask
// and maskedoldval0,oldval,mask2
// or storeval,maskedoldval0,newval
// sc success,storeval,0(alignedaddr)
// beq success,$0,loopMBB
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. llvm-svn: 135415
2011-07-19 02:52:12 +08:00
// atomic.swap
// loopMBB:
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// ll oldval,0(alignedaddr)
Remove redundant instructions. - In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the instruction being expanded, instead of masking it in thisMBB. - Remove redundant Or in EmitAtomicCmpSwap. llvm-svn: 135495
2011-07-20 02:14:26 +08:00
// and newval,incr2,mask
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// and maskedoldval0,oldval,mask2
// or storeval,maskedoldval0,newval
// sc success,storeval,0(alignedaddr)
// beq success,$0,loopMBB
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. llvm-svn: 135415
2011-07-19 02:52:12 +08:00
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
BB = loopMBB;
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. llvm-svn: 188830
2013-08-21 05:08:22 +08:00
BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
if (Nand) {
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// and andres, oldval, incr2
// nor binopres, $0, andres
// and newval, binopres, mask
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(Mips::ZERO).addReg(AndRes);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
} else if (BinOpcode) {
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// <binop> binopres, oldval, incr2
// and newval, binopres, mask
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
} else { // atomic.swap
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// and newval, incr2, mask
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
Remove redundant instructions. - In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the instruction being expanded, instead of masking it in thisMBB. - Remove redundant Or in EmitAtomicCmpSwap. llvm-svn: 135495
2011-07-20 02:14:26 +08:00
}
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(OldVal).addReg(Mask2);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
Change variable name. llvm-svn: 135522
2011-07-20 04:56:53 +08:00
.addReg(MaskedOldVal0).addReg(NewVal);
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. llvm-svn: 188830
2013-08-21 05:08:22 +08:00
BuildMI(BB, DL, TII->get(Mips::SC), Success)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::BEQ))
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
// sinkMBB:
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// and maskedoldval1,oldval,mask
// srl srlres,maskedoldval1,shiftamt
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
// sign_extend dest,srlres
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
BB = sinkMBB;
Do not insert instructions in reverse order. llvm-svn: 135464
2011-07-19 11:14:58 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(OldVal).addReg(Mask);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
[mips] Reverse the order of source operands of shift and rotate instructions that have three register operands. No intended functionality changes. llvm-svn: 185376
2013-07-02 04:39:53 +08:00
.addReg(MaskedOldVal1).addReg(ShiftAmt);
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
MI->eraseFromParent(); // The instruction is gone now.
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
return exitMBB;
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
}
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
MachineBasicBlock *BB,
unsigned Size) const {
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
DebugLoc DL = MI->getDebugLoc();
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
unsigned LL, SC, ZERO, BNE, BEQ;
if (Size == 4) {
Support for microMIPS LL and SC instructions. llvm-svn: 197692
2013-12-20 00:12:56 +08:00
LL = isMicroMips ? Mips::LL_MM : Mips::LL;
SC = isMicroMips ? Mips::SC_MM : Mips::SC;
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
ZERO = Mips::ZERO;
BNE = Mips::BNE;
BEQ = Mips::BEQ;
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
} else {
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. llvm-svn: 188830
2013-08-21 05:08:22 +08:00
LL = Mips::LLD;
SC = Mips::SCD;
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
ZERO = Mips::ZERO_64;
BNE = Mips::BNE64;
BEQ = Mips::BEQ64;
}
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
unsigned Dest = MI->getOperand(0).getReg();
unsigned Ptr = MI->getOperand(1).getReg();
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
unsigned OldVal = MI->getOperand(2).getReg();
unsigned NewVal = MI->getOperand(3).getReg();
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
unsigned Success = RegInfo.createVirtualRegister(RC);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// insert new blocks after the current block
const BasicBlock *LLVM_BB = BB->getBasicBlock();
MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
MachineFunction::iterator It = BB;
++It;
MF->insert(It, loop1MBB);
MF->insert(It, loop2MBB);
MF->insert(It, exitMBB);
// Transfer the remainder of BB and its successor edges to exitMBB.
exitMBB->splice(exitMBB->begin(), BB,
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev. Remove the old functions. llvm-svn: 202636
2014-03-02 20:27:27 +08:00
std::next(MachineBasicBlock::iterator(MI)), BB->end());
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
// thisMBB:
// ...
// fallthrough --> loop1MBB
BB->addSuccessor(loop1MBB);
Separate code that modifies control flow from code that adds instruction to basic blocks. llvm-svn: 135490
2011-07-20 01:09:53 +08:00
loop1MBB->addSuccessor(exitMBB);
loop1MBB->addSuccessor(loop2MBB);
loop2MBB->addSuccessor(loop1MBB);
loop2MBB->addSuccessor(exitMBB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// loop1MBB:
// ll dest, 0(ptr)
// bne dest, oldval, exitMBB
BB = loop1MBB;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
BuildMI(BB, DL, TII->get(BNE))
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(Dest).addReg(OldVal).addMBB(exitMBB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// loop2MBB:
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// sc success, newval, 0(ptr)
// beq success, $0, loop1MBB
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
BB = loop2MBB;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(SC), Success)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(NewVal).addReg(Ptr).addImm(0);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(BEQ))
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
.addReg(Success).addReg(ZERO).addMBB(loop1MBB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
MI->eraseFromParent(); // The instruction is gone now.
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
return exitMBB;
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
}
MachineBasicBlock *
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
Coding style fixes. - Fix indentation. - Move comments. - Fit lines in 80 columns. - Remove dead code. llvm-svn: 132724
2011-06-08 02:58:42 +08:00
MachineBasicBlock *BB,
unsigned Size) const {
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
assert((Size == 1 || Size == 2) &&
"Unsupported size for EmitAtomicCmpSwapPartial.");
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
DebugLoc DL = MI->getDebugLoc();
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
unsigned Dest = MI->getOperand(0).getReg();
unsigned Ptr = MI->getOperand(1).getReg();
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
unsigned CmpVal = MI->getOperand(2).getReg();
unsigned NewVal = MI->getOperand(3).getReg();
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
unsigned Mask = RegInfo.createVirtualRegister(RC);
unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
unsigned OldVal = RegInfo.createVirtualRegister(RC);
unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
unsigned StoreVal = RegInfo.createVirtualRegister(RC);
unsigned SrlRes = RegInfo.createVirtualRegister(RC);
unsigned Success = RegInfo.createVirtualRegister(RC);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// insert new blocks after the current block
const BasicBlock *LLVM_BB = BB->getBasicBlock();
MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
MachineFunction::iterator It = BB;
++It;
MF->insert(It, loop1MBB);
MF->insert(It, loop2MBB);
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
MF->insert(It, sinkMBB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
MF->insert(It, exitMBB);
// Transfer the remainder of BB and its successor edges to exitMBB.
exitMBB->splice(exitMBB->begin(), BB,
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev. Remove the old functions. llvm-svn: 202636
2014-03-02 20:27:27 +08:00
std::next(MachineBasicBlock::iterator(MI)), BB->end());
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
Separate code that modifies control flow from code that adds instruction to basic blocks. llvm-svn: 135490
2011-07-20 01:09:53 +08:00
BB->addSuccessor(loop1MBB);
loop1MBB->addSuccessor(sinkMBB);
loop1MBB->addSuccessor(loop2MBB);
loop2MBB->addSuccessor(loop1MBB);
loop2MBB->addSuccessor(sinkMBB);
sinkMBB->addSuccessor(exitMBB);
Remove redundant instructions. - In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the instruction being expanded, instead of masking it in thisMBB. - Remove redundant Or in EmitAtomicCmpSwap. llvm-svn: 135495
2011-07-20 02:14:26 +08:00
// FIXME: computation of newval2 can be moved to loop2MBB.
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// thisMBB:
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// addiu masklsb2,$0,-4 # 0xfffffffc
// and alignedaddr,ptr,masklsb2
// andi ptrlsb2,ptr,3
// sll shiftamt,ptrlsb2,3
// ori maskupper,$0,255 # 0xff
// sll mask,maskupper,shiftamt
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// nor mask2,$0,mask
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// andi maskedcmpval,cmpval,255
// sll shiftedcmpval,maskedcmpval,shiftamt
// andi maskednewval,newval,255
// sll shiftednewval,maskednewval,shiftamt
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
int64_t MaskImm = (Size == 1) ? 255 : 65535;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(Mips::ZERO).addImm(-4);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(Ptr).addReg(MaskLSB2);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
[mips] Big-endian code generation for atomic instructions. Patch by Jyun-Yan You. llvm-svn: 182984
2013-05-31 11:25:44 +08:00
if (Subtarget->isLittle()) {
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
} else {
unsigned Off = RegInfo.createVirtualRegister(RC);
BuildMI(BB, DL, TII->get(Mips::XORi), Off)
.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(Mips::ZERO).addImm(MaskImm);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
[mips] Reverse the order of source operands of shift and rotate instructions that have three register operands. No intended functionality changes. llvm-svn: 185376
2013-07-02 04:39:53 +08:00
.addReg(MaskUpper).addReg(ShiftAmt);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(CmpVal).addImm(MaskImm);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
[mips] Reverse the order of source operands of shift and rotate instructions that have three register operands. No intended functionality changes. llvm-svn: 185376
2013-07-02 04:39:53 +08:00
.addReg(MaskedCmpVal).addReg(ShiftAmt);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(NewVal).addImm(MaskImm);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
[mips] Reverse the order of source operands of shift and rotate instructions that have three register operands. No intended functionality changes. llvm-svn: 185376
2013-07-02 04:39:53 +08:00
.addReg(MaskedNewVal).addReg(ShiftAmt);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// loop1MBB:
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// ll oldval,0(alginedaddr)
// and maskedoldval0,oldval,mask
// bne maskedoldval0,shiftedcmpval,sinkMBB
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
BB = loop1MBB;
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. llvm-svn: 188830
2013-08-21 05:08:22 +08:00
BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(OldVal).addReg(Mask);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::BNE))
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
// loop2MBB:
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// and maskedoldval1,oldval,mask2
// or storeval,maskedoldval1,shiftednewval
// sc success,storeval,0(alignedaddr)
// beq success,$0,loop1MBB
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
BB = loop2MBB;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(OldVal).addReg(Mask2);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(MaskedOldVal1).addReg(ShiftedNewVal);
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. llvm-svn: 188830
2013-08-21 05:08:22 +08:00
BuildMI(BB, DL, TII->get(Mips::SC), Success)
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::BEQ))
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
.addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
// sinkMBB:
Use descriptive variable names. llvm-svn: 135514
2011-07-20 04:11:17 +08:00
// srl srlres,maskedoldval0,shiftamt
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
// sign_extend dest,srlres
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
BB = sinkMBB;
Do not insert instructions in reverse order. llvm-svn: 135464
2011-07-19 11:14:58 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
[mips] Reverse the order of source operands of shift and rotate instructions that have three register operands. No intended functionality changes. llvm-svn: 185376
2013-07-02 04:39:53 +08:00
.addReg(MaskedOldVal0).addReg(ShiftAmt);
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
MI->eraseFromParent(); // The instruction is gone now.
Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
2011-07-19 11:42:13 +08:00
return exitMBB;
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
}
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI,
MachineBasicBlock *BB) const {
MachineFunction *MF = BB->getParent();
const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
DebugLoc DL = MI->getDebugLoc();
MachineBasicBlock::iterator II(MI);
unsigned Fc = MI->getOperand(1).getReg();
const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
.addImm(0)
.addReg(Fc)
.addImm(Mips::sub_lo);
// We don't erase the original instruction, we just replace the condition
// register with the 64-bit super-register.
MI->getOperand(1).setReg(Fc2);
return BB;
}
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Misc Lower Operation implementation
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
[mips] Custom-legalize BR_JT. In N64-static, GOT address is needed to compute the branch address. llvm-svn: 176580
2013-03-07 05:32:03 +08:00
SDValue Chain = Op.getOperand(0);
SDValue Table = Op.getOperand(1);
SDValue Index = Op.getOperand(2);
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
[mips] Custom-legalize BR_JT. In N64-static, GOT address is needed to compute the branch address. llvm-svn: 176580
2013-03-07 05:32:03 +08:00
EVT PTy = getPointerTy();
unsigned EntrySize =
DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
DAG.getConstant(EntrySize, PTy));
SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
MachinePointerInfo::getJumpTable(), MemVT, false, false,
0);
Chain = Addr.getValue(1);
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) ||
Subtarget->isABI_N64()) {
[mips] Custom-legalize BR_JT. In N64-static, GOT address is needed to compute the branch address. llvm-svn: 176580
2013-03-07 05:32:03 +08:00
// For PIC, the sequence is:
// BRIND(load(Jumptable + index) + RelocBase)
// RelocBase can be JumpTable, GOT or some sort of global base.
Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
getPICJumpTableRelocBase(Table, DAG));
}
return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
}
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// The first operand is the chain, the second is the condition, the third is
Added floating point lowering for setcc and brcond. Fixed COMM asm directive usage. ConstantPool using custom FourByteConstantSection. llvm-svn: 54139
2008-07-29 03:11:24 +08:00
// the block to branch to if the condition is true.
SDValue Chain = Op.getOperand(0);
SDValue Dest = Op.getOperand(2);
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
Handle more SELECT corner cases considering legalize types, probabily wont work with the default legalizer. llvm-svn: 54249
2008-08-01 02:31:28 +08:00
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
assert(!Subtarget->hasMips32r6() && !Subtarget->hasMips64r6());
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
Fix a ton of comment typos found by codespell. Patch by Luis Felipe Strano Moraes! llvm-svn: 129558
2011-04-15 13:18:47 +08:00
// Return if flag is not set by a floating point comparison.
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
if (CondRes.getOpcode() != MipsISD::FPCmp)
Fixed bug in global address lowering for functions and in Brcond lowering llvm-svn: 54215
2008-07-31 01:06:13 +08:00
return Op;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Handle more SELECT corner cases considering legalize types, probabily wont work with the default legalizer. llvm-svn: 54249
2008-08-01 02:31:28 +08:00
SDValue CCNode = CondRes.getOperand(2);
Rename ConstantSDNode::getValue to getZExtValue, for consistency with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
2008-09-13 00:56:44 +08:00
Mips::CondCode CC =
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
[mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd. llvm-svn: 178396
2013-03-30 09:16:38 +08:00
unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
[mips] Fix FP branch instructions to have explicit FP condition code register operands. llvm-svn: 187238
2013-07-27 04:13:47 +08:00
SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
[mips] Fix FP branch instructions to have explicit FP condition code register operands. llvm-svn: 187238
2013-07-27 04:13:47 +08:00
FCC0, Dest, CondRes);
Added floating point lowering for setcc and brcond. Fixed COMM asm directive usage. ConstantPool using custom FourByteConstantSection. llvm-svn: 54139
2008-07-29 03:11:24 +08:00
}
Added floating point lowering for select. llvm-svn: 54167
2008-07-30 03:05:28 +08:00
SDValue MipsTargetLowering::
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
lowerSELECT(SDValue Op, SelectionDAG &DAG) const
Added floating point lowering for select. llvm-svn: 54167
2008-07-30 03:05:28 +08:00
{
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
assert(!Subtarget->hasMips32r6() && !Subtarget->hasMips64r6());
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
Added floating point lowering for select. llvm-svn: 54167
2008-07-30 03:05:28 +08:00
Fix a ton of comment typos found by codespell. Patch by Luis Felipe Strano Moraes! llvm-svn: 129558
2011-04-15 13:18:47 +08:00
// Return if flag is not set by a floating point comparison.
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
if (Cond.getOpcode() != MipsISD::FPCmp)
return Op;
Removed SELECT_CC custom lowering. This is not needed anymore, the SELECT node is lowered properly and covers everything LowerSELECT_CC did. Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This avoid the ugly instruction by instruction checking in printOperand. Added a swap instruction present in the allegrex core. Added two conditional instructions present in the allegrex core : MOVZ and MOVN. They both allow a more efficient SELECT operation for integers. Also added SELECT patterns to optimize MOVZ and MOVN usage. The brcond and setcc patterns were cleaned: redundant and suboptimal patterns were removed. The suboptimals were replaced by more efficient ones. Fixed some instructions that were using immZExt16 instead of immSExt16. llvm-svn: 54724
2008-08-13 15:13:40 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc(Op));
Added floating point lowering for select. llvm-svn: 54167
2008-07-30 03:05:28 +08:00
}
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. llvm-svn: 160064
2012-07-12 03:32:27 +08:00
SDValue MipsTargetLowering::
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. llvm-svn: 160064
2012-07-12 03:32:27 +08:00
{
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. llvm-svn: 160064
2012-07-12 03:32:27 +08:00
EVT Ty = Op.getOperand(0).getValueType();
Add LLVMContext argument to getSetCCResultType llvm-svn: 182180
2013-05-18 08:21:46 +08:00
SDValue Cond = DAG.getNode(ISD::SETCC, DL,
getSetCCResultType(*DAG.getContext(), Ty),
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. llvm-svn: 160064
2012-07-12 03:32:27 +08:00
Op.getOperand(0), Op.getOperand(1),
Op.getOperand(4));
return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
Op.getOperand(3));
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
assert(!Subtarget->hasMips32r6() && !Subtarget->hasMips64r6());
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue Cond = createFPCmp(DAG, Op);
Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass. llvm-svn: 152450
2012-03-10 07:46:03 +08:00
assert(Cond.getOpcode() == MipsISD::FPCmp &&
"Floating point operand expected.");
SDValue True = DAG.getConstant(1, MVT::i32);
SDValue False = DAG.getConstant(0, MVT::i32);
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass. llvm-svn: 152450
2012-03-10 07:46:03 +08:00
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
Use const qualifiers with TargetLowering. This eliminates several const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
2010-04-17 23:26:15 +08:00
SelectionDAG &DAG) const {
Remove more non-DebugLoc versions of getNode. llvm-svn: 63969
2009-02-07 05:50:26 +08:00
// FIXME there isn't actually debug info here
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
EVT Ty = Op.getValueType();
GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
const GlobalValue *GV = N->getGlobal();
Changed some methods order. llvm-svn: 54169
2008-07-30 03:29:50 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
!Subtarget->isABI_N64()) {
Misc. 1. Remove RA from list of allocatable registers 2. Enable d,y,r constraint inline assembly instructions Patch by Reed Kotler. llvm-svn: 163753
2012-09-13 07:27:55 +08:00
const MipsTargetObjectFile &TLOF =
(const MipsTargetObjectFile&)getObjFileLowering();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Restore some "small section" support code, reverting my patch from r76936. llvm-svn: 78894
2009-08-13 13:41:27 +08:00
// %gp_rel relocation
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
Reapply 80278 Add MO flags to simplify the printing of relocations. Remove the support for printing large code model relocs (which aren't supported anyway). llvm-svn: 80691
2009-09-02 01:27:58 +08:00
MipsII::MO_GPREL);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL,
Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>. llvm-svn: 207327
2014-04-27 02:35:24 +08:00
DAG.getVTList(MVT::i32), GA);
Add register Mips::GP to the list of reserved registers if target is bare-metal to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. llvm-svn: 162340
2012-08-22 11:18:13 +08:00
SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
Restore some "small section" support code, reverting my patch from r76936. llvm-svn: 78894
2009-08-13 13:41:27 +08:00
}
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. llvm-svn: 168458
2012-11-22 04:30:40 +08:00
Changed some methods order. llvm-svn: 54169
2008-07-30 03:29:50 +08:00
// %hi/%lo relocation
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
return getAddrNonPIC(N, Ty, DAG);
Changed some methods order. llvm-svn: 54169
2008-07-30 03:29:50 +08:00
}
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. llvm-svn: 168458
2012-11-22 04:30:40 +08:00
if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
return getAddrLocal(N, Ty, DAG,
Subtarget->isABI_N32() || Subtarget->isABI_N64());
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. llvm-svn: 168458
2012-11-22 04:30:40 +08:00
[mips] Generate big GOT code. llvm-svn: 168460
2012-11-22 04:40:38 +08:00
if (LargeGOT)
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16,
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
2013-09-28 08:12:32 +08:00
MipsII::MO_GOT_LO16, DAG.getEntryNode(),
MachinePointerInfo::getGOT());
[mips] Generate big GOT code. llvm-svn: 168460
2012-11-22 04:40:38 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
return getAddrGlobal(N, Ty, DAG,
(Subtarget->isABI_N32() || Subtarget->isABI_N64())
? MipsII::MO_GOT_DISP
: MipsII::MO_GOT16,
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
2013-09-28 08:12:32 +08:00
DAG.getEntryNode(), MachinePointerInfo::getGOT());
Changed some methods order. llvm-svn: 54169
2008-07-30 03:29:50 +08:00
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka llvm-svn: 127027
2011-03-05 04:01:52 +08:00
SelectionDAG &DAG) const {
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
EVT Ty = Op.getValueType();
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
!Subtarget->isABI_N64())
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
return getAddrNonPIC(N, Ty, DAG);
Lower BlockAddress node when relocation-model is static. llvm-svn: 130131
2011-04-26 01:10:45 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
return getAddrLocal(N, Ty, DAG,
Subtarget->isABI_N32() || Subtarget->isABI_N64());
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka llvm-svn: 127027
2011-03-05 04:01:52 +08:00
}
Changed some methods order. llvm-svn: 54169
2008-07-30 03:29:50 +08:00
SDValue MipsTargetLowering::
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Changed some methods order. llvm-svn: 54169
2008-07-30 03:29:50 +08:00
{
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object emission is not supported yet, but a patch that adds the support should follow soon. llvm-svn: 146572
2011-12-15 02:26:41 +08:00
// If the relocation model is PIC, use the General Dynamic TLS Model or
// Local Dynamic TLS model, otherwise use the Initial Exec or
// Local Exec TLS Model.
This patch implements the thread local storage. Implemented are General Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
2011-05-31 10:53:58 +08:00
GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(GA);
This patch implements the thread local storage. Implemented are General Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
2011-05-31 10:53:58 +08:00
const GlobalValue *GV = GA->getGlobal();
EVT PtrVT = getPointerTy();
Make ARM and Mips use TargetMachine::getTLSModel() This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). llvm-svn: 156162
2012-05-04 17:40:39 +08:00
TLSModel::Model model = getTargetMachine().getTLSModel(GV);
if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
MIPS TLS: use the model selected by TargetMachine::getTLSModel(). This was mostly done already in r156162, but I missed one place. llvm-svn: 157929
2012-06-04 22:02:08 +08:00
// General Dynamic and Local Dynamic TLS Model.
unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
: MipsII::MO_TLSGD;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
getGlobalReg(DAG, PtrVT), TGA);
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the target is Mips64. llvm-svn: 146183
2011-12-09 05:05:38 +08:00
unsigned PtrSize = PtrVT.getSizeInBits();
IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
Mips: Don't create a dangling IR function just to get the address of a symbol. llvm-svn: 146340
2011-12-11 20:21:34 +08:00
SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
This patch implements the thread local storage. Implemented are General Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
2011-05-31 10:53:58 +08:00
ArgListTy Args;
ArgListEntry Entry;
Entry.Node = Argument;
Implement 64-bit support for thread local storage handling. - Modify lowering of global TLS address nodes. - Modify isel of ThreadPointer. - Wrap target global TLS address nodes that are operands of loads with WrapperPIC. - Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be substituted with other existing nodes. llvm-svn: 146175
2011-12-09 04:34:32 +08:00
Entry.Ty = PtrTy;
This patch implements the thread local storage. Implemented are General Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
2011-05-31 10:53:58 +08:00
Args.push_back(Entry);
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
Target: remove old constructors for CallLoweringInfo This is mostly a mechanical change changing all the call sites to the newer chained-function construction pattern. This removes the horrible 15-parameter constructor for the CallLoweringInfo in favour of setting properties of the call via chained functions. No functional change beyond the removal of the old constructors are intended. llvm-svn: 209082
2014-05-18 05:50:17 +08:00
TargetLowering::CallLoweringInfo CLI(DAG);
CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
[DAG] Pass the argument list to the CallLoweringInfo via move semantics. NFCI. The argument list vector is never used after it has been passed to the CallLoweringInfo and moving it to the CallLoweringInfo is cleaner and pretty much as cheap as keeping a pointer to it. llvm-svn: 212135
2014-07-02 06:01:54 +08:00
.setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
2012-05-26 00:35:28 +08:00
std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
This patch implements the thread local storage. Implemented are General Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
2011-05-31 10:53:58 +08:00
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object emission is not supported yet, but a patch that adds the support should follow soon. llvm-svn: 146572
2011-12-15 02:26:41 +08:00
SDValue Ret = CallResult.first;
Make ARM and Mips use TargetMachine::getTLSModel() This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). llvm-svn: 156162
2012-05-04 17:40:39 +08:00
if (model != TLSModel::LocalDynamic)
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object emission is not supported yet, but a patch that adds the support should follow soon. llvm-svn: 146572
2011-12-15 02:26:41 +08:00
return Ret;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object emission is not supported yet, but a patch that adds the support should follow soon. llvm-svn: 146572
2011-12-15 02:26:41 +08:00
MipsII::MO_DTPREL_HI);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object emission is not supported yet, but a patch that adds the support should follow soon. llvm-svn: 146572
2011-12-15 02:26:41 +08:00
MipsII::MO_DTPREL_LO);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
Coding style fixes. llvm-svn: 133496
2011-06-21 09:02:03 +08:00
}
This patch implements the thread local storage. Implemented are General Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
2011-05-31 10:53:58 +08:00
Coding style fixes. llvm-svn: 133496
2011-06-21 09:02:03 +08:00
SDValue Offset;
Make ARM and Mips use TargetMachine::getTLSModel() This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). llvm-svn: 156162
2012-05-04 17:40:39 +08:00
if (model == TLSModel::InitialExec) {
Coding style fixes. llvm-svn: 133496
2011-06-21 09:02:03 +08:00
// Initial Exec TLS Model
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
Coding style fixes. llvm-svn: 133496
2011-06-21 09:02:03 +08:00
MipsII::MO_GOTTPREL);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
Add an option to use a virtual register as the global base register instead of reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
2012-02-25 06:34:47 +08:00
TGA);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
Offset = DAG.getLoad(PtrVT, DL,
Coding style fixes. llvm-svn: 133496
2011-06-21 09:02:03 +08:00
DAG.getEntryNode(), TGA, MachinePointerInfo(),
Added invariant field to the DAG.getLoad method and changed all calls. When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
2011-11-09 02:42:53 +08:00
false, false, false, 0);
Coding style fixes. llvm-svn: 133496
2011-06-21 09:02:03 +08:00
} else {
// Local Exec TLS Model
Make ARM and Mips use TargetMachine::getTLSModel() This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). llvm-svn: 156162
2012-05-04 17:40:39 +08:00
assert(model == TLSModel::LocalExec);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
Coding style fixes. llvm-svn: 133496
2011-06-21 09:02:03 +08:00
MipsII::MO_TPREL_HI);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
Coding style fixes. llvm-svn: 133496
2011-06-21 09:02:03 +08:00
MipsII::MO_TPREL_LO);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
This patch implements the thread local storage. Implemented are General Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
2011-05-31 10:53:58 +08:00
}
Coding style fixes. llvm-svn: 133496
2011-06-21 09:02:03 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
Changed some methods order. llvm-svn: 54169
2008-07-30 03:29:50 +08:00
}
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue MipsTargetLowering::
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Added JumpTable support Fixed some AsmPrinter issues Added GLOBAL_OFFSET_TABLE Node handle. llvm-svn: 44024
2007-11-13 03:49:57 +08:00
{
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
EVT Ty = Op.getValueType();
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
!Subtarget->isABI_N64())
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
return getAddrNonPIC(N, Ty, DAG);
Added JumpTable support Fixed some AsmPrinter issues Added GLOBAL_OFFSET_TABLE Node handle. llvm-svn: 44024
2007-11-13 03:49:57 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
return getAddrLocal(N, Ty, DAG,
Subtarget->isABI_N32() || Subtarget->isABI_N64());
Added JumpTable support Fixed some AsmPrinter issues Added GLOBAL_OFFSET_TABLE Node handle. llvm-svn: 44024
2007-11-13 03:49:57 +08:00
}
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue MipsTargetLowering::
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
MipsTargetLowering cleanup llvm-svn: 53270
2008-07-09 12:15:08 +08:00
{
Minor fixes. Added ConstantPool support. llvm-svn: 53951
2008-07-24 00:01:50 +08:00
// gp_rel relocation
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// FIXME: we should reference the constant pool using small data sections,
Fix a ton of comment typos found by codespell. Patch by Luis Felipe Strano Moraes! llvm-svn: 129558
2011-04-15 13:18:47 +08:00
// but the asm printer currently doesn't support this feature without
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// hacking it. This feature should come soon so we can uncomment the
Disable gp_rel relocation for constant pools access for now. llvm-svn: 54142
2008-07-29 03:26:25 +08:00
// stuff below.
Remove -disable-mips-abicall and -enable-mips-absolute-call command-line options, which don't appear to be useful. -enable-mips-absolute-call is completely unused (and unless I'm mistaken, is supposed to have the same effect that -relocation-model=dynamic-no-pic should have), and -disable-mips-abicall appears to be effectively a synonym for -relocation-model=static. Adjust the few users of hasABICall to checks which seem more appropriate. Update MipsSubtarget, MipsTargetMachine, and MipselTargetMachine to synchronize with recent changes. llvm-svn: 77938
2009-08-03 10:22:28 +08:00
//if (IsInSmallSection(C->getType())) {
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
// SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
// SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
EVT Ty = Op.getValueType();
Support PIC loading of constant pool entries llvm-svn: 89863
2009-11-25 20:17:58 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
!Subtarget->isABI_N64())
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
return getAddrNonPIC(N, Ty, DAG);
Minor fixes. Added ConstantPool support. llvm-svn: 53951
2008-07-24 00:01:50 +08:00
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
return getAddrLocal(N, Ty, DAG,
Subtarget->isABI_N32() || Subtarget->isABI_N64());
MipsTargetLowering cleanup llvm-svn: 53270
2008-07-09 12:15:08 +08:00
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
Move per-function state out of TargetLowering subclasses and into MachineFunctionInfo subclasses. llvm-svn: 101634
2010-04-17 22:41:14 +08:00
MachineFunction &MF = DAG.getMachineFunction();
MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
Move per-function state out of TargetLowering subclasses and into MachineFunctionInfo subclasses. llvm-svn: 101634
2010-04-17 22:41:14 +08:00
SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
getPointerTy());
Add suport for VASTART on Mips. llvm-svn: 95506
2010-02-07 05:00:02 +08:00
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
Tidy up. Simplify logic. No functional change intended. llvm-svn: 146896
2011-12-20 03:52:25 +08:00
MachinePointerInfo(SV), false, false, 0);
Add suport for VASTART on Mips. llvm-svn: 95506
2010-02-07 05:00:02 +08:00
}
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
[mips] Do not generate INS/EXT nodes if target does not have support for ins/ext. llvm-svn: 192330
2013-10-10 07:36:17 +08:00
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
bool HasExtractInsert) {
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
EVT TyX = Op.getOperand(0).getValueType();
EVT TyY = Op.getOperand(1).getValueType();
SDValue Const1 = DAG.getConstant(1, MVT::i32);
SDValue Const31 = DAG.getConstant(31, MVT::i32);
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
SDValue Res;
// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
// to i32.
SDValue X = (TyX == MVT::f32) ?
DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
Const1);
SDValue Y = (TyY == MVT::f32) ?
DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
Const1);
[mips] Do not generate INS/EXT nodes if target does not have support for ins/ext. llvm-svn: 192330
2013-10-10 07:36:17 +08:00
if (HasExtractInsert) {
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
// ext E, Y, 31, 1 ; extract bit31 of Y
// ins X, E, 31, 1 ; insert extracted bit at bit31 of X
SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
} else {
// sll SllX, X, 1
// srl SrlX, SllX, 1
// srl SrlY, Y, 31
// sll SllY, SrlX, 31
// or Or, SrlX, SllY
SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
}
Custom-lower FCOPYSIGN nodes. llvm-svn: 132074
2011-05-26 03:32:07 +08:00
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
if (TyX == MVT::f32)
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
Add a parameter to CCState so that it can access the MachineFunction. No functional change. Part of PR6965 llvm-svn: 132763
2011-06-09 07:55:35 +08:00
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Op.getOperand(0), DAG.getConstant(0, MVT::i32));
return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
}
Custom-lower FCOPYSIGN nodes. llvm-svn: 132074
2011-05-26 03:32:07 +08:00
[mips] Do not generate INS/EXT nodes if target does not have support for ins/ext. llvm-svn: 192330
2013-10-10 07:36:17 +08:00
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
bool HasExtractInsert) {
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
SDValue Const1 = DAG.getConstant(1, MVT::i32);
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
// Bitcast to integer nodes.
SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
[mips] Do not generate INS/EXT nodes if target does not have support for ins/ext. llvm-svn: 192330
2013-10-10 07:36:17 +08:00
if (HasExtractInsert) {
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
// ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
// ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
DAG.getConstant(WidthY - 1, MVT::i32), Const1);
if (WidthX > WidthY)
E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
else if (WidthY > WidthX)
E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
}
// (d)sll SllX, X, 1
// (d)srl SrlX, SllX, 1
// (d)srl SrlY, Y, width(Y)-1
// (d)sll SllY, SrlX, width(Y)-1
// or Or, SrlX, SllY
SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
DAG.getConstant(WidthY - 1, MVT::i32));
if (WidthX > WidthY)
SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
else if (WidthY > WidthX)
SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
DAG.getConstant(WidthX - 1, MVT::i32));
SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
Custom-lower FCOPYSIGN nodes. llvm-svn: 132074
2011-05-26 03:32:07 +08:00
}
Tidy up. Simplify logic. No functional change intended. llvm-svn: 146896
2011-12-20 03:52:25 +08:00
SDValue
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
[mips] Fix fcopysign for MIPS-IV and add the test. Summary: This was another incorrect use of hasMips64() vs isGP64bit(). Depends on D3344 Reviewers: matheusalmeida, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3347 llvm-svn: 206187
2014-04-15 00:24:12 +08:00
if (Subtarget->isGP64bit())
[mips] Do not generate INS/EXT nodes if target does not have support for ins/ext. llvm-svn: 192330
2013-10-10 07:36:17 +08:00
return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasExtractInsert());
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
[mips] Do not generate INS/EXT nodes if target does not have support for ins/ext. llvm-svn: 192330
2013-10-10 07:36:17 +08:00
return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasExtractInsert());
Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user. Invalid operation is signaled if the operand of these instructions is NaN. llvm-svn: 154545
2012-04-12 06:49:04 +08:00
}
Custom-lower FRAMEADDR. Patch by Sasa Stankovic. llvm-svn: 132444
2011-06-02 08:24:44 +08:00
SDValue MipsTargetLowering::
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
Silence warnings in non assert builds. Patch by David Blaikie llvm-svn: 133118
2011-06-16 08:40:02 +08:00
// check the depth
assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
Coding style fixes. - Fix indentation. - Move comments. - Fit lines in 80 columns. - Remove dead code. llvm-svn: 132724
2011-06-08 02:58:42 +08:00
"Frame address can only be determined for current frame.");
Custom-lower FRAMEADDR. Patch by Sasa Stankovic. llvm-svn: 132444
2011-06-02 08:24:44 +08:00
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
MFI->setFrameAddressIsTaken(true);
EVT VT = Op.getValueType();
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
SDValue FrameAddr =
DAG.getCopyFromReg(DAG.getEntryNode(), DL,
Subtarget->isABI_N64() ? Mips::FP_64 : Mips::FP, VT);
Custom-lower FRAMEADDR. Patch by Sasa Stankovic. llvm-svn: 132444
2011-06-02 08:24:44 +08:00
return FrameAddr;
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
Lower RETURNADDR node in Mips backend. Patch by Sasa Stankovic. llvm-svn: 160031
2012-07-11 08:53:32 +08:00
SelectionDAG &DAG) const {
Refactor function that checks that __builtin_returnaddress's argument is constant. This moves the check up into the parent class so that all targets can use it without having to copy (and keep in sync) the same error message. llvm-svn: 198579
2014-01-06 08:43:20 +08:00
if (verifyReturnAddressArgumentIsConstant(Op, DAG))
Emit an error message if the value passed to __builtin_returnaddress isn't a constant __builtin_returnaddress requires that the value passed into is be a constant. However, at -O0 even a constant expression may not be converted to a constant. Emit an error message intead of crashing. llvm-svn: 198531
2014-01-05 09:47:20 +08:00
return SDValue();
Lower RETURNADDR node in Mips backend. Patch by Sasa Stankovic. llvm-svn: 160031
2012-07-11 08:53:32 +08:00
// check the depth
assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
"Return address can be determined only for current frame.");
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT. Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. This is the second attempt. In the first attempt (r169837), a few getSimpleVT() were hoisted too far, detected by bootstrap failures. llvm-svn: 170104
2012-12-13 14:34:11 +08:00
MVT VT = Op.getSimpleValueType();
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
unsigned RA = Subtarget->isABI_N64() ? Mips::RA_64 : Mips::RA;
Lower RETURNADDR node in Mips backend. Patch by Sasa Stankovic. llvm-svn: 160031
2012-07-11 08:53:32 +08:00
MFI->setReturnAddressIsTaken(true);
// Return RA, which contains the return address. Mark it an implicit live-in.
unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
Lower RETURNADDR node in Mips backend. Patch by Sasa Stankovic. llvm-svn: 160031
2012-07-11 08:53:32 +08:00
}
[mips] Lower EH_RETURN. Patch by Sasa Stankovic. llvm-svn: 173862
2013-01-30 08:26:49 +08:00
// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
// generated from __builtin_eh_return (offset, handler)
// The effect of this is to adjust the stack pointer by "offset"
// and then branch to "handler".
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
[mips] Lower EH_RETURN. Patch by Sasa Stankovic. llvm-svn: 173862
2013-01-30 08:26:49 +08:00
const {
MachineFunction &MF = DAG.getMachineFunction();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
MipsFI->setCallsEhReturn();
SDValue Chain = Op.getOperand(0);
SDValue Offset = Op.getOperand(1);
SDValue Handler = Op.getOperand(2);
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
EVT Ty = Subtarget->isABI_N64() ? MVT::i64 : MVT::i32;
[mips] Lower EH_RETURN. Patch by Sasa Stankovic. llvm-svn: 173862
2013-01-30 08:26:49 +08:00
// Store stack offset in V1, store jump target in V0. Glue CopyToReg and
// EH_RETURN nodes, so that instructions are emitted back-to-back.
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
unsigned OffsetReg = Subtarget->isABI_N64() ? Mips::V1_64 : Mips::V1;
unsigned AddrReg = Subtarget->isABI_N64() ? Mips::V0_64 : Mips::V0;
[mips] Lower EH_RETURN. Patch by Sasa Stankovic. llvm-svn: 173862
2013-01-30 08:26:49 +08:00
Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
DAG.getRegister(OffsetReg, Ty),
DAG.getRegister(AddrReg, getPointerTy()),
Chain.getValue(1));
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
Fix coding style violations. Remove white spaces and tabs. llvm-svn: 158471
2012-06-15 05:10:56 +08:00
SelectionDAG &DAG) const {
Code generation for 'fence' instruction. llvm-svn: 136283
2011-07-28 06:21:52 +08:00
// FIXME: Need pseudo-fence for 'singlethread' fences
// FIXME: Set SType for weaker fences where supported/appropriate.
unsigned SType = 0;
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
Code generation for 'fence' instruction. llvm-svn: 136283
2011-07-28 06:21:52 +08:00
DAG.getConstant(SType, MVT::i32));
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
Fix coding style violations. Remove white spaces and tabs. llvm-svn: 158471
2012-06-15 05:10:56 +08:00
SelectionDAG &DAG) const {
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
Expand 64-bit shifts if target ABI is O32. llvm-svn: 156457
2012-05-09 08:55:21 +08:00
SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
SDValue Shamt = Op.getOperand(2);
// if shamt < 32:
// lo = (shl lo, shamt)
// hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
// else:
// lo = 0
// hi = (shl lo, shamt[4:0])
SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
DAG.getConstant(-1, MVT::i32));
SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
DAG.getConstant(1, MVT::i32));
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
Not);
SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
DAG.getConstant(0x20, MVT::i32));
Fix coding style violations. Remove white spaces and tabs. llvm-svn: 158471
2012-06-15 05:10:56 +08:00
Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
DAG.getConstant(0, MVT::i32), ShiftLeftLo);
Expand 64-bit shifts if target ABI is O32. llvm-svn: 156457
2012-05-09 08:55:21 +08:00
Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
SDValue Ops[2] = {Lo, Hi};
Convert SelectionDAG::getMergeValues to use ArrayRef. llvm-svn: 207374
2014-04-28 03:20:57 +08:00
return DAG.getMergeValues(Ops, DL);
Expand 64-bit shifts if target ABI is O32. llvm-svn: 156457
2012-05-09 08:55:21 +08:00
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
Expand 64-bit shifts if target ABI is O32. llvm-svn: 156457
2012-05-09 08:55:21 +08:00
bool IsSRA) const {
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(Op);
Expand 64-bit shifts if target ABI is O32. llvm-svn: 156457
2012-05-09 08:55:21 +08:00
SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
SDValue Shamt = Op.getOperand(2);
// if shamt < 32:
// lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
// if isSRA:
// hi = (sra hi, shamt)
// else:
// hi = (srl hi, shamt)
// else:
// if isSRA:
// lo = (sra hi, shamt[4:0])
// hi = (sra hi, 31)
// else:
// lo = (srl hi, shamt[4:0])
// hi = 0
SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
DAG.getConstant(-1, MVT::i32));
SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
DAG.getConstant(1, MVT::i32));
SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
Hi, Shamt);
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
DAG.getConstant(0x20, MVT::i32));
SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
DAG.getConstant(31, MVT::i32));
Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
ShiftRightHi);
SDValue Ops[2] = {Lo, Hi};
Convert SelectionDAG::getMergeValues to use ArrayRef. llvm-svn: 207374
2014-04-28 03:20:57 +08:00
return DAG.getMergeValues(Ops, DL);
Expand 64-bit shifts if target ABI is O32. llvm-svn: 156457
2012-05-09 08:55:21 +08:00
}
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp. - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
2013-04-12 03:07:14 +08:00
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
SDValue Chain, SDValue Src, unsigned Offset) {
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp. llvm-svn: 158413
2012-06-14 03:06:08 +08:00
SDValue Ptr = LD->getBasePtr();
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp. llvm-svn: 158413
2012-06-14 03:06:08 +08:00
EVT BasePtrVT = Ptr.getValueType();
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(LD);
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
SDVTList VTList = DAG.getVTList(VT, MVT::Other);
if (Offset)
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp. llvm-svn: 158413
2012-06-14 03:06:08 +08:00
Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
DAG.getConstant(Offset, BasePtrVT));
SDValue Ops[] = { Chain, Ptr, Src };
Convert getMemIntrinsicNode to take ArrayRef of SDValue instead of pointer and size. llvm-svn: 207329
2014-04-27 03:29:41 +08:00
return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
LD->getMemOperand());
}
// Expand an unaligned 32 or 64-bit integer load node.
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
LoadSDNode *LD = cast<LoadSDNode>(Op);
EVT MemVT = LD->getMemoryVT();
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
if (Subtarget->systemSupportsUnalignedAccess())
return Op;
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
// Return if load is aligned or if MemVT is neither i32 nor i64.
if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
((MemVT != MVT::i32) && (MemVT != MVT::i64)))
return SDValue();
bool IsLittle = Subtarget->isLittle();
EVT VT = Op.getValueType();
ISD::LoadExtType ExtType = LD->getExtensionType();
SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
assert((VT == MVT::i32) || (VT == MVT::i64));
// Expand
// (set dst, (i64 (load baseptr)))
// to
// (set tmp, (ldl (add baseptr, 7), undef))
// (set dst, (ldr baseptr, tmp))
if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp. - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
2013-04-12 03:07:14 +08:00
SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
IsLittle ? 7 : 0);
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp. - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
2013-04-12 03:07:14 +08:00
return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
IsLittle ? 0 : 7);
}
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp. - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
2013-04-12 03:07:14 +08:00
SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
IsLittle ? 3 : 0);
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp. - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
2013-04-12 03:07:14 +08:00
SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
IsLittle ? 0 : 3);
// Expand
// (set dst, (i32 (load baseptr))) or
// (set dst, (i64 (sextload baseptr))) or
// (set dst, (i64 (extload baseptr)))
// to
// (set tmp, (lwl (add baseptr, 3), undef))
// (set dst, (lwr baseptr, tmp))
if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
(ExtType == ISD::EXTLOAD))
return LWR;
assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
// Expand
// (set dst, (i64 (zextload baseptr)))
// to
// (set tmp0, (lwl (add baseptr, 3), undef))
// (set tmp1, (lwr baseptr, tmp0))
// (set tmp2, (shl tmp1, 32))
// (set dst, (srl tmp2, 32))
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(LD);
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
SDValue Const32 = DAG.getConstant(32, MVT::i32);
SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is inserted after the shift-left-logical node. llvm-svn: 157937
2012-06-05 01:46:29 +08:00
SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
SDValue Ops[] = { SRL, LWR.getValue(1) };
Convert SelectionDAG::getMergeValues to use ArrayRef. llvm-svn: 207374
2014-04-28 03:20:57 +08:00
return DAG.getMergeValues(Ops, DL);
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
}
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp. - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
2013-04-12 03:07:14 +08:00
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
SDValue Chain, unsigned Offset) {
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp. llvm-svn: 158413
2012-06-14 03:06:08 +08:00
SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL(SD);
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
SDVTList VTList = DAG.getVTList(MVT::Other);
if (Offset)
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp. llvm-svn: 158413
2012-06-14 03:06:08 +08:00
Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
DAG.getConstant(Offset, BasePtrVT));
SDValue Ops[] = { Chain, Value, Ptr };
Convert getMemIntrinsicNode to take ArrayRef of SDValue instead of pointer and size. llvm-svn: 207329
2014-04-27 03:29:41 +08:00
return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
SD->getMemOperand());
}
// Expand an unaligned 32 or 64-bit integer store node.
[mips] Factor out unaligned store lowering code. llvm-svn: 182050
2013-05-17 04:45:17 +08:00
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
bool IsLittle) {
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
SDValue Value = SD->getValue(), Chain = SD->getChain();
EVT VT = Value.getValueType();
// Expand
// (store val, baseptr) or
// (truncstore val, baseptr)
// to
// (swl val, (add baseptr, 3))
// (swr val, baseptr)
if ((VT == MVT::i32) || SD->isTruncatingStore()) {
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp. - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
2013-04-12 03:07:14 +08:00
SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
IsLittle ? 3 : 0);
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp. - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
2013-04-12 03:07:14 +08:00
return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
}
assert(VT == MVT::i64);
// Expand
// (store val, baseptr)
// to
// (sdl val, (add baseptr, 7))
// (sdr val, baseptr)
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp. - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
2013-04-12 03:07:14 +08:00
SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which custom-lower unaligned load and store nodes. llvm-svn: 157864
2012-06-02 08:03:49 +08:00
}
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
2013-05-17 05:17:15 +08:00
// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
SDValue Val = SD->getValue();
if (Val.getOpcode() != ISD::FP_TO_SINT)
return SDValue();
EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
2013-05-17 05:17:15 +08:00
Val.getOperand(0));
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
2013-05-17 05:17:15 +08:00
SD->getPointerInfo(), SD->isVolatile(),
SD->isNonTemporal(), SD->getAlignment());
}
[mips] Factor out unaligned store lowering code. llvm-svn: 182050
2013-05-17 04:45:17 +08:00
SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
StoreSDNode *SD = cast<StoreSDNode>(Op);
EVT MemVT = SD->getMemoryVT();
// Lower unaligned integer stores.
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
if (!Subtarget->systemSupportsUnalignedAccess() &&
(SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
[mips] Factor out unaligned store lowering code. llvm-svn: 182050
2013-05-17 04:45:17 +08:00
((MemVT == MVT::i32) || (MemVT == MVT::i64)))
return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle());
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
2013-05-17 05:17:15 +08:00
return lowerFP_TO_SINT_STORE(SD, DAG);
[mips] Factor out unaligned store lowering code. llvm-svn: 182050
2013-05-17 04:45:17 +08:00
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
[mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node. Patch by Sasa Stankovic. llvm-svn: 167548
2012-11-08 03:10:58 +08:00
if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
|| cast<ConstantSDNode>
(Op->getOperand(0).getOperand(0))->getZExtValue() != 0
|| Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
return SDValue();
// The pattern
// (add (frameaddr 0), (frame_to_args_offset))
// results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
// (add FrameObject, 0)
// where FrameObject is a fixed StackObject with offset 0 which points to
// the old stack pointer.
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
EVT ValTy = Op->getValueType(0);
int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
[mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node. Patch by Sasa Stankovic. llvm-svn: 167548
2012-11-08 03:10:58 +08:00
DAG.getConstant(0, ValTy));
}
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
2013-05-17 05:17:15 +08:00
SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
SelectionDAG &DAG) const {
EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
2013-05-17 05:17:15 +08:00
Op.getOperand(0));
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) llvm-svn: 182053
2013-05-17 05:17:15 +08:00
}
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Calling Convention Implementation
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// TODO: Implement a generic logic using tblgen that can support this.
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
// Mips O32 ABI rules:
// ---
// i32 - Passed in A0, A1, A2, A3 and stack
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// f32 - Only passed in f32 registers if no int reg has been used yet to hold
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
// an argument. Otherwise, passed in A1, A2, A3 and stack.
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// f64 - Only passed in two aliased f32 registers if no int reg has been used
// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
// not used, it must be shadowed. If only A3 is avaiable, shadow it and
// go to stack.
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic. llvm-svn: 131657
2011-05-20 02:06:05 +08:00
//
// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
CCState &State, const MCPhysReg *F64Regs) {
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
static const unsigned IntRegsSize = 4, FloatRegsSize = 2;
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
// Do not process byval args here.
if (ArgFlags.isByVal())
return true;
Implement byval structure argument passing. The following limitations or deficiencies exist: - Works only if ABI is o32. - Zero-sized structures cannot be passed. - There is a lot of redundancy in generated code. llvm-svn: 131986
2011-05-25 03:18:33 +08:00
First step towards varargs support in Mips: - o32 cc must pass all arguments in A0...A3 and stack regardless if its type (but respect the alignment). - Store all variable arguments back to the caller stack. llvm-svn: 95500
2010-02-07 03:20:49 +08:00
// Promote i8 and i16
if (LocVT == MVT::i8 || LocVT == MVT::i16) {
LocVT = MVT::i32;
if (ArgFlags.isSExt())
LocInfo = CCValAssign::SExt;
else if (ArgFlags.isZExt())
LocInfo = CCValAssign::ZExt;
else
LocInfo = CCValAssign::AExt;
}
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic llvm-svn: 127029
2011-03-05 04:27:44 +08:00
unsigned Reg;
First step towards varargs support in Mips: - o32 cc must pass all arguments in A0...A3 and stack regardless if its type (but respect the alignment). - Store all variable arguments back to the caller stack. llvm-svn: 95500
2010-02-07 03:20:49 +08:00
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic. llvm-svn: 131657
2011-05-20 02:06:05 +08:00
// f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
// is true: function is vararg, argument is 3rd or higher, there is previous
// argument which is not f32 or f64.
bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
|| State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
Align i64 arguments to 64 bit boundaries. llvm-svn: 131668
2011-05-20 04:29:48 +08:00
unsigned OrigAlign = ArgFlags.getOrigAlign();
bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic. llvm-svn: 131657
2011-05-20 02:06:05 +08:00
if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic llvm-svn: 127029
2011-03-05 04:27:44 +08:00
Reg = State.AllocateReg(IntRegs, IntRegsSize);
Align i64 arguments to 64 bit boundaries. llvm-svn: 131668
2011-05-20 04:29:48 +08:00
// If this is the first part of an i64 arg,
// the allocated register must be either A0 or A2.
if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
Reg = State.AllocateReg(IntRegs, IntRegsSize);
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic llvm-svn: 127029
2011-03-05 04:27:44 +08:00
LocVT = MVT::i32;
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic. llvm-svn: 131657
2011-05-20 02:06:05 +08:00
} else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
// Allocate int register and shadow next int register. If first
// available register is Mips::A1 or Mips::A3, shadow it too.
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic llvm-svn: 127029
2011-03-05 04:27:44 +08:00
Reg = State.AllocateReg(IntRegs, IntRegsSize);
if (Reg == Mips::A1 || Reg == Mips::A3)
Reg = State.AllocateReg(IntRegs, IntRegsSize);
State.AllocateReg(IntRegs, IntRegsSize);
LocVT = MVT::i32;
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic. llvm-svn: 131657
2011-05-20 02:06:05 +08:00
} else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
// we are guaranteed to find an available float register
if (ValVT == MVT::f32) {
Reg = State.AllocateReg(F32Regs, FloatRegsSize);
// Shadow int register
State.AllocateReg(IntRegs, IntRegsSize);
} else {
Reg = State.AllocateReg(F64Regs, FloatRegsSize);
// Shadow int registers
unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
State.AllocateReg(IntRegs, IntRegsSize);
State.AllocateReg(IntRegs, IntRegsSize);
}
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic llvm-svn: 127029
2011-03-05 04:27:44 +08:00
} else
llvm_unreachable("Cannot handle this ValVT.");
First step towards varargs support in Mips: - o32 cc must pass all arguments in A0...A3 and stack regardless if its type (but respect the alignment). - Store all variable arguments back to the caller stack. llvm-svn: 95500
2010-02-07 03:20:49 +08:00
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
if (!Reg) {
unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
OrigAlign);
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic llvm-svn: 127029
2011-03-05 04:27:44 +08:00
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
} else
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic llvm-svn: 127029
2011-03-05 04:27:44 +08:00
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
First step towards varargs support in Mips: - o32 cc must pass all arguments in A0...A3 and stack regardless if its type (but respect the alignment). - Store all variable arguments back to the caller stack. llvm-svn: 95500
2010-02-07 03:20:49 +08:00
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
return false;
Function for handling byval arguments. llvm-svn: 144447
2011-11-12 10:20:46 +08:00
}
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. llvm-svn: 188847
2013-08-21 07:38:40 +08:00
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. llvm-svn: 188847
2013-08-21 07:38:40 +08:00
return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
}
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. llvm-svn: 188847
2013-08-21 07:38:40 +08:00
return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
}
Function for handling byval arguments. llvm-svn: 144447
2011-11-12 10:20:46 +08:00
#include "MipsGenCallingConv.inc"
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
// Call Calling Convention Implementation
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Do not rely on the enum values of argument registers A0-A3 being consecutive. Define function getNextIntArgReg, which takes a register as a parameter and returns the next O32 argument integer register. Use this function when double precision floating point arguments are passed in two integer registers. llvm-svn: 140363
2011-09-23 08:58:33 +08:00
// Return next O32 integer argument register.
static unsigned getNextIntArgReg(unsigned Reg) {
assert((Reg == Mips::A0) || (Reg == Mips::A2));
return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
}
Add definition of function MipsTargetLowering::passArgOnStack which emits nodes for passing a function call argument on a stack. llvm-svn: 167041
2012-10-31 03:23:25 +08:00
SDValue
MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDValue Chain, SDValue Arg, SDLoc DL,
Add definition of function MipsTargetLowering::passArgOnStack which emits nodes for passing a function call argument on a stack. llvm-svn: 167041
2012-10-31 03:23:25 +08:00
bool IsTailCall, SelectionDAG &DAG) const {
if (!IsTailCall) {
SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
DAG.getIntPtrConstant(Offset));
return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
false, 0);
}
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
/*isVolatile=*/ true, false, 0);
}
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
void MipsTargetLowering::
getOpndList(SmallVectorImpl<SDValue> &Ops,
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
// Insert node "GP copy globalreg" before call to function.
//
// R_MIPS_CALL* operators (emitted when non-internal functions are called
// in PIC mode) allow symbols to be resolved via lazy binding.
// The lazy binding stub requires GP to point to the GOT.
if (IsPICCall && !InternalLinkage) {
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
unsigned GPReg = Subtarget->isABI_N64() ? Mips::GP_64 : Mips::GP;
EVT Ty = Subtarget->isABI_N64() ? MVT::i64 : MVT::i32;
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
The next phase of Mips16 hard float implementation. Allow Mips16 routines to call Mips32 routines that have abi requirements that either arguments or return values are passed in floating point registers. This handles only the pic case. We have not done non pic for Mips16 yet in any form. The libm functions are Mips32, so with this addition we have a complete Mips16 hard float implementation. We still are not able to complete mix Mip16 and Mips32 with hard float. That will be the next phase which will have several steps. For Mips32 to freely call Mips16 some stub functions must be created. llvm-svn: 173320
2013-01-24 12:24:02 +08:00
}
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
// Build a sequence of copy-to-reg nodes chained together with token
// chain and flag operands which copy the outgoing args into registers.
// The InFlag in necessary since all emitted instructions must be
// stuck together.
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
The next phase of Mips16 hard float implementation. Allow Mips16 routines to call Mips32 routines that have abi requirements that either arguments or return values are passed in floating point registers. This handles only the pic case. We have not done non pic for Mips16 yet in any form. The libm functions are Mips32, so with this addition we have a complete Mips16 hard float implementation. We still are not able to complete mix Mip16 and Mips32 with hard float. That will be the next phase which will have several steps. For Mips32 to freely call Mips16 some stub functions must be created. llvm-svn: 173320
2013-01-24 12:24:02 +08:00
}
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
// Add argument registers to the end of the list so that they are
// known live into the call.
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
RegsToPass[i].second.getValueType()));
// Add a register mask operand representing the call-preserved registers.
const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
assert(Mask && "Missing call preserved mask for calling convention");
Checkin in of first of several patches to finish implementation of mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
2013-05-11 06:25:39 +08:00
if (Subtarget->inMips16HardFloat()) {
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
llvm::StringRef Sym = G->getGlobal()->getName();
Function *F = G->getGlobal()->getParent()->getFunction(Sym);
Check for null pointer before dereferencing. A careless typo on my part. I don't know why this did not show up earlier. This code has been around for ages. llvm-svn: 197119
2013-12-12 10:41:11 +08:00
if (F && F->hasFnAttribute("__Mips16RetHelper")) {
Checkin in of first of several patches to finish implementation of mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
2013-05-11 06:25:39 +08:00
Mask = MipsRegisterInfo::getMips16RetHelperMask();
}
}
}
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
Ops.push_back(CLI.DAG.getRegisterMask(Mask));
if (InFlag.getNode())
Ops.push_back(InFlag);
The next phase of Mips16 hard float implementation. Allow Mips16 routines to call Mips32 routines that have abi requirements that either arguments or return values are passed in floating point registers. This handles only the pic case. We have not done non pic for Mips16 yet in any form. The libm functions are Mips32, so with this addition we have a complete Mips16 hard float implementation. We still are not able to complete mix Mip16 and Mips32 with hard float. That will be the next phase which will have several steps. For Mips32 to freely call Mips16 some stub functions must be created. llvm-svn: 173320
2013-01-24 12:24:02 +08:00
}
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
/// LowerCall - functions arguments are copied from virtual regs to
Fix a typo llvm-svn: 62989
2009-01-26 11:15:54 +08:00
/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
SDValue
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
2012-05-26 00:35:28 +08:00
MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Use const qualifiers with TargetLowering. This eliminates several const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
2010-04-17 23:26:15 +08:00
SmallVectorImpl<SDValue> &InVals) const {
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
2012-05-26 00:35:28 +08:00
SelectionDAG &DAG = CLI.DAG;
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL = CLI.DL;
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. llvm-svn: 186274
2013-07-14 12:42:23 +08:00
SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
When store nodes or memcpy nodes are created to copy the function call arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and integer offset operands rather than frame object operands. llvm-svn: 161068
2012-08-01 02:46:41 +08:00
SDValue Chain = CLI.Chain;
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
2012-05-26 00:35:28 +08:00
SDValue Callee = CLI.Callee;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
bool &IsTailCall = CLI.IsTailCall;
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
2012-05-26 00:35:28 +08:00
CallingConv::ID CallConv = CLI.CallConv;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
bool IsVarArg = CLI.IsVarArg;
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
2012-05-26 00:35:28 +08:00
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
MachineFunction &MF = DAG.getMachineFunction();
Fixed AddLiveOut issues FI's created the write way to represent Mips stack llvm-svn: 39760
2007-07-12 07:16:16 +08:00
MachineFrameInfo *MFI = MF.getFrameInfo();
In CC_MipsO32, allocate a stack space regardless of whether the argument is passed in register or on the stack. llvm-svn: 131758
2011-05-21 05:39:54 +08:00
const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
2013-09-28 08:12:32 +08:00
MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
Reapply 80278 Add MO flags to simplify the printing of relocations. Remove the support for printing large code model relocs (which aren't supported anyway). llvm-svn: 80691
2009-09-02 01:27:58 +08:00
bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
Tidy up. Simplify logic. No functional change intended. llvm-svn: 146896
2011-12-20 03:52:25 +08:00
getTargetMachine(), ArgLocs, *DAG.getContext());
Checkin in of first of several patches to finish implementation of mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
2013-05-11 06:25:39 +08:00
MipsCC::SpecialCallingConvType SpecialCallingConv =
getSpecialCallingConv(Callee);
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(),
CCInfo, SpecialCallingConv);
Fixed AddLiveOut issues FI's created the write way to represent Mips stack llvm-svn: 39760
2007-07-12 07:16:16 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
Fix a problem with dual mips16/mips32 mode. When the underlying processor has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. llvm-svn: 189690
2013-08-31 03:40:56 +08:00
Subtarget->mipsSEUsesSoftFloat(),
Target: change member from reference to pointer This is a preliminary step to help ease the construction of CallLoweringInfo. Changing the construction to a chained function pattern requires that the parameter be nullable. However, rather than copying the vector, save a pointer rather than the reference to permit a late binding of the arguments. llvm-svn: 209080
2014-05-18 05:50:01 +08:00
Callee.getNode(), CLI.getArgs());
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Get a count of how many bytes are to be pushed on the stack.
Reorganize code in MipsTargetLowering::LowerCall to improve readability. llvm-svn: 132756
2011-06-09 01:39:33 +08:00
unsigned NextStackOffset = CCInfo.getNextStackOffset();
Pass the correct call frame size to callseq_start node. This is needed to replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with the one MachineFrameInfo has. llvm-svn: 160841
2012-07-27 07:27:01 +08:00
[mips] Add code to do tail call optimization. Currently, it is enabled only if option "enable-mips-tail-calls" is given and all of the callee's arguments are passed in registers. llvm-svn: 166342
2012-10-20 05:47:33 +08:00
// Check if it's really possible to do a tail call.
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
if (IsTailCall)
IsTailCall =
isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
[mips] Allow tail-call optimization for vararg functions and functions which use the caller's stack. llvm-svn: 167048
2012-10-31 04:16:31 +08:00
*MF.getInfo<MipsFunctionInfo>());
[mips] Add code to do tail call optimization. Currently, it is enabled only if option "enable-mips-tail-calls" is given and all of the callee's arguments are passed in registers. llvm-svn: 166342
2012-10-20 05:47:33 +08:00
Add 'musttail' marker to call instructions This is similar to the 'tail' marker, except that it guarantees that tail call optimization will occur. It also comes with convervative IR verification rules that ensure that tail call optimization is possible. Reviewers: nicholas Differential Revision: http://llvm-reviews.chandlerc.com/D3240 llvm-svn: 207143
2014-04-25 04:14:34 +08:00
if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
report_fatal_error("failed to perform tail call elimination on a call "
"site marked musttail");
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
if (IsTailCall)
[mips] Add code to do tail call optimization. Currently, it is enabled only if option "enable-mips-tail-calls" is given and all of the callee's arguments are passed in registers. llvm-svn: 166342
2012-10-20 05:47:33 +08:00
++NumTailCalls;
Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't yet legal according to comments in LegalizeDAG.cpp:227. Memcpy nodes created for copying byval arguments are inserted before CALLSEQ_START. The two failing tests reported in PR10876 pass after applying this patch. llvm-svn: 140046
2011-09-20 04:26:02 +08:00
// Chain is the output chain of the last Load/Store or CopyToReg node.
// ByValChain is the output chain of the last Memcpy node created for copying
// byval arguments to the stack.
[mips] Allow tail-call optimization for vararg functions and functions which use the caller's stack. llvm-svn: 167048
2012-10-31 04:16:31 +08:00
unsigned StackAlignment = TFL->getStackAlignment();
NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't yet legal according to comments in LegalizeDAG.cpp:227. Memcpy nodes created for copying byval arguments are inserted before CALLSEQ_START. The two failing tests reported in PR10876 pass after applying this patch. llvm-svn: 140046
2011-09-20 04:26:02 +08:00
SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
[mips] Add code to do tail call optimization. Currently, it is enabled only if option "enable-mips-tail-calls" is given and all of the callee's arguments are passed in registers. llvm-svn: 166342
2012-10-20 05:47:33 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
if (!IsTailCall)
Order CALLSEQ_START and CALLSEQ_END nodes. Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. llvm-svn: 182885
2013-05-30 06:03:55 +08:00
Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
When store nodes or memcpy nodes are created to copy the function call arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and integer offset operands rather than frame object operands. llvm-svn: 161068
2012-08-01 02:46:41 +08:00
[mips] Stop caching the result of hasMips64(), isABI_O32(), isABI_N32(), and isABI_N64() from MipsSubTarget in MipsTargetLowering Summary: The short name is quite convenient so provide an accessor for them instead. No functional change Depends on D3177 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3178 llvm-svn: 204911
2014-03-27 18:46:12 +08:00
SDValue StackPtr = DAG.getCopyFromReg(
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
Chain, DL, Subtarget->isABI_N64() ? Mips::SP_64 : Mips::SP,
getPointerTy());
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Reorganize code in MipsTargetLowering::LowerCall to improve readability. llvm-svn: 132756
2011-06-09 01:39:33 +08:00
// With EABI is it possible to have 16 args on registers.
[mips] Clean up code in MipsTargetLowering::LowerCall. No functional change intended llvm-svn: 173189
2013-01-23 04:05:56 +08:00
std::deque< std::pair<unsigned, SDValue> > RegsToPass;
Reorganize code in MipsTargetLowering::LowerCall to improve readability. llvm-svn: 132756
2011-06-09 01:39:33 +08:00
SmallVector<SDValue, 8> MemOpChains;
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
Reorganize code in MipsTargetLowering::LowerCall to improve readability. llvm-svn: 132756
2011-06-09 01:39:33 +08:00
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Walk the register/memloc assignments, inserting copies/loads.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Split the SDValue out of OutputArg so that SelectionDAG-independent code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
2010-07-07 23:54:55 +08:00
SDValue Arg = OutVals[i];
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
CCValAssign &VA = ArgLocs[i];
Make changes necessary in LowerCall to support Mips64. llvm-svn: 143217
2011-10-29 03:49:00 +08:00
MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
Implement Mips64's handling of byval arguments in LowerCall. llvm-svn: 144452
2011-11-12 10:34:50 +08:00
ISD::ArgFlagsTy Flags = Outs[i].Flags;
// ByVal Arg.
if (Flags.isByVal()) {
assert(Flags.getByValSize() &&
"ByVal args of size 0 should have been ignored by front-end.");
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
assert(ByValArg != MipsCCInfo.byval_end());
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
assert(!IsTailCall &&
[mips] Allow tail-call optimization for vararg functions and functions which use the caller's stack. llvm-svn: 167048
2012-10-31 04:16:31 +08:00
"Do not tail-call optimize if there is a byval argument.");
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
++ByValArg;
Implement Mips64's handling of byval arguments in LowerCall. llvm-svn: 144452
2011-11-12 10:34:50 +08:00
continue;
}
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Promote the value if needed.
switch (VA.getLocInfo()) {
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
2009-07-15 00:55:14 +08:00
default: llvm_unreachable("Unknown loc info!");
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
case CCValAssign::Full:
Make changes necessary in LowerCall to support Mips64. llvm-svn: 143217
2011-10-29 03:49:00 +08:00
if (VA.isRegLoc()) {
if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
[mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floating point registers. llvm-svn: 176521
2013-03-06 06:20:28 +08:00
(ValVT == MVT::f64 && LocVT == MVT::i64) ||
(ValVT == MVT::i64 && LocVT == MVT::f64))
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
Make changes necessary in LowerCall to support Mips64. llvm-svn: 143217
2011-10-29 03:49:00 +08:00
else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
Arg, DAG.getConstant(0, MVT::i32));
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. llvm-svn: 129606
2011-04-16 05:00:26 +08:00
Arg, DAG.getConstant(1, MVT::i32));
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. llvm-svn: 129594
2011-04-16 03:52:08 +08:00
if (!Subtarget->isLittle())
std::swap(Lo, Hi);
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
unsigned LocRegLo = VA.getLocReg();
Do not rely on the enum values of argument registers A0-A3 being consecutive. Define function getNextIntArgReg, which takes a register as a parameter and returns the next O32 argument integer register. Use this function when double precision floating point arguments are passed in two integer registers. llvm-svn: 140363
2011-09-23 08:58:33 +08:00
unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
continue;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
}
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
}
break;
minor cleanups llvm-svn: 48448
2008-03-17 14:57:02 +08:00
case CCValAssign::SExt:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
minor cleanups llvm-svn: 48448
2008-03-17 14:57:02 +08:00
break;
case CCValAssign::ZExt:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
minor cleanups llvm-svn: 48448
2008-03-17 14:57:02 +08:00
break;
case CCValAssign::AExt:
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
minor cleanups llvm-svn: 48448
2008-03-17 14:57:02 +08:00
break;
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// Arguments that can be passed on register must be kept at
Added support for PIC code with "explicit relocations" *only*. Removed all macro code for PIC (goodbye "la"). Support tested with shootout bench. llvm-svn: 43697
2007-11-05 11:02:32 +08:00
// RegsToPass vector
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
if (VA.isRegLoc()) {
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
minor cleanups llvm-svn: 48448
2008-03-17 14:57:02 +08:00
continue;
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
// Register can't get to this point...
minor cleanups llvm-svn: 48448
2008-03-17 14:57:02 +08:00
assert(VA.isMemLoc());
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// emit ISD::STORE whichs stores the
minor cleanups llvm-svn: 48448
2008-03-17 14:57:02 +08:00
// parameter value to a stack Location
[mips] Allow tail-call optimization for vararg functions and functions which use the caller's stack. llvm-svn: 167048
2012-10-31 04:16:31 +08:00
MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
Chain, Arg, DL, IsTailCall, DAG));
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
// Transform all store nodes into one single node because all store
// nodes are independent of each other.
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (!MemOpChains.empty())
Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>. llvm-svn: 207327
2014-04-27 02:35:24 +08:00
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Reverting r56249. On further investigation, this functionality isn't needed. Apologies for the thrashing. llvm-svn: 56251
2008-09-17 05:48:12 +08:00
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
// node so that legalize doesn't hack it.
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
bool IsPICCall =
(Subtarget->isABI_N64() || IsPIC); // true if calls are translated to
// jalr $25
[mips] Do not copy GOT address to register $gp if the function being called has internal linkage. llvm-svn: 170092
2012-12-13 11:17:29 +08:00
bool GlobalOrExternal = false, InternalLinkage = false;
Fix handling of functions with internal linkage. llvm-svn: 129099
2011-04-08 03:51:44 +08:00
SDValue CalleeLo;
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
EVT Ty = Callee.getValueType();
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase. llvm-svn: 128830
2011-04-05 01:11:07 +08:00
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. llvm-svn: 168458
2012-11-22 04:30:40 +08:00
if (IsPICCall) {
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
2013-09-28 08:12:32 +08:00
const GlobalValue *Val = G->getGlobal();
InternalLinkage = Val->hasInternalLinkage();
[mips] Do not copy GOT address to register $gp if the function being called has internal linkage. llvm-svn: 170092
2012-12-13 11:17:29 +08:00
if (InternalLinkage)
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
Callee = getAddrLocal(G, Ty, DAG,
Subtarget->isABI_N32() || Subtarget->isABI_N64());
[mips] Generate big GOT code. llvm-svn: 168460
2012-11-22 04:40:38 +08:00
else if (LargeGOT)
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16,
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
2013-09-28 08:12:32 +08:00
MipsII::MO_CALL_LO16, Chain,
FuncInfo->callPtrInfo(Val));
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. llvm-svn: 168458
2012-11-22 04:30:40 +08:00
else
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
2013-09-28 08:12:32 +08:00
Callee = getAddrGlobal(G, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
FuncInfo->callPtrInfo(Val));
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. llvm-svn: 168458
2012-11-22 04:30:40 +08:00
} else
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. llvm-svn: 168458
2012-11-22 04:30:40 +08:00
MipsII::MO_NO_FLAG);
jalr should use t9 ($25) for indirect calls regardless of the relocation model specified. llvm-svn: 146229
2011-12-09 09:45:12 +08:00
GlobalOrExternal = true;
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase. llvm-svn: 128830
2011-04-05 01:11:07 +08:00
}
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
2013-09-28 08:12:32 +08:00
const char *Sym = S->getSymbol();
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (!Subtarget->isABI_N64() && !IsPIC) // !N64 && static
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
2013-09-28 08:12:32 +08:00
Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(),
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. llvm-svn: 168458
2012-11-22 04:30:40 +08:00
MipsII::MO_NO_FLAG);
[mips] Generate big GOT code. llvm-svn: 168460
2012-11-22 04:40:38 +08:00
else if (LargeGOT)
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions. No intended functionality change. llvm-svn: 191546
2013-09-28 03:51:35 +08:00
Callee = getAddrGlobalLargeGOT(S, Ty, DAG, MipsII::MO_CALL_HI16,
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
2013-09-28 08:12:32 +08:00
MipsII::MO_CALL_LO16, Chain,
FuncInfo->callPtrInfo(Sym));
[mips] Emit call16 operator instead of got_disp. The former allows lazy binding. llvm-svn: 175920
2013-02-23 05:10:03 +08:00
else // N64 || PIC
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
2013-09-28 08:12:32 +08:00
Callee = getAddrGlobal(S, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
FuncInfo->callPtrInfo(Sym));
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. llvm-svn: 168458
2012-11-22 04:30:40 +08:00
jalr should use t9 ($25) for indirect calls regardless of the relocation model specified. llvm-svn: 146229
2011-12-09 09:45:12 +08:00
GlobalOrExternal = true;
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase. llvm-svn: 128830
2011-04-05 01:11:07 +08:00
}
[mips] Clean up code in MipsTargetLowering::LowerCall. No functional change intended llvm-svn: 173189
2013-01-23 04:05:56 +08:00
SmallVector<SDValue, 8> Ops(1, Chain);
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
[mips] Clean up code in MipsTargetLowering::LowerCall. No functional change intended llvm-svn: 173189
2013-01-23 04:05:56 +08:00
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
CLI, Callee, Chain);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
if (IsTailCall)
Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>. llvm-svn: 207327
2014-04-27 02:35:24 +08:00
return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
[mips] Add code to do tail call optimization. Currently, it is enabled only if option "enable-mips-tail-calls" is given and all of the callee's arguments are passed in registers. llvm-svn: 166342
2012-10-20 05:47:33 +08:00
Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>. llvm-svn: 207327
2014-04-27 02:35:24 +08:00
Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
SDValue InFlag = Chain.getValue(1);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Fix PR6144. Reload GP before the emission of CALLSEQ_END to guarantee the right reload order llvm-svn: 94915
2010-01-31 02:32:07 +08:00
// Create the CALLSEQ_END node.
Pass the correct call frame size to callseq_start node. This is needed to replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with the one MachineFrameInfo has. llvm-svn: 160841
2012-07-27 07:27:01 +08:00
Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
Order CALLSEQ_START and CALLSEQ_END nodes. Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. llvm-svn: 182885
2013-05-30 06:03:55 +08:00
DAG.getIntPtrConstant(0, true), InFlag, DL);
Fix PR6144. Reload GP before the emission of CALLSEQ_END to guarantee the right reload order llvm-svn: 94915
2010-01-31 02:32:07 +08:00
InFlag = Chain.getValue(1);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Handle result values, copying them out of physregs into vregs that we
// return.
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
return LowerCallResult(Chain, InFlag, CallConv, IsVarArg,
Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
/// LowerCallResult - Lower the result values of a call into the
/// appropriate copies out of appropriate physical registers.
SDValue
MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
CallingConv::ID CallConv, bool IsVarArg,
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
const SmallVectorImpl<ISD::InputArg> &Ins,
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL, SelectionDAG &DAG,
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
SmallVectorImpl<SDValue> &InVals,
const SDNode *CallNode,
const Type *RetTy) const {
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
Fix coding style violations. Remove white spaces and tabs. llvm-svn: 158471
2012-06-15 05:10:56 +08:00
getTargetMachine(), RVLocs, *DAG.getContext());
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(),
CCInfo);
Fixed AddLiveOut issues FI's created the write way to represent Mips stack llvm-svn: 39760
2007-07-12 07:16:16 +08:00
Fix a problem with dual mips16/mips32 mode. When the underlying processor has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. llvm-svn: 189690
2013-08-31 03:40:56 +08:00
MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(),
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
CallNode, RetTy);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
RVLocs[i].getLocVT(), InFlag);
Chain = Val.getValue(1);
InFlag = Val.getValue(2);
if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val);
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
InVals.push_back(Val);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
Added support for PIC code with "explicit relocations" *only*. Removed all macro code for PIC (goodbye "la"). Support tested with shootout bench. llvm-svn: 43697
2007-11-05 11:02:32 +08:00
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
return Chain;
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
// Formal Arguments Calling Convention Implementation
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
/// LowerFormalArguments - transform physical registers into virtual registers
First step towards varargs support in Mips: - o32 cc must pass all arguments in A0...A3 and stack regardless if its type (but respect the alignment). - Store all variable arguments back to the caller stack. llvm-svn: 95500
2010-02-07 03:20:49 +08:00
/// and generate load operations for arguments places on the stack.
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
SDValue
MipsTargetLowering::LowerFormalArguments(SDValue Chain,
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. llvm-svn: 129606
2011-04-16 05:00:26 +08:00
CallingConv::ID CallConv,
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
bool IsVarArg,
Tidy up. Simplify logic. No functional change intended. llvm-svn: 146896
2011-12-20 03:52:25 +08:00
const SmallVectorImpl<ISD::InputArg> &Ins,
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL, SelectionDAG &DAG,
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. llvm-svn: 129606
2011-04-16 05:00:26 +08:00
SmallVectorImpl<SDValue> &InVals)
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
const {
Mips ISelLowering cleanup : Removed old LowerCALL and FORMAL_ARGS helpers, they aren't used anyway, they also used to broke compiling when fastcc was specified for a function, but not anymore. llvm-svn: 54316
2008-08-04 15:12:52 +08:00
MachineFunction &MF = DAG.getMachineFunction();
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
MachineFrameInfo *MFI = MF.getFrameInfo();
Changed stack allocation On LowerFORMAL_ARGUMENTS. Added comments about new stack allocation. Expand SelectCC for i32 results llvm-svn: 41527
2007-08-28 13:08:16 +08:00
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Fixed AddLiveOut issues FI's created the write way to represent Mips stack llvm-svn: 39760
2007-07-12 07:16:16 +08:00
Move per-function state out of TargetLowering subclasses and into MachineFunctionInfo subclasses. llvm-svn: 101634
2010-04-17 22:41:14 +08:00
MipsFI->setVarArgsFrameIndex(0);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
First step towards varargs support in Mips: - o32 cc must pass all arguments in A0...A3 and stack regardless if its type (but respect the alignment). - Store all variable arguments back to the caller stack. llvm-svn: 95500
2010-02-07 03:20:49 +08:00
// Used with vargs to acumulate store chains.
std::vector<SDValue> OutChains;
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
Tidy up. Simplify logic. No functional change intended. llvm-svn: 146896
2011-12-20 03:52:25 +08:00
getTargetMachine(), ArgLocs, *DAG.getContext());
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(),
CCInfo);
[mips] Correct handling of fp128 (long double) formals and read long double parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
2013-03-06 06:13:04 +08:00
Function::const_arg_iterator FuncArg =
DAG.getMachineFunction().getFunction()->arg_begin();
Fix a problem with dual mips16/mips32 mode. When the underlying processor has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. llvm-svn: 189690
2013-08-31 03:40:56 +08:00
bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat();
Fixed AddLiveOut issues FI's created the write way to represent Mips stack llvm-svn: 39760
2007-07-12 07:16:16 +08:00
[mips] Correct handling of fp128 (long double) formals and read long double parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
2013-03-06 06:13:04 +08:00
MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
Add code for saving formal argument information to MipsFunctionInfo. This information will be used by IsEligibleForTailCallOptimization to determine whether a call can be tail-call optimized. llvm-svn: 167043
2012-10-31 03:37:25 +08:00
MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
MipsCCInfo.hasByValArg());
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
[mips] Make sure FuncArg doesn't advance when OrigArgIndex is the same as in the previous iteration. llvm-svn: 166850
2012-10-27 08:44:39 +08:00
unsigned CurArgIdx = 0;
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
[mips] Make sure FuncArg doesn't advance when OrigArgIndex is the same as in the previous iteration. llvm-svn: 166850
2012-10-27 08:44:39 +08:00
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
CCValAssign &VA = ArgLocs[i];
[mips] Make sure FuncArg doesn't advance when OrigArgIndex is the same as in the previous iteration. llvm-svn: 166850
2012-10-27 08:44:39 +08:00
std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
CurArgIdx = Ins[i].OrigArgIndex;
Make changes necessary in LowerFormalArguments to support Mips64. llvm-svn: 143218
2011-10-29 03:55:48 +08:00
EVT ValVT = VA.getValVT();
Implement Mips64's handling of byval arguments in LowerFormalArguments. llvm-svn: 144449
2011-11-12 10:29:58 +08:00
ISD::ArgFlagsTy Flags = Ins[i].Flags;
bool IsRegLoc = VA.isRegLoc();
if (Flags.isByVal()) {
assert(Flags.getByValSize() &&
"ByVal args of size 0 should have been ignored by front-end.");
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
assert(ByValArg != MipsCCInfo.byval_end());
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
MipsCCInfo, *ByValArg);
++ByValArg;
Implement Mips64's handling of byval arguments in LowerFormalArguments. llvm-svn: 144449
2011-11-12 10:29:58 +08:00
continue;
}
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Arguments stored on registers
Implement Mips64's handling of byval arguments in LowerFormalArguments. llvm-svn: 144449
2011-11-12 10:29:58 +08:00
if (IsRegLoc) {
[mips] Simplify LowerFormalArguments using getRegClassFor. No functionality change. llvm-svn: 193540
2013-10-29 05:21:36 +08:00
MVT RegVT = VA.getLocVT();
Simplify offset calculation of stack frame objects for $gp restore location and variable arguments in LowerCall and LowerFormalArguments. This should also fix the bug in which handling of variable arguments is incorrect when the front-end optimizes away unused fixed arguments. llvm-svn: 131942
2011-05-24 08:23:52 +08:00
unsigned ArgReg = VA.getLocReg();
[mips] Simplify LowerFormalArguments using getRegClassFor. No functionality change. llvm-svn: 193540
2013-10-29 05:21:36 +08:00
const TargetRegisterClass *RC = getRegClassFor(RegVT);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// Transform the arguments stored on
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// physical registers into virtual ones
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// If this is an 8 or 16-bit value, it has been passed promoted
// to 32 bits. Insert an assert[sz]ext to capture this, then
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// truncate to the right size.
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
if (VA.getLocInfo() != CCValAssign::Full) {
fix an apparently real bug exposed by a warning in -asserts mode. llvm-svn: 67737
2009-03-26 13:28:14 +08:00
unsigned Opcode = 0;
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
if (VA.getLocInfo() == CCValAssign::SExt)
Opcode = ISD::AssertSext;
else if (VA.getLocInfo() == CCValAssign::ZExt)
Opcode = ISD::AssertZext;
fix an apparently real bug exposed by a warning in -asserts mode. llvm-svn: 67737
2009-03-26 13:28:14 +08:00
if (Opcode)
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
Make changes necessary in LowerFormalArguments to support Mips64. llvm-svn: 143218
2011-10-29 03:55:48 +08:00
DAG.getValueType(ValVT));
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
}
[mips] Correct handling of fp128 (long double) formals and read long double parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
2013-03-06 06:13:04 +08:00
// Handle floating point arguments passed in integer registers and
// long double arguments passed in floating point registers.
Make changes necessary in LowerFormalArguments to support Mips64. llvm-svn: 143218
2011-10-29 03:55:48 +08:00
if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
[mips] Correct handling of fp128 (long double) formals and read long double parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
2013-03-06 06:13:04 +08:00
(RegVT == MVT::i64 && ValVT == MVT::f64) ||
(RegVT == MVT::f64 && ValVT == MVT::i64))
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
else if (Subtarget->isABI_O32() && RegVT == MVT::i32 &&
ValVT == MVT::f64) {
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
Make changes necessary in LowerFormalArguments to support Mips64. llvm-svn: 143218
2011-10-29 03:55:48 +08:00
getNextIntArgReg(ArgReg), RC);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
Make changes necessary in LowerFormalArguments to support Mips64. llvm-svn: 143218
2011-10-29 03:55:48 +08:00
if (!Subtarget->isLittle())
std::swap(ArgValue, ArgValue2);
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
Make changes necessary in LowerFormalArguments to support Mips64. llvm-svn: 143218
2011-10-29 03:55:48 +08:00
ArgValue, ArgValue2);
Added support for Mips O32 Calling Convention llvm-svn: 67280
2009-03-19 10:12:28 +08:00
}
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
InVals.push_back(ArgValue);
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
} else { // VA.isRegLoc()
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// sanity check
assert(VA.isMemLoc());
First step towards varargs support in Mips: - o32 cc must pass all arguments in A0...A3 and stack regardless if its type (but respect the alignment). - Store all variable arguments back to the caller stack. llvm-svn: 95500
2010-02-07 03:20:49 +08:00
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// The stack pointer offset is relative to the caller stack frame.
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
Simplify offset calculation of stack frame objects for $gp restore location and variable arguments in LowerCall and LowerFormalArguments. This should also fix the bug in which handling of variable arguments is incorrect when the front-end optimizes away unused fixed arguments. llvm-svn: 131942
2011-05-24 08:23:52 +08:00
VA.getLocMemOffset(), true);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Create load nodes to retrieve arguments from the stack
Use the methods and classes that were added to simplify LowerCall and LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
2012-10-27 08:29:43 +08:00
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
[mips] Make sure there is a chain edge dependency between loads that read formal arguments on the stack and stores created afterwards. We need this to ensure tail call optimized function calls do not write over the argument area of the stack before it is read out. llvm-svn: 194309
2013-11-09 10:38:51 +08:00
SDValue Load = DAG.getLoad(ValVT, DL, Chain, FIN,
MachinePointerInfo::getFixedStack(FI),
false, false, false, 0);
InVals.push_back(Load);
OutChains.push_back(Load.getValue(1));
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
Try to fix an SDAG dependence issue with sret r208453 added support for having sret on the second parameter. In that change, the code for copying sret into a virtual register was hoisted into the loop that lowers formal parameters. This caused a "Wrong topological sorting" assertion failure during scheduling when a parameter is passed in memory. This change undoes that by creating a second loop that deals with sret. I'm worried that this fix is incomplete. I don't fully understand the dependence issues. However, with this change we produce the same DAGs we used to produce, so if they are broken, they are just as broken as they have always been. llvm-svn: 208637
2014-05-13 06:01:27 +08:00
}
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
Try to fix an SDAG dependence issue with sret r208453 added support for having sret on the second parameter. In that change, the code for copying sret into a virtual register was hoisted into the loop that lowers formal parameters. This caused a "Wrong topological sorting" assertion failure during scheduling when a parameter is passed in memory. This change undoes that by creating a second loop that deals with sret. I'm worried that this fix is incomplete. I don't fully understand the dependence issues. However, with this change we produce the same DAGs we used to produce, so if they are broken, they are just as broken as they have always been. llvm-svn: 208637
2014-05-13 06:01:27 +08:00
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Allow sret on the second parameter as well as the first MSVC always places the implicit sret parameter after the implicit this parameter of instance methods. We used to handle this for x86_thiscallcc by allocating the sret parameter on the stack and leaving the this pointer in ecx, but that doesn't handle alternative calling conventions like cdecl, stdcall, fastcall, or the win64 convention. Instead, change the verifier to allow sret on the second parameter. This also requires changing the Mips and X86 backends to return the argument with the sret parameter, instead of assuming that the sret parameter comes first. The Sparc backend also returns sret parameters in a register, but I wasn't able to update it to handle secondary sret parameters. It currently calls report_fatal_error if you feed it an sret in the second parameter. Reviewers: rafael.espindola, majnemer Differential Revision: http://reviews.llvm.org/D3617 llvm-svn: 208453
2014-05-10 06:32:13 +08:00
// The mips ABIs for returning structs by value requires that we copy
// the sret argument into $v0 for the return. Save the argument into
// a virtual register so that we can access it from the return points.
Try to fix an SDAG dependence issue with sret r208453 added support for having sret on the second parameter. In that change, the code for copying sret into a virtual register was hoisted into the loop that lowers formal parameters. This caused a "Wrong topological sorting" assertion failure during scheduling when a parameter is passed in memory. This change undoes that by creating a second loop that deals with sret. I'm worried that this fix is incomplete. I don't fully understand the dependence issues. However, with this change we produce the same DAGs we used to produce, so if they are broken, they are just as broken as they have always been. llvm-svn: 208637
2014-05-13 06:01:27 +08:00
if (Ins[i].Flags.isSRet()) {
Allow sret on the second parameter as well as the first MSVC always places the implicit sret parameter after the implicit this parameter of instance methods. We used to handle this for x86_thiscallcc by allocating the sret parameter on the stack and leaving the this pointer in ecx, but that doesn't handle alternative calling conventions like cdecl, stdcall, fastcall, or the win64 convention. Instead, change the verifier to allow sret on the second parameter. This also requires changing the Mips and X86 backends to return the argument with the sret parameter, instead of assuming that the sret parameter comes first. The Sparc backend also returns sret parameters in a register, but I wasn't able to update it to handle secondary sret parameters. It currently calls report_fatal_error if you feed it an sret in the second parameter. Reviewers: rafael.espindola, majnemer Differential Revision: http://reviews.llvm.org/D3617 llvm-svn: 208453
2014-05-10 06:32:13 +08:00
unsigned Reg = MipsFI->getSRetReturnReg();
if (!Reg) {
Reg = MF.getRegInfo().createVirtualRegister(
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
getRegClassFor(Subtarget->isABI_N64() ? MVT::i64 : MVT::i32));
Allow sret on the second parameter as well as the first MSVC always places the implicit sret parameter after the implicit this parameter of instance methods. We used to handle this for x86_thiscallcc by allocating the sret parameter on the stack and leaving the this pointer in ecx, but that doesn't handle alternative calling conventions like cdecl, stdcall, fastcall, or the win64 convention. Instead, change the verifier to allow sret on the second parameter. This also requires changing the Mips and X86 backends to return the argument with the sret parameter, instead of assuming that the sret parameter comes first. The Sparc backend also returns sret parameters in a register, but I wasn't able to update it to handle secondary sret parameters. It currently calls report_fatal_error if you feed it an sret in the second parameter. Reviewers: rafael.espindola, majnemer Differential Revision: http://reviews.llvm.org/D3617 llvm-svn: 208453
2014-05-10 06:32:13 +08:00
MipsFI->setSRetReturnReg(Reg);
}
Try to fix an SDAG dependence issue with sret r208453 added support for having sret on the second parameter. In that change, the code for copying sret into a virtual register was hoisted into the loop that lowers formal parameters. This caused a "Wrong topological sorting" assertion failure during scheduling when a parameter is passed in memory. This change undoes that by creating a second loop that deals with sret. I'm worried that this fix is incomplete. I don't fully understand the dependence issues. However, with this change we produce the same DAGs we used to produce, so if they are broken, they are just as broken as they have always been. llvm-svn: 208637
2014-05-13 06:01:27 +08:00
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
Allow sret on the second parameter as well as the first MSVC always places the implicit sret parameter after the implicit this parameter of instance methods. We used to handle this for x86_thiscallcc by allocating the sret parameter on the stack and leaving the this pointer in ecx, but that doesn't handle alternative calling conventions like cdecl, stdcall, fastcall, or the win64 convention. Instead, change the verifier to allow sret on the second parameter. This also requires changing the Mips and X86 backends to return the argument with the sret parameter, instead of assuming that the sret parameter comes first. The Sparc backend also returns sret parameters in a register, but I wasn't able to update it to handle secondary sret parameters. It currently calls report_fatal_error if you feed it an sret in the second parameter. Reviewers: rafael.espindola, majnemer Differential Revision: http://reviews.llvm.org/D3617 llvm-svn: 208453
2014-05-10 06:32:13 +08:00
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
Try to fix an SDAG dependence issue with sret r208453 added support for having sret on the second parameter. In that change, the code for copying sret into a virtual register was hoisted into the loop that lowers formal parameters. This caused a "Wrong topological sorting" assertion failure during scheduling when a parameter is passed in memory. This change undoes that by creating a second loop that deals with sret. I'm worried that this fix is incomplete. I don't fully understand the dependence issues. However, with this change we produce the same DAGs we used to produce, so if they are broken, they are just as broken as they have always been. llvm-svn: 208637
2014-05-13 06:01:27 +08:00
break;
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
}
}
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
if (IsVarArg)
writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG);
First step towards varargs support in Mips: - o32 cc must pass all arguments in A0...A3 and stack regardless if its type (but respect the alignment). - Store all variable arguments back to the caller stack. llvm-svn: 95500
2010-02-07 03:20:49 +08:00
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// All stores are grouped in one node to allow the matching between
First step towards varargs support in Mips: - o32 cc must pass all arguments in A0...A3 and stack regardless if its type (but respect the alignment). - Store all variable arguments back to the caller stack. llvm-svn: 95500
2010-02-07 03:20:49 +08:00
// the size of Ins and InVals. This only happens when on varg functions
if (!OutChains.empty()) {
OutChains.push_back(Chain);
Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>. llvm-svn: 207327
2014-04-27 02:35:24 +08:00
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
First step towards varargs support in Mips: - o32 cc must pass all arguments in A0...A3 and stack regardless if its type (but respect the alignment). - Store all variable arguments back to the caller stack. llvm-svn: 95500
2010-02-07 03:20:49 +08:00
}
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
return Chain;
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Return Value Calling Convention Implementation
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Implement MipsTargetLowering::CanLowerReturn. Patch by Sasa Stankovic. llvm-svn: 165585
2012-10-10 09:27:09 +08:00
bool
MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
MachineFunction &MF, bool IsVarArg,
Implement MipsTargetLowering::CanLowerReturn. Patch by Sasa Stankovic. llvm-svn: 165585
2012-10-10 09:27:09 +08:00
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const {
SmallVector<CCValAssign, 16> RVLocs;
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(),
Implement MipsTargetLowering::CanLowerReturn. Patch by Sasa Stankovic. llvm-svn: 165585
2012-10-10 09:27:09 +08:00
RVLocs, Context);
return CCInfo.CheckReturn(Outs, RetCC_Mips);
}
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
SDValue
MipsTargetLowering::LowerReturn(SDValue Chain,
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
CallingConv::ID CallConv, bool IsVarArg,
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
const SmallVectorImpl<ISD::OutputArg> &Outs,
Split the SDValue out of OutputArg so that SelectionDAG-independent code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
2010-07-07 23:54:55 +08:00
const SmallVectorImpl<SDValue> &OutVals,
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL, SelectionDAG &DAG) const {
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// CCValAssign - represent the assignment of
// the return value to a location
SmallVector<CCValAssign, 16> RVLocs;
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
MachineFunction &MF = DAG.getMachineFunction();
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// CCState - Info about the registers and stack slot.
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
*DAG.getContext());
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(),
CCInfo);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
// Analyze return values.
Fix a problem with dual mips16/mips32 mode. When the underlying processor has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. llvm-svn: 189690
2013-08-31 03:40:56 +08:00
MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(),
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
MF.getFunction()->getReturnType());
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue Flag;
Move MRI liveouts to Mips return instructions. llvm-svn: 174410
2013-02-06 02:12:03 +08:00
SmallVector<SDValue, 4> RetOps(1, Chain);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
SDValue Val = OutVals[i];
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Move MRI liveouts to Mips return instructions. llvm-svn: 174410
2013-02-06 02:12:03 +08:00
// Guarantee that all emitted copies are stuck together with flags.
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Flag = Chain.getValue(1);
Move MRI liveouts to Mips return instructions. llvm-svn: 174410
2013-02-06 02:12:03 +08:00
RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
// The mips ABIs for returning structs by value requires that we copy
// the sret argument into $v0 for the return. We saved the argument into
// a virtual register in the entry block, so now we copy the value out
// and into $v0.
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
if (MF.getFunction()->hasStructRetAttr()) {
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
unsigned Reg = MipsFI->getSRetReturnReg();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (!Reg)
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
2009-07-15 00:55:14 +08:00
llvm_unreachable("sret virtual register not created in the entry block");
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
unsigned V0 = Subtarget->isABI_N64() ? Mips::V0_64 : Mips::V0;
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
Flag = Chain.getValue(1);
Move MRI liveouts to Mips return instructions. llvm-svn: 174410
2013-02-06 02:12:03 +08:00
RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
}
Move MRI liveouts to Mips return instructions. llvm-svn: 174410
2013-02-06 02:12:03 +08:00
RetOps[0] = Chain; // Update chain.
// Add the flag if we have it.
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
if (Flag.getNode())
Move MRI liveouts to Mips return instructions. llvm-svn: 174410
2013-02-06 02:12:03 +08:00
RetOps.push_back(Flag);
Make register Mips::RA allocatable if not in mips16 mode. llvm-svn: 159971
2012-07-10 08:19:06 +08:00
Move MRI liveouts to Mips return instructions. llvm-svn: 174410
2013-02-06 02:12:03 +08:00
// Return on Mips is always a "jr $ra"
Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>. llvm-svn: 207327
2014-04-27 02:35:24 +08:00
return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
// Mips Inline Assembly Support
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
MipsTargetLowering::ConstraintType MipsTargetLowering::
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
getConstraintType(const std::string &Constraint) const
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
{
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
// Mips specific constraints
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
// GCC config/mips/constraints.md
//
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// 'd' : An address register. Equivalent to r
// unless generating MIPS16 code.
// 'y' : Equivalent to r; retained for
// backwards compatibility.
Add support for the 'c' constraint. Patch by Jack Carter. llvm-svn: 156293
2012-05-07 14:25:10 +08:00
// 'c' : A register suitable for use in an indirect
// jump. This will always be $25 for -mabicalls.
Add support for the 'x' constraint. Patch by Jack Carter. llvm-svn: 156295
2012-05-07 14:25:19 +08:00
// 'l' : The lo register. 1 word storage.
// 'x' : The hilo register pair. Double word storage.
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default : break;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
case 'd':
case 'y':
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
case 'f':
Add support for the 'c' constraint. Patch by Jack Carter. llvm-svn: 156293
2012-05-07 14:25:10 +08:00
case 'c':
Add support for the 'l' constraint. Patch by Jack Carter. llvm-svn: 156294
2012-05-07 14:25:15 +08:00
case 'l':
Add support for the 'x' constraint. Patch by Jack Carter. llvm-svn: 156295
2012-05-07 14:25:19 +08:00
case 'x':
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
return C_RegisterClass;
Mips specific inline assembler constraint 'R' 'R' An address that can be sued in a non-macro load or store. This patch includes a positive test case. llvm-svn: 176452
2013-03-05 05:33:15 +08:00
case 'R':
return C_Memory;
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
}
}
return TargetLowering::getConstraintType(Constraint);
}
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
/// Examine constraint type and operand type and determine a weight value.
/// This object must already have been set up with the operand type
/// and the current alternative constraint selected.
TargetLowering::ConstraintWeight
MipsTargetLowering::getSingleConstraintMatchWeight(
AsmOperandInfo &info, const char *constraint) const {
ConstraintWeight weight = CW_Invalid;
Value *CallOperandVal = info.CallOperandVal;
// If we don't have a value, we can't do a match,
// but allow it at the lowest weight.
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
if (!CallOperandVal)
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
return CW_Default;
land David Blaikie's patch to de-constify Type, with a few tweaks. llvm-svn: 135375
2011-07-18 12:54:35 +08:00
Type *type = CallOperandVal->getType();
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
// Look at the constraint type.
switch (*constraint) {
default:
weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
break;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
case 'd':
case 'y':
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
if (type->isIntegerTy())
weight = CW_Register;
break;
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
case 'f': // FPU or MSA register
if (Subtarget->hasMSA() && type->isVectorTy() &&
cast<VectorType>(type)->getBitWidth() == 128)
weight = CW_Register;
else if (type->isFloatTy())
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
weight = CW_Register;
break;
Add support for the 'c' constraint. Patch by Jack Carter. llvm-svn: 156293
2012-05-07 14:25:10 +08:00
case 'c': // $25 for indirect jumps
Add support for the 'l' constraint. Patch by Jack Carter. llvm-svn: 156294
2012-05-07 14:25:15 +08:00
case 'l': // lo register
Add support for the 'x' constraint. Patch by Jack Carter. llvm-svn: 156295
2012-05-07 14:25:19 +08:00
case 'x': // hilo register pair
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
if (type->isIntegerTy())
Add support for the 'c' constraint. Patch by Jack Carter. llvm-svn: 156293
2012-05-07 14:25:10 +08:00
weight = CW_SpecificReg;
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
break;
Add support for the 'I' inline asm constraint. Also add tests from the previous 2 patches. Patch by Jack Carter. llvm-svn: 156279
2012-05-07 11:13:32 +08:00
case 'I': // signed 16 bit immediate
Support the 'J' constraint. Patch by Jack Carter. llvm-svn: 156280
2012-05-07 11:13:42 +08:00
case 'J': // integer zero
Add support for the inline asm constraint 'K'. llvm-svn: 156282
2012-05-07 13:46:29 +08:00
case 'K': // unsigned 16 bit immediate
Add support for the 'L' inline asm constraint. Patch by Jack Carter. llvm-svn: 156283
2012-05-07 13:46:37 +08:00
case 'L': // signed 32 bit immediate where lower 16 bits are 0
Add support for the 'N' inline asm constraint. Patch by Jack Carter. llvm-svn: 156284
2012-05-07 13:46:43 +08:00
case 'N': // immediate in the range of -65535 to -1 (inclusive)
Add support for the 'O' constraint. Patch by Jack Carter. llvm-svn: 156285
2012-05-07 13:46:48 +08:00
case 'O': // signed 15 bit immediate (+- 16383)
Add support for the 'P' constraint. Patch by Jack Carter. llvm-svn: 156292
2012-05-07 14:25:02 +08:00
case 'P': // immediate in the range of 65535 to 1 (inclusive)
Add support for the 'I' inline asm constraint. Also add tests from the previous 2 patches. Patch by Jack Carter. llvm-svn: 156279
2012-05-07 11:13:32 +08:00
if (isa<ConstantInt>(CallOperandVal))
weight = CW_Constant;
break;
Mips specific inline assembler constraint 'R' 'R' An address that can be sued in a non-macro load or store. This patch includes a positive test case. llvm-svn: 176452
2013-03-05 05:33:15 +08:00
case 'R':
weight = CW_Memory;
break;
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
}
return weight;
}
[mips] Properly parse registers that appear in inline-asm constraints. llvm-svn: 188336
2013-08-14 08:21:25 +08:00
/// This is a helper function to parse a physical register string and split it
/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
/// that is returned indicates whether parsing was successful. The second flag
/// is true if the numeric part exists.
static std::pair<bool, bool>
parsePhysicalReg(const StringRef &C, std::string &Prefix,
unsigned long long &Reg) {
if (C.front() != '{' || C.back() != '}')
return std::make_pair(false, false);
// Search for the first numeric character.
StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
I = std::find_if(B, E, std::ptr_fun(isdigit));
Prefix.assign(B, I - B);
// The second flag is set to false if no numeric characters were found.
if (I == E)
return std::make_pair(true, false);
// Parse the numeric characters.
return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
true);
}
std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
const TargetRegisterClass *RC;
std::string Prefix;
unsigned long long Reg;
std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
if (!R.first)
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
return std::make_pair(0U, nullptr);
[mips] Properly parse registers that appear in inline-asm constraints. llvm-svn: 188336
2013-08-14 08:21:25 +08:00
if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
// No numeric characters follow "hi" or "lo".
if (R.second)
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
return std::make_pair(0U, nullptr);
[mips] Properly parse registers that appear in inline-asm constraints. llvm-svn: 188336
2013-08-14 08:21:25 +08:00
RC = TRI->getRegClass(Prefix == "hi" ?
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
Mips::HI32RegClassID : Mips::LO32RegClassID);
[mips] Properly parse registers that appear in inline-asm constraints. llvm-svn: 188336
2013-08-14 08:21:25 +08:00
return std::make_pair(*(RC->begin()), RC);
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
} else if (Prefix.compare(0, 4, "$msa") == 0) {
// Parse $msa(ir|csr|access|save|modify|request|map|unmap)
// No numeric characters follow the name.
if (R.second)
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
return std::make_pair(0U, nullptr);
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
Reg = StringSwitch<unsigned long long>(Prefix)
.Case("$msair", Mips::MSAIR)
.Case("$msacsr", Mips::MSACSR)
.Case("$msaaccess", Mips::MSAAccess)
.Case("$msasave", Mips::MSASave)
.Case("$msamodify", Mips::MSAModify)
.Case("$msarequest", Mips::MSARequest)
.Case("$msamap", Mips::MSAMap)
.Case("$msaunmap", Mips::MSAUnmap)
.Default(0);
if (!Reg)
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
return std::make_pair(0U, nullptr);
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
return std::make_pair(Reg, RC);
[mips] Properly parse registers that appear in inline-asm constraints. llvm-svn: 188336
2013-08-14 08:21:25 +08:00
}
if (!R.second)
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
return std::make_pair(0U, nullptr);
[mips] Properly parse registers that appear in inline-asm constraints. llvm-svn: 188336
2013-08-14 08:21:25 +08:00
if (Prefix == "$f") { // Parse $f0-$f31.
// If the size of FP registers is 64-bit or Reg is an even number, select
// the 64-bit register class. Otherwise, select the 32-bit register class.
if (VT == MVT::Other)
VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
RC = getRegClassFor(VT);
[mips] Properly parse registers that appear in inline-asm constraints. llvm-svn: 188336
2013-08-14 08:21:25 +08:00
if (RC == &Mips::AFGR64RegClass) {
assert(Reg % 2 == 0);
Reg >>= 1;
}
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
} else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
[mips] Properly parse registers that appear in inline-asm constraints. llvm-svn: 188336
2013-08-14 08:21:25 +08:00
RC = TRI->getRegClass(Mips::FCCRegClassID);
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
else if (Prefix == "$w") { // Parse $w0-$w31.
RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
[mips] Properly parse registers that appear in inline-asm constraints. llvm-svn: 188336
2013-08-14 08:21:25 +08:00
} else { // Parse $0-$31.
assert(Prefix == "$");
RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
}
assert(Reg < RC->getNumRegs());
return std::make_pair(*(RC->begin() + Reg), RC);
}
Update comment for getRegForInlineAsmConstraint for Mips. llvm-svn: 134087
2011-06-30 03:33:04 +08:00
/// Given a register class constraint, like 'r', if this corresponds directly
/// to an LLVM register class, return a register of 0 and the register class
/// pointer.
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
The getRegForInlineAsmConstraint function should only accept MVT value types. llvm-svn: 184642
2013-06-23 02:37:38 +08:00
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
{
if (Constraint.size() == 1) {
switch (Constraint[0]) {
Remove getRegClassForInlineAsmConstraint for Mips. Part of rdar://9643582 llvm-svn: 134084
2011-06-30 03:04:31 +08:00
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
case 'r':
Misc. 1. Remove RA from list of allocatable registers 2. Enable d,y,r constraint inline assembly instructions Patch by Reed Kotler. llvm-svn: 163753
2012-09-13 07:27:55 +08:00
if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
if (Subtarget->inMips16Mode())
return std::make_pair(0U, &Mips::CPU16RegsRegClass);
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
return std::make_pair(0U, &Mips::GPR32RegClass);
Misc. 1. Remove RA from list of allocatable registers 2. Enable d,y,r constraint inline assembly instructions Patch by Reed Kotler. llvm-svn: 163753
2012-09-13 07:27:55 +08:00
}
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (VT == MVT::i64 && !Subtarget->isGP64bit())
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
return std::make_pair(0U, &Mips::GPR32RegClass);
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (VT == MVT::i64 && Subtarget->isGP64bit())
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
return std::make_pair(0U, &Mips::GPR64RegClass);
Allow 64 bit integer values in gpu registers if arch and abi are 64 bit. Patch by Jack Carter. llvm-svn: 156278
2012-05-07 11:13:22 +08:00
// This will generate an error message
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
return std::make_pair(0U, nullptr);
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
case 'f': // FPU or MSA register
if (VT == MVT::v16i8)
return std::make_pair(0U, &Mips::MSA128BRegClass);
else if (VT == MVT::v8i16 || VT == MVT::v8f16)
return std::make_pair(0U, &Mips::MSA128HRegClass);
else if (VT == MVT::v4i32 || VT == MVT::v4f32)
return std::make_pair(0U, &Mips::MSA128WRegClass);
else if (VT == MVT::v2i64 || VT == MVT::v2f64)
return std::make_pair(0U, &Mips::MSA128DRegClass);
else if (VT == MVT::f32)
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. llvm-svn: 155188
2012-04-20 15:30:17 +08:00
return std::make_pair(0U, &Mips::FGR32RegClass);
[mips][msa] Enable inlinse assembly for MSA. Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
2013-11-12 20:56:01 +08:00
else if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
Have getRegForInlineAsmConstraint return the correct register class when target is Mips64. llvm-svn: 147516
2012-01-04 10:45:01 +08:00
if (Subtarget->isFP64bit())
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. llvm-svn: 155188
2012-04-20 15:30:17 +08:00
return std::make_pair(0U, &Mips::FGR64RegClass);
return std::make_pair(0U, &Mips::AFGR64RegClass);
Have getRegForInlineAsmConstraint return the correct register class when target is Mips64. llvm-svn: 147516
2012-01-04 10:45:01 +08:00
}
Add support for the 'c' constraint. Patch by Jack Carter. llvm-svn: 156293
2012-05-07 14:25:10 +08:00
break;
case 'c': // register suitable for indirect jump
if (VT == MVT::i32)
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
Add support for the 'c' constraint. Patch by Jack Carter. llvm-svn: 156293
2012-05-07 14:25:10 +08:00
assert(VT == MVT::i64 && "Unexpected type.");
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
Add support for the 'l' constraint. Patch by Jack Carter. llvm-svn: 156294
2012-05-07 14:25:15 +08:00
case 'l': // register suitable for indirect jump
if (VT == MVT::i32)
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
Add support for the 'x' constraint. Patch by Jack Carter. llvm-svn: 156295
2012-05-07 14:25:19 +08:00
case 'x': // register suitable for indirect jump
// Fixme: Not triggering the use of both hi and low
// This will generate an error message
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
return std::make_pair(0U, nullptr);
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
}
}
[mips] Properly parse registers that appear in inline-asm constraints. llvm-svn: 188336
2013-08-14 08:21:25 +08:00
std::pair<unsigned, const TargetRegisterClass *> R;
R = parseRegForInlineAsmConstraint(Constraint, VT);
if (R.second)
return R;
InlineAsm asm support for integer registers added llvm-svn: 41225
2007-08-22 00:09:25 +08:00
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
}
Add support for the 'I' inline asm constraint. Also add tests from the previous 2 patches. Patch by Jack Carter. llvm-svn: 156279
2012-05-07 11:13:32 +08:00
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
std::string &Constraint,
std::vector<SDValue>&Ops,
SelectionDAG &DAG) const {
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
SDValue Result;
Add support for the 'I' inline asm constraint. Also add tests from the previous 2 patches. Patch by Jack Carter. llvm-svn: 156279
2012-05-07 11:13:32 +08:00
// Only support length 1 constraints for now.
if (Constraint.length() > 1) return;
char ConstraintLetter = Constraint[0];
switch (ConstraintLetter) {
default: break; // This will fall through to the generic implementation
case 'I': // Signed 16 bit constant
// If this fails, the parent routine will give an error
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue();
if (isInt<16>(Val)) {
Result = DAG.getTargetConstant(Val, Type);
break;
}
}
return;
Support the 'J' constraint. Patch by Jack Carter. llvm-svn: 156280
2012-05-07 11:13:42 +08:00
case 'J': // integer zero
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
EVT Type = Op.getValueType();
int64_t Val = C->getZExtValue();
if (Val == 0) {
Result = DAG.getTargetConstant(0, Type);
break;
}
}
return;
Add support for the inline asm constraint 'K'. llvm-svn: 156282
2012-05-07 13:46:29 +08:00
case 'K': // unsigned 16 bit immediate
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
EVT Type = Op.getValueType();
uint64_t Val = (uint64_t)C->getZExtValue();
if (isUInt<16>(Val)) {
Result = DAG.getTargetConstant(Val, Type);
break;
}
}
return;
Add support for the 'L' inline asm constraint. Patch by Jack Carter. llvm-svn: 156283
2012-05-07 13:46:37 +08:00
case 'L': // signed 32 bit immediate where lower 16 bits are 0
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue();
if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
Result = DAG.getTargetConstant(Val, Type);
break;
}
}
return;
Add support for the 'N' inline asm constraint. Patch by Jack Carter. llvm-svn: 156284
2012-05-07 13:46:43 +08:00
case 'N': // immediate in the range of -65535 to -1 (inclusive)
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue();
if ((Val >= -65535) && (Val <= -1)) {
Result = DAG.getTargetConstant(Val, Type);
break;
}
}
return;
Add support for the 'O' constraint. Patch by Jack Carter. llvm-svn: 156285
2012-05-07 13:46:48 +08:00
case 'O': // signed 15 bit immediate
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue();
if ((isInt<15>(Val))) {
Result = DAG.getTargetConstant(Val, Type);
break;
}
}
return;
Add support for the 'P' constraint. Patch by Jack Carter. llvm-svn: 156292
2012-05-07 14:25:02 +08:00
case 'P': // immediate in the range of 1 to 65535 (inclusive)
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue();
if ((Val <= 65535) && (Val >= 1)) {
Result = DAG.getTargetConstant(Val, Type);
break;
}
}
return;
Add support for the 'I' inline asm constraint. Also add tests from the previous 2 patches. Patch by Jack Carter. llvm-svn: 156279
2012-05-07 11:13:32 +08:00
}
if (Result.getNode()) {
Ops.push_back(Result);
return;
}
TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
}
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM,
Type *Ty) const {
Initial implementation of MipsTargetLowering::isLegalAddressingMode. llvm-svn: 168230
2012-11-17 08:25:41 +08:00
// No global is ever allowed as a base.
if (AM.BaseGV)
return false;
switch (AM.Scale) {
case 0: // "r+i" or just "i", depending on HasBaseReg.
break;
case 1:
if (!AM.HasBaseReg) // allow "r+i".
break;
return false; // disallow "r+r" or "r+r+i".
default:
return false;
}
return true;
}
Teach DAGCombine to fold constant offsets into GlobalAddress nodes, and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. llvm-svn: 57748
2008-10-18 10:06:02 +08:00
bool
MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
// The Mips target isn't yet aware of offsets.
return false;
}
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target. llvm-svn: 85281
2009-10-28 03:56:55 +08:00
Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp. llvm-svn: 158414
2012-06-14 03:33:32 +08:00
EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I mention the inline memcpy / memset expansion code is a mess? This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset. The first indicates whether it is expanding a memset or a memcpy / memmove. The later is whether the memset is a memset of zero. It's totally possible (likely even) that targets may want to do different things for memcpy and memset of zero. llvm-svn: 169959
2012-12-12 10:34:41 +08:00
unsigned SrcAlign,
bool IsMemset, bool ZeroMemset,
Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp. llvm-svn: 158414
2012-06-14 03:33:32 +08:00
bool MemcpyStrSrc,
MachineFunction &MF) const {
if (Subtarget->hasMips64())
return MVT::i64;
return MVT::i32;
}
Add a second ValueType argument to isFPImmLegal. llvm-svn: 85361
2009-10-28 09:43:28 +08:00
bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
if (VT != MVT::f32 && VT != MVT::f64)
return false;
Negative zero is not legal on mips. Patch by Sasa Stankovic llvm-svn: 123766
2011-01-19 03:41:41 +08:00
if (Imm.isNegZero())
return false;
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target. llvm-svn: 85281
2009-10-28 03:56:55 +08:00
return Imm.isZero();
}
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
2012-02-03 12:33:00 +08:00
unsigned MipsTargetLowering::getJumpTableEncoding() const {
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
if (Subtarget->isABI_N64())
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
2012-02-03 12:33:00 +08:00
return MachineJumpTableInfo::EK_GPRel64BlockAddress;
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
2012-02-03 12:33:00 +08:00
return TargetLowering::getJumpTableEncoding();
}
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets returned in registers $2 and $4. llvm-svn: 176527
2013-03-06 06:54:59 +08:00
/// This function returns true if CallSym is a long double emulation routine.
static bool isF128SoftLibCall(const char *CallSym) {
const char *const LibCalls[] =
{"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2",
"__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi",
"__fixunstfti", "__floatditf", "__floatsitf", "__floattitf",
"__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2",
"__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3",
"__trunctfdf2", "__trunctfsf2", "__unordtf2",
"ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl",
"log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
"truncl"};
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
const char *const *End = LibCalls + array_lengthof(LibCalls);
[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets returned in registers $2 and $4. llvm-svn: 176527
2013-03-06 06:54:59 +08:00
// Check that LibCalls is sorted alphabetically.
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
MipsTargetLowering::LTStr Comp;
[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets returned in registers $2 and $4. llvm-svn: 176527
2013-03-06 06:54:59 +08:00
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
#ifndef NDEBUG
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
for (const char *const *I = LibCalls; I < End - 1; ++I)
[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets returned in registers $2 and $4. llvm-svn: 176527
2013-03-06 06:54:59 +08:00
assert(Comp(*I, *(I + 1)));
#endif
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
return std::binary_search(LibCalls, End, CallSym, Comp);
[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets returned in registers $2 and $4. llvm-svn: 176527
2013-03-06 06:54:59 +08:00
}
/// This function returns true if Ty is fp128 or i128 which was originally a
/// fp128.
static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) {
if (Ty->isFP128Ty())
return true;
const ExternalSymbolSDNode *ES =
dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode);
// If the Ty is i128 and the function being called is a long double emulation
// routine, then the original type is f128.
return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol()));
}
Checkin in of first of several patches to finish implementation of mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
2013-05-11 06:25:39 +08:00
MipsTargetLowering::MipsCC::SpecialCallingConvType
MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const {
MipsCC::SpecialCallingConvType SpecialCallingConv =
Remove some empty statements Cleanup only. llvm-svn: 206710
2014-04-20 07:56:35 +08:00
MipsCC::NoSpecialCallingConv;
Checkin in of first of several patches to finish implementation of mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
2013-05-11 06:25:39 +08:00
if (Subtarget->inMips16HardFloat()) {
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
llvm::StringRef Sym = G->getGlobal()->getName();
Function *F = G->getGlobal()->getParent()->getFunction(Sym);
Check for null pointer before dereferencing. A careless typo on my part. I don't know why this did not show up earlier. This code has been around for ages. llvm-svn: 197119
2013-12-12 10:41:11 +08:00
if (F && F->hasFnAttribute("__Mips16RetHelper")) {
Checkin in of first of several patches to finish implementation of mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
2013-05-11 06:25:39 +08:00
SpecialCallingConv = MipsCC::Mips16RetHelperConv;
}
}
}
return SpecialCallingConv;
}
MipsTargetLowering::MipsCC::MipsCC(
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. llvm-svn: 188847
2013-08-21 07:38:40 +08:00
CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info,
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
MipsCC::SpecialCallingConvType SpecialCallingConv_)
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. llvm-svn: 188847
2013-08-21 07:38:40 +08:00
: CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_),
Checkin in of first of several patches to finish implementation of mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
2013-05-11 06:25:39 +08:00
SpecialCallingConv(SpecialCallingConv_){
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
// Pre-allocate reserved argument area.
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
CCInfo.AllocateStack(reservedArgArea(), 1);
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
}
Checkin in of first of several patches to finish implementation of mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
2013-05-11 06:25:39 +08:00
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
void MipsTargetLowering::MipsCC::
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
[mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floating point registers. llvm-svn: 176521
2013-03-06 06:20:28 +08:00
bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode,
std::vector<ArgListEntry> &FuncArgs) {
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
assert((CallConv != CallingConv::Fast || !IsVarArg) &&
"CallingConv::Fast shouldn't be used for vararg functions.");
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
unsigned NumOpnds = Args.size();
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
for (unsigned I = 0; I != NumOpnds; ++I) {
MVT ArgVT = Args[I].VT;
ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
bool R;
if (ArgFlags.isByVal()) {
handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
continue;
}
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
if (IsVarArg && !Args[I].IsFixed)
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
[mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floating point registers. llvm-svn: 176521
2013-03-06 06:20:28 +08:00
else {
MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
IsSoftFloat);
R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo);
}
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
if (R) {
#ifndef NDEBUG
dbgs() << "Call operand #" << I << " has unhandled type "
<< EVT(ArgVT).getEVTString();
#endif
[C++] Use 'nullptr'. llvm-svn: 207394
2014-04-28 12:05:08 +08:00
llvm_unreachable(nullptr);
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
}
}
}
void MipsTargetLowering::MipsCC::
[mips] Correct handling of fp128 (long double) formals and read long double parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
2013-03-06 06:13:04 +08:00
analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
unsigned NumArgs = Args.size();
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
llvm::CCAssignFn *FixedFn = fixedArgFn();
[mips] Correct handling of fp128 (long double) formals and read long double parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
2013-03-06 06:13:04 +08:00
unsigned CurArgIdx = 0;
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
for (unsigned I = 0; I != NumArgs; ++I) {
MVT ArgVT = Args[I].VT;
ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
[mips] Correct handling of fp128 (long double) formals and read long double parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
2013-03-06 06:13:04 +08:00
std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
CurArgIdx = Args[I].OrigArgIndex;
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
if (ArgFlags.isByVal()) {
handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
continue;
}
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), nullptr, IsSoftFloat);
[mips] Correct handling of fp128 (long double) formals and read long double parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
2013-03-06 06:13:04 +08:00
if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
continue;
#ifndef NDEBUG
dbgs() << "Formal Arg #" << I << " has unhandled type "
<< EVT(ArgVT).getEVTString();
#endif
[C++] Use 'nullptr'. llvm-svn: 207394
2014-04-28 12:05:08 +08:00
llvm_unreachable(nullptr);
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
}
}
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
template<typename Ty>
void MipsTargetLowering::MipsCC::
analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
const SDNode *CallNode, const Type *RetTy) const {
[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets returned in registers $2 and $4. llvm-svn: 176527
2013-03-06 06:54:59 +08:00
CCAssignFn *Fn;
if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode))
Fn = RetCC_F128Soft;
else
Fn = RetCC_Mips;
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
for (unsigned I = 0, E = RetVals.size(); I < E; ++I) {
MVT VT = RetVals[I].VT;
ISD::ArgFlagsTy Flags = RetVals[I].Flags;
MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat);
[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets returned in registers $2 and $4. llvm-svn: 176527
2013-03-06 06:54:59 +08:00
if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) {
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
#ifndef NDEBUG
dbgs() << "Call result #" << I << " has unhandled type "
<< EVT(VT).getEVTString() << '\n';
#endif
[C++] Use 'nullptr'. llvm-svn: 207394
2014-04-28 12:05:08 +08:00
llvm_unreachable(nullptr);
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
}
}
}
void MipsTargetLowering::MipsCC::
analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
const SDNode *CallNode, const Type *RetTy) const {
analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy);
}
void MipsTargetLowering::MipsCC::
analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
const Type *RetTy) const {
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
analyzeReturn(Outs, IsSoftFloat, nullptr, RetTy);
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. llvm-svn: 176523
2013-03-06 06:41:55 +08:00
}
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
MVT LocVT,
CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags) {
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
struct ByValArgInfo ByVal;
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
unsigned RegSize = regSize();
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
RegSize * 2);
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
if (useRegsForByval())
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
allocateRegs(ByVal, ByValSize, Align);
// Allocate space on caller's stack.
ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
Align);
CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
LocInfo));
ByValArgs.push_back(ByVal);
}
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
}
unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
}
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
const MCPhysReg *MipsTargetLowering::MipsCC::intArgRegs() const {
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
return IsO32 ? O32IntRegs : Mips64IntRegs;
}
llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
if (CallConv == CallingConv::Fast)
return CC_Mips_FastCC;
Checkin in of first of several patches to finish implementation of mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
2013-05-11 06:25:39 +08:00
if (SpecialCallingConv == Mips16RetHelperConv)
return CC_Mips16RetHelper;
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. llvm-svn: 188847
2013-08-21 07:38:40 +08:00
return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN;
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
}
llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. llvm-svn: 188847
2013-08-21 07:38:40 +08:00
return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg;
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
}
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
const MCPhysReg *MipsTargetLowering::MipsCC::shadowRegs() const {
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
return IsO32 ? O32IntRegs : Mips64DPRegs;
}
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
unsigned ByValSize,
unsigned Align) {
[mips] Clean up class MipsCCInfo. No functionality change intended. llvm-svn: 175310
2013-02-16 05:45:11 +08:00
unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
const MCPhysReg *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
Add class MipsCC which provides methods used to analyze formal and call arguments and inquire about calling convention information. llvm-svn: 166840
2012-10-27 07:56:38 +08:00
assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
"Byval argument's size and alignment should be a multiple of"
"RegSize.");
ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
// If Align > RegSize, the first arg register must be even.
if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
++ByVal.FirstIdx;
}
// Mark the registers allocated.
for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
}
Add method MipsTargetLowering::copyByValRegs. This method copies byval arguments passed in registers onto the stack and has the same functionality as existing functions CopyMips64ByValRegs and ReadByValArg which will be deleted later. llvm-svn: 166841
2012-10-27 08:10:18 +08:00
[mips] Correct handling of fp128 (long double) formals and read long double parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
2013-03-06 06:13:04 +08:00
MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
const SDNode *CallNode,
bool IsSoftFloat) const {
if (IsSoftFloat || IsO32)
return VT;
// Check if the original type was fp128.
[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets returned in registers $2 and $4. llvm-svn: 176527
2013-03-06 06:54:59 +08:00
if (originalTypeIsF128(OrigTy, CallNode)) {
[mips] Correct handling of fp128 (long double) formals and read long double parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
2013-03-06 06:13:04 +08:00
assert(VT == MVT::i64);
return MVT::f64;
}
return VT;
}
Add method MipsTargetLowering::copyByValRegs. This method copies byval arguments passed in registers onto the stack and has the same functionality as existing functions CopyMips64ByValRegs and ReadByValArg which will be deleted later. llvm-svn: 166841
2012-10-27 08:10:18 +08:00
void MipsTargetLowering::
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
Add method MipsTargetLowering::copyByValRegs. This method copies byval arguments passed in registers onto the stack and has the same functionality as existing functions CopyMips64ByValRegs and ReadByValArg which will be deleted later. llvm-svn: 166841
2012-10-27 08:10:18 +08:00
SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
const MipsCC &CC, const ByValArgInfo &ByVal) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
int FrameObjOffset;
if (RegAreaSize)
FrameObjOffset = (int)CC.reservedArgArea() -
(int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
else
FrameObjOffset = ByVal.Address;
// Create frame object.
EVT PtrTy = getPointerTy();
int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
InVals.push_back(FIN);
if (!ByVal.NumRegs)
return;
// Copy arg registers.
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT. Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. This is the second attempt. In the first attempt (r169837), a few getSimpleVT() were hoisted too far, detected by bootstrap failures. llvm-svn: 170104
2012-12-13 14:34:11 +08:00
MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
Add method MipsTargetLowering::copyByValRegs. This method copies byval arguments passed in registers onto the stack and has the same functionality as existing functions CopyMips64ByValRegs and ReadByValArg which will be deleted later. llvm-svn: 166841
2012-10-27 08:10:18 +08:00
const TargetRegisterClass *RC = getRegClassFor(RegTy);
for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
unsigned VReg = addLiveIn(MF, ArgReg, RC);
Add method MipsTargetLowering::copyByValRegs. This method copies byval arguments passed in registers onto the stack and has the same functionality as existing functions CopyMips64ByValRegs and ReadByValArg which will be deleted later. llvm-svn: 166841
2012-10-27 08:10:18 +08:00
unsigned Offset = I * CC.regSize();
SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
DAG.getConstant(Offset, PtrTy));
SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
StorePtr, MachinePointerInfo(FuncArg, Offset),
false, false, 0);
OutChains.push_back(Store);
}
}
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
// Copy byVal arg to registers and stack.
void MipsTargetLowering::
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
passByValArg(SDValue Chain, SDLoc DL,
[mips] Clean up code in MipsTargetLowering::LowerCall. No functional change intended llvm-svn: 173189
2013-01-23 04:05:56 +08:00
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. llvm-svn: 186274
2013-07-14 12:42:23 +08:00
SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
const MipsCC &CC, const ByValArgInfo &ByVal,
const ISD::ArgFlagsTy &Flags, bool isLittle) const {
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
unsigned ByValSizeInBytes = Flags.getByValSize();
unsigned OffsetInBytes = 0; // From beginning of struct
unsigned RegSizeInBytes = CC.regSize();
unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
if (ByVal.NumRegs) {
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
const MCPhysReg *ArgRegs = CC.intArgRegs();
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
bool LeftoverBytes = (ByVal.NumRegs * RegSizeInBytes > ByValSizeInBytes);
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
unsigned I = 0;
// Copy words to registers.
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
for (; I < ByVal.NumRegs - LeftoverBytes;
++I, OffsetInBytes += RegSizeInBytes) {
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
DAG.getConstant(OffsetInBytes, PtrTy));
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
MachinePointerInfo(), false, false, false,
Alignment);
MemOpChains.push_back(LoadVal.getValue(1));
unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
}
// Return if the struct has been fully copied.
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
if (ByValSizeInBytes == OffsetInBytes)
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
return;
// Copy the remainder of the byval argument with sub-word loads and shifts.
if (LeftoverBytes) {
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
assert((ByValSizeInBytes > OffsetInBytes) &&
(ByValSizeInBytes < OffsetInBytes + RegSizeInBytes) &&
"Size of the remainder should be smaller than RegSizeInBytes.");
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
SDValue Val;
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
if (RemainingSizeInBytes < LoadSizeInBytes)
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
continue;
// Load subword.
SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
DAG.getConstant(OffsetInBytes, PtrTy));
SDValue LoadVal = DAG.getExtLoad(
ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, Alignment);
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
MemOpChains.push_back(LoadVal.getValue(1));
// Shift the loaded value.
unsigned Shamt;
if (isLittle)
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
Shamt = TotalBytesLoaded * 8;
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
else
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
DAG.getConstant(Shamt, MVT::i32));
if (Val.getNode())
Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
else
Val = Shift;
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
OffsetInBytes += LoadSizeInBytes;
TotalBytesLoaded += LoadSizeInBytes;
Alignment = std::min(Alignment, LoadSizeInBytes);
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
}
unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
RegsToPass.push_back(std::make_pair(ArgReg, Val));
return;
}
}
// Copy remainder of byval arg to it with memcpy.
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
DAG.getConstant(OffsetInBytes, PtrTy));
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
DAG.getIntPtrConstant(ByVal.Address));
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
Break PseudoSourceValue out of the Value hierarchy. It is now the root of its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead. llvm-svn: 206255
2014-04-15 15:22:52 +08:00
MachinePointerInfo(), MachinePointerInfo());
Add method MipsTargetLowering::passByValArg. This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. llvm-svn: 166843
2012-10-27 08:16:36 +08:00
MemOpChains.push_back(Chain);
}
Add method MipsTargetLowering::writeVarArgRegs which copies argument registers of vararg functions back to the stack. llvm-svn: 166844
2012-10-27 08:21:13 +08:00
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
const MipsCC &CC, SDValue Chain,
SDLoc DL, SelectionDAG &DAG) const {
Add method MipsTargetLowering::writeVarArgRegs which copies argument registers of vararg functions back to the stack. llvm-svn: 166844
2012-10-27 08:21:13 +08:00
unsigned NumRegs = CC.numIntArgRegs();
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. llvm-svn: 205610
2014-04-04 13:16:06 +08:00
const MCPhysReg *ArgRegs = CC.intArgRegs();
Add method MipsTargetLowering::writeVarArgRegs which copies argument registers of vararg functions back to the stack. llvm-svn: 166844
2012-10-27 08:21:13 +08:00
const CCState &CCInfo = CC.getCCInfo();
unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
unsigned RegSize = CC.regSize();
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT. Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. This is the second attempt. In the first attempt (r169837), a few getSimpleVT() were hoisted too far, detected by bootstrap failures. llvm-svn: 170104
2012-12-13 14:34:11 +08:00
MVT RegTy = MVT::getIntegerVT(RegSize * 8);
Add method MipsTargetLowering::writeVarArgRegs which copies argument registers of vararg functions back to the stack. llvm-svn: 166844
2012-10-27 08:21:13 +08:00
const TargetRegisterClass *RC = getRegClassFor(RegTy);
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
// Offset of the first variable argument from stack pointer.
int VaArgOffset;
if (NumRegs == Idx)
VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
else
[mips] Coding style clean up. llvm-svn: 192125
2013-10-08 03:33:02 +08:00
VaArgOffset = (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
Add method MipsTargetLowering::writeVarArgRegs which copies argument registers of vararg functions back to the stack. llvm-svn: 166844
2012-10-27 08:21:13 +08:00
// Record the frame index of the first variable argument
// which is a value necessary to VASTART.
int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
MipsFI->setVarArgsFrameIndex(FI);
// Copy the integer registers that have not been used for argument passing
// to the argument register save area. For O32, the save area is allocated
// in the caller's stack frame, while for N32/64, it is allocated in the
// callee's stack frame.
for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
[mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. llvm-svn: 176844
2013-03-12 08:16:36 +08:00
unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
Add method MipsTargetLowering::writeVarArgRegs which copies argument registers of vararg functions back to the stack. llvm-svn: 166844
2012-10-27 08:21:13 +08:00
SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
MachinePointerInfo(), false, false, 0);
[C++] Use 'nullptr'. Target edition. llvm-svn: 207197
2014-04-25 13:30:21 +08:00
cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue((Value*)nullptr);
Add method MipsTargetLowering::writeVarArgRegs which copies argument registers of vararg functions back to the stack. llvm-svn: 166844
2012-10-27 08:21:13 +08:00
OutChains.push_back(Store);
}
}