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llvm-project/llvm/test/CodeGen/X86/div-rem-simplify.ll

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[x86] add tests to show missing div/rem simplifications; NFC These are not x86-specific, but the problem is not visible for all targets because it is masked by other transforms. These can lead to compiler crashes. llvm-svn: 297017
2017-03-06 23:50:07 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
[DAGCombiner] simplify div/rem-by-0 Refactoring of duplicated code and more fixes to follow. This is motivated by the post-commit comments for r296699: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170306/435182.html Ie, we can crash if we're missing obvious simplifications like this that exist in the IR simplifier or if these occur later than expected. The x86 change for non-splat division shows a potential opportunity to improve vector codegen: we assumed that since only one lane had meaningful results, we should do the math in scalar. But that means moving back and forth from vector registers. llvm-svn: 297026
2017-03-07 00:36:42 +08:00
; Div/rem by zero is undef.
[x86] add tests to show missing div/rem simplifications; NFC These are not x86-specific, but the problem is not visible for all targets because it is masked by other transforms. These can lead to compiler crashes. llvm-svn: 297017
2017-03-06 23:50:07 +08:00
define i32 @srem0(i32 %x) {
; CHECK-LABEL: srem0:
; CHECK: # BB#0:
; CHECK-NEXT: retq
%rem = srem i32 %x, 0
ret i32 %rem
}
define i32 @urem0(i32 %x) {
; CHECK-LABEL: urem0:
; CHECK: # BB#0:
; CHECK-NEXT: retq
%rem = urem i32 %x, 0
ret i32 %rem
}
define i32 @sdiv0(i32 %x) {
; CHECK-LABEL: sdiv0:
; CHECK: # BB#0:
; CHECK-NEXT: retq
%div = sdiv i32 %x, 0
ret i32 %div
}
define i32 @udiv0(i32 %x) {
; CHECK-LABEL: udiv0:
; CHECK: # BB#0:
; CHECK-NEXT: retq
%div = udiv i32 %x, 0
ret i32 %div
}
[DAGCombiner] simplify div/rem-by-0 Refactoring of duplicated code and more fixes to follow. This is motivated by the post-commit comments for r296699: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170306/435182.html Ie, we can crash if we're missing obvious simplifications like this that exist in the IR simplifier or if these occur later than expected. The x86 change for non-splat division shows a potential opportunity to improve vector codegen: we assumed that since only one lane had meaningful results, we should do the math in scalar. But that means moving back and forth from vector registers. llvm-svn: 297026
2017-03-07 00:36:42 +08:00
; Div/rem by zero vectors is undef.
[x86] add tests to show missing div/rem simplifications; NFC These are not x86-specific, but the problem is not visible for all targets because it is masked by other transforms. These can lead to compiler crashes. llvm-svn: 297017
2017-03-06 23:50:07 +08:00
define <4 x i32> @srem_vec0(<4 x i32> %x) {
; CHECK-LABEL: srem_vec0:
; CHECK: # BB#0:
; CHECK-NEXT: retq
%rem = srem <4 x i32> %x, zeroinitializer
ret <4 x i32> %rem
}
define <4 x i32> @urem_vec0(<4 x i32> %x) {
; CHECK-LABEL: urem_vec0:
; CHECK: # BB#0:
; CHECK-NEXT: retq
%rem = urem <4 x i32> %x, zeroinitializer
ret <4 x i32> %rem
}
define <4 x i32> @sdiv_vec0(<4 x i32> %x) {
; CHECK-LABEL: sdiv_vec0:
; CHECK: # BB#0:
; CHECK-NEXT: retq
%div = sdiv <4 x i32> %x, zeroinitializer
ret <4 x i32> %div
}
define <4 x i32> @udiv_vec0(<4 x i32> %x) {
; CHECK-LABEL: udiv_vec0:
; CHECK: # BB#0:
; CHECK-NEXT: retq
%div = udiv <4 x i32> %x, zeroinitializer
ret <4 x i32> %div
}