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llvm-project/llvm/test/CodeGen/ARM/smul.ll

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ARM: fixup more tests to specify the target more explicitly This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
2014-04-04 00:01:44 +08:00
; RUN: llc -mtriple=arm-eabi -mcpu=generic %s -o /dev/null
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
; RUN: llc -mtriple=thumb--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; RUN: llc -mtriple=thumbv6t2-none-eabi %s -o - | FileCheck %s
; RUN: llc -mtriple=thumbv6-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMBV6
ARM test cases contributed by Apple. llvm-svn: 33354
2007-01-19 17:20:23 +08:00
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
define i32 @f1(i16 %x, i32 %y) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f1:
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK-NOT: sxth
; CHECK: {{smulbt r0, r0, r1|smultb r0, r1, r0}}
; CHECK-THUMBV6-NOT: {{smulbt|smultb}}
%tmp1 = sext i16 %x to i32
%tmp2 = ashr i32 %y, 16
%tmp3 = mul i32 %tmp2, %tmp1
ret i32 %tmp3
ARM test cases contributed by Apple. llvm-svn: 33354
2007-01-19 17:20:23 +08:00
}
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
define i32 @f2(i32 %x, i32 %y) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f2:
FileCheck'ify test. llvm-svn: 128706
2011-04-01 11:36:33 +08:00
; CHECK: smultt
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK-THUMBV6-NOT: smultt
%tmp1 = ashr i32 %x, 16
%tmp3 = ashr i32 %y, 16
%tmp4 = mul i32 %tmp3, %tmp1
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
ret i32 %tmp4
ARM test cases contributed by Apple. llvm-svn: 33354
2007-01-19 17:20:23 +08:00
}
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
define i32 @f3(i32 %a, i16 %x, i32 %y) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f3:
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK-NOT: sxth
; CHECK: {{smlabt r0, r1, r2, r0|smlatb r0, r2, r1, r0}}
; CHECK-THUMBV6-NOT: {{smlabt|smlatb}}
%tmp = sext i16 %x to i32
%tmp2 = ashr i32 %y, 16
%tmp3 = mul i32 %tmp2, %tmp
%tmp5 = add i32 %tmp3, %a
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
ret i32 %tmp5
ARM test cases contributed by Apple. llvm-svn: 33354
2007-01-19 17:20:23 +08:00
}
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
define i32 @f4(i32 %a, i32 %x, i32 %y) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f4:
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
; CHECK: smlatt
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK-THUMBV6-NOT: smlatt
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
%tmp1 = ashr i32 %x, 16
%tmp3 = ashr i32 %y, 16
%tmp4 = mul i32 %tmp3, %tmp1
%tmp5 = add i32 %tmp4, %a
ret i32 %tmp5
}
define i32 @f5(i32 %a, i16 %x, i16 %y) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f5:
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK-NOT: sxth
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
; CHECK: smlabb
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK-THUMBV6-NOT: smlabb
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
%tmp1 = sext i16 %x to i32
%tmp3 = sext i16 %y to i32
%tmp4 = mul i32 %tmp3, %tmp1
%tmp5 = add i32 %tmp4, %a
ret i32 %tmp5
}
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
define i32 @f6(i32 %a, i32 %x, i16 %y) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f6:
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK-NOT: sxth
; CHECK: {{smlatb r0, r1, r2, r0|smlabt r0, r2, r1, r0}}
; CHECK-THUMBV6-NOT: {{smlatb|smlabt}}
%tmp1 = sext i16 %y to i32
%tmp2 = ashr i32 %x, 16
%tmp3 = mul i32 %tmp2, %tmp1
%tmp5 = add i32 %tmp3, %a
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
ret i32 %tmp5
}
define i32 @f7(i32 %a, i32 %b, i32 %c) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f7:
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK: smlawb r0, r0, r1, r2
; CHECK-THUMBV6-NOT: smlawb
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
%shl = shl i32 %b, 16
%shr = ashr exact i32 %shl, 16
%conv = sext i32 %a to i64
%conv2 = sext i32 %shr to i64
%mul = mul nsw i64 %conv2, %conv
%shr49 = lshr i64 %mul, 16
%conv5 = trunc i64 %shr49 to i32
%add = add nsw i32 %conv5, %c
ret i32 %add
}
define i32 @f8(i32 %a, i16 signext %b, i32 %c) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f8:
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK-NOT: sxth
; CHECK: smlawb r0, r0, r1, r2
; CHECK-THUMBV6-NOT: smlawb
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
%conv = sext i32 %a to i64
%conv1 = sext i16 %b to i64
%mul = mul nsw i64 %conv1, %conv
%shr5 = lshr i64 %mul, 16
%conv2 = trunc i64 %shr5 to i32
%add = add nsw i32 %conv2, %c
ret i32 %add
}
define i32 @f9(i32 %a, i32 %b, i32 %c) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f9:
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK: smlawt r0, r0, r1, r2
; CHECK-THUMBV6-NOT: smlawt
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
%conv = sext i32 %a to i64
%shr = ashr i32 %b, 16
%conv1 = sext i32 %shr to i64
%mul = mul nsw i64 %conv1, %conv
%shr26 = lshr i64 %mul, 16
%conv3 = trunc i64 %shr26 to i32
%add = add nsw i32 %conv3, %c
ret i32 %add
}
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
define i32 @f10(i32 %a, i32 %b) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f10:
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK: smulwb r0, r0, r1
; CHECK-THUMBV6-NOT: smulwb
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
%shl = shl i32 %b, 16
%shr = ashr exact i32 %shl, 16
%conv = sext i32 %a to i64
%conv2 = sext i32 %shr to i64
%mul = mul nsw i64 %conv2, %conv
%shr37 = lshr i64 %mul, 16
%conv4 = trunc i64 %shr37 to i32
ret i32 %conv4
}
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
define i32 @f11(i32 %a, i16 signext %b) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f11:
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK-NOT: sxth
; CHECK: smulwb r0, r0, r1
; CHECK-THUMBV6-NOT: smulwb
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
%conv = sext i32 %a to i64
%conv1 = sext i16 %b to i64
%mul = mul nsw i64 %conv1, %conv
%shr4 = lshr i64 %mul, 16
%conv2 = trunc i64 %shr4 to i32
ret i32 %conv2
}
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
define i32 @f12(i32 %a, i32 %b) {
Add trailing colons to labels in a test. This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
2016-04-09 03:49:03 +08:00
; CHECK-LABEL: f12:
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
; CHECK: smulwt r0, r0, r1
; CHECK-THUMBV6-NOT: smulwt
[ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selection Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
2016-04-09 00:02:53 +08:00
%conv = sext i32 %a to i64
%shr = ashr i32 %b, 16
%conv1 = sext i32 %shr to i64
%mul = mul nsw i64 %conv1, %conv
%shr25 = lshr i64 %mul, 16
%conv3 = trunc i64 %shr25 to i32
ret i32 %conv3
}
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 20:44:27 +08:00
define i32 @f13(i32 %x, i16 %y) {
; CHECK-LABEL: f13:
; CHECK-NOT: sxth
; CHECK: {{smultb r0, r0, r1|smulbt r0, r1, r0}}
; CHECK-THUMBV6-NOT: {{smultb|smulbt}}
%tmp1 = sext i16 %y to i32
%tmp2 = ashr i32 %x, 16
%tmp3 = mul i32 %tmp2, %tmp1
ret i32 %tmp3
}
define i32 @f14(i32 %x, i32 %y) {
; CHECK-LABEL: f14:
; CHECK-NOT: sxth
; CHECK: {{smultb r0, r0, r1|smulbt r0, r1, r0}}
; CHECK-THUMBV6-NOT: {{smultb|smulbt}}
%tmp1 = shl i32 %y, 16
%tmp2 = ashr i32 %tmp1, 16
%tmp3 = ashr i32 %x, 16
%tmp4 = mul i32 %tmp3, %tmp2
ret i32 %tmp4
}
define i32 @f15(i32 %x, i32 %y) {
; CHECK-LABEL: f15:
; CHECK-NOT: sxth
; CHECK: {{smulbt r0, r0, r1|smultb r0, r1, r0}}
; CHECK-THUMBV6-NOT: {{smulbt|smultb}}
%tmp1 = shl i32 %x, 16
%tmp2 = ashr i32 %tmp1, 16
%tmp3 = ashr i32 %y, 16
%tmp4 = mul i32 %tmp2, %tmp3
ret i32 %tmp4
}
define i32 @f16(i16 %x, i16 %y) {
; CHECK-LABEL: f16:
; CHECK-NOT: sxth
; CHECK: smulbb
; CHECK-THUMBV6-NOT: smulbb
%tmp1 = sext i16 %x to i32
%tmp2 = sext i16 %x to i32
%tmp3 = mul i32 %tmp1, %tmp2
ret i32 %tmp3
}
define i32 @f17(i32 %x, i32 %y) {
; CHECK-LABEL: f17:
; CHECK: smulbb
; CHECK-THUMBV6-NOT: smulbb
%tmp1 = shl i32 %x, 16
%tmp2 = shl i32 %y, 16
%tmp3 = ashr i32 %tmp1, 16
%tmp4 = ashr i32 %tmp2, 16
%tmp5 = mul i32 %tmp3, %tmp4
ret i32 %tmp5
}
define i32 @f18(i32 %a, i32 %x, i32 %y) {
; CHECK-LABEL: f18:
; CHECK: {{smlabt r0, r1, r2, r0|smlatb r0, r2, r1, r0}}
; CHECK-THUMBV6-NOT: {{smlabt|smlatb}}
%tmp0 = shl i32 %x, 16
%tmp1 = ashr i32 %tmp0, 16
%tmp2 = ashr i32 %y, 16
%tmp3 = mul i32 %tmp2, %tmp1
%tmp5 = add i32 %tmp3, %a
ret i32 %tmp5
}
define i32 @f19(i32 %a, i32 %x, i32 %y) {
; CHECK-LABEL: f19:
; CHECK: {{smlatb r0, r1, r2, r0|smlabt r0, r2, r1, r0}}
; CHECK-THUMBV6-NOT: {{smlatb|smlabt}}
%tmp0 = shl i32 %y, 16
%tmp1 = ashr i32 %tmp0, 16
%tmp2 = ashr i32 %x, 16
%tmp3 = mul i32 %tmp2, %tmp1
%tmp5 = add i32 %tmp3, %a
ret i32 %tmp5
}
define i32 @f20(i32 %a, i32 %x, i32 %y) {
; CHECK-LABEL: f20:
; CHECK: smlabb
; CHECK-THUMBV6-NOT: smlabb
%tmp1 = shl i32 %x, 16
%tmp2 = ashr i32 %tmp1, 16
%tmp3 = shl i32 %y, 16
%tmp4 = ashr i32 %tmp3, 16
%tmp5 = mul i32 %tmp2, %tmp4
%tmp6 = add i32 %tmp5, %a
ret i32 %tmp6
}
define i32 @f21(i32 %a, i32 %x, i16 %y) {
; CHECK-LABEL: f21
; CHECK-NOT: sxth
; CHECK: smlabb
; CHECK-THUMBV6-NOT: smlabb
%tmp1 = shl i32 %x, 16
%tmp2 = ashr i32 %tmp1, 16
%tmp3 = sext i16 %y to i32
%tmp4 = mul i32 %tmp2, %tmp3
%tmp5 = add i32 %a, %tmp4
ret i32 %tmp5
}