maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/testb-je-fusion.ll

28 lines
782 B
LLVM
Raw Normal View History

Regenerate test result for testb-je-fusion.ll. NFC. llvm-svn: 323595
2018-01-28 01:19:16 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
X86: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309774
2017-08-02 08:28:10 +08:00
; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7-avx | FileCheck %s
[X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0. Also, add a case clause in X86InstrInfo::shouldScheduleAdjacent to enable macro-fusion. <rdar://problem/15680770> llvm-svn: 212747
2014-07-11 02:00:53 +08:00
; testb should be scheduled right before je to enable macro-fusion.
define i32 @check_flag(i32 %flags, ...) nounwind {
Regenerate test result for testb-je-fusion.ll. NFC. llvm-svn: 323595
2018-01-28 01:19:16 +08:00
; CHECK-LABEL: check_flag:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
[X86] Avoid using high register trick for test instruction Summary: It seems it's main effect is to create addition copies when values are inr register that do not support this trick, which increase register pressure and makes the code bigger. Reviewers: craig.topper, niravd, spatel, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42646 llvm-svn: 323888
2018-02-01 00:48:54 +08:00
; CHECK-NEXT: testl $512, %edi # imm = 0x200
Regenerate test result for testb-je-fusion.ll. NFC. llvm-svn: 323595
2018-01-28 01:19:16 +08:00
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: retq
[X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0. Also, add a case clause in X86InstrInfo::shouldScheduleAdjacent to enable macro-fusion. <rdar://problem/15680770> llvm-svn: 212747
2014-07-11 02:00:53 +08:00
entry:
%and = and i32 %flags, 512
%tobool = icmp eq i32 %and, 0
Revert "CodeGen: Allow small copyable blocks to "break" the CFG." This reverts commit ada6595a526d71df04988eb0a4b4fe84df398ded. This needs a simple probability check because there are some cases where it is not profitable. llvm-svn: 291695
2017-01-12 03:55:19 +08:00
br i1 %tobool, label %if.end, label %if.then
[X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0. Also, add a case clause in X86InstrInfo::shouldScheduleAdjacent to enable macro-fusion. <rdar://problem/15680770> llvm-svn: 212747
2014-07-11 02:00:53 +08:00
if.then:
br label %if.end
if.end:
%hasflag = phi i32 [ 1, %if.then ], [ 0, %entry ]
ret i32 %hasflag
}