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llvm-project/llvm/test/CodeGen/AArch64/ldst-opt-aa.mir

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[AArch64] Use alias analysis in the load/store optimization pass. This allows the optimization to rearrange loads and stores more aggressively. Differential Revision: http://reviews.llvm.org/D30903 llvm-svn: 298092
2017-03-17 22:19:55 +08:00
# RUN: llc -mtriple=aarch64--linux-gnu -run-pass=aarch64-ldst-opt %s -verify-machineinstrs -o - | FileCheck %s
--- |
define void @ldr_str_aa(i32* noalias nocapture %x, i32* noalias nocapture readonly %y) {
entry:
%0 = load i32, i32* %y, align 4
store i32 %0, i32* %x, align 4
%arrayidx2 = getelementptr inbounds i32, i32* %y, i32 1
%1 = load i32, i32* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds i32, i32* %x, i32 1
store i32 %1, i32* %arrayidx3, align 4
ret void
}
...
---
# CHECK-LABEL: name: ldr_str_aa
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# CHECK: $w8, $w9 = LDPWi $x1, 0
# CHECK: STPWi $w8, $w9, $x0, 0
[AArch64] Use alias analysis in the load/store optimization pass. This allows the optimization to rearrange loads and stores more aggressively. Differential Revision: http://reviews.llvm.org/D30903 llvm-svn: 298092
2017-03-17 22:19:55 +08:00
name: ldr_str_aa
tracksRegLiveness: true
body: |
bb.0.entry:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $x0, $x1
[AArch64] Use alias analysis in the load/store optimization pass. This allows the optimization to rearrange loads and stores more aggressively. Differential Revision: http://reviews.llvm.org/D30903 llvm-svn: 298092
2017-03-17 22:19:55 +08:00
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$w8 = LDRWui $x1, 0 :: (load 4 from %ir.y)
STRWui killed $w8, $x0, 0 :: (store 4 into %ir.x)
$w9 = LDRWui killed $x1, 1 :: (load 4 from %ir.arrayidx2)
STRWui killed $w9, killed $x0, 1 :: (store 4 into %ir.arrayidx3)
RET undef $lr
[AArch64] Use alias analysis in the load/store optimization pass. This allows the optimization to rearrange loads and stores more aggressively. Differential Revision: http://reviews.llvm.org/D30903 llvm-svn: 298092
2017-03-17 22:19:55 +08:00