forked from OSchip/llvm-project
45 lines
1.9 KiB
Plaintext
45 lines
1.9 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s
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# The wrong form of scavengeRegister was used, so it wasn't accounting
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# for the iterator passed to eliminateFrameIndex. It was instead using
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# the current iterator in the scavenger, which was not yet set if the
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# spill was the first instruction in the block.
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---
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name: scavenge_register_position
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tracksRegLiveness: true
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# Force a frame larger than the immediate field with a large alignment.
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stack:
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- { id: 0, type: default, offset: 4096, size: 4, alignment: 8192 }
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr5
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frameOffsetReg: $sgpr5
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body: |
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; CHECK-LABEL: name: scavenge_register_position
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $sgpr4, $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: $sgpr5 = COPY $sgpr4
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; CHECK: $sgpr6 = S_ADD_U32 $sgpr5, 524288, implicit-def $scc
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; CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, align 8192, addrspace 5)
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; CHECK: S_BRANCH %bb.1
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; CHECK: bb.1:
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; CHECK: liveins: $sgpr5, $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: $sgpr4 = S_ADD_U32 $sgpr5, 524288, implicit-def $scc
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; CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, align 8192, addrspace 5)
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; CHECK: S_ENDPGM 0, implicit $vgpr0
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bb.0:
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$vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
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S_BRANCH %bb.1
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bb.1:
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$vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
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S_ENDPGM 0, implicit $vgpr0
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...
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