2018-08-31 13:49:54 +08:00
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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; RUN: llvm-as -data-layout=A5 < %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs | FileCheck --check-prefix=GCN %s
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2017-10-27 01:54:09 +08:00
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2018-02-14 02:00:25 +08:00
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declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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2017-10-27 01:54:09 +08:00
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare i32 @llvm.amdgcn.workgroup.id.x()
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declare void @llvm.amdgcn.s.barrier()
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@test_local.temp = internal addrspace(3) global [1 x i32] undef, align 4
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@test_global_local.temp = internal addrspace(3) global [1 x i32] undef, align 4
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; GCN-LABEL: {{^}}test_local
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; GCN: v_mov_b32_e32 v[[VAL:[0-9]+]], 0x777
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; GCN: ds_write_b32 v{{[0-9]+}}, v[[VAL]]
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; GCN: s_waitcnt lgkmcnt(0){{$}}
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; GCN-NEXT: s_barrier
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; GCN: flat_store_dword
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define amdgpu_kernel void @test_local(i32 addrspace(1)*) {
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2018-01-31 06:32:39 +08:00
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%2 = alloca i32 addrspace(1)*, align 4, addrspace(5)
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store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4
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2017-10-27 01:54:09 +08:00
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%3 = call i32 @llvm.amdgcn.workitem.id.x()
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%4 = zext i32 %3 to i64
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%5 = icmp eq i64 %4, 0
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br i1 %5, label %6, label %7
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; <label>:6: ; preds = %1
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store i32 1911, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_local.temp, i64 0, i64 0), align 4
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br label %7
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; <label>:7: ; preds = %6, %1
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fence syncscope("workgroup") release
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call void @llvm.amdgcn.s.barrier()
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fence syncscope("workgroup") acquire
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%8 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_local.temp, i64 0, i64 0), align 4
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2018-01-31 06:32:39 +08:00
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%9 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
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2018-02-14 02:00:25 +08:00
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%10 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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2017-10-27 01:54:09 +08:00
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%11 = call i32 @llvm.amdgcn.workitem.id.x()
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%12 = call i32 @llvm.amdgcn.workgroup.id.x()
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2018-02-14 02:00:25 +08:00
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%13 = getelementptr inbounds i8, i8 addrspace(4)* %10, i64 4
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%14 = bitcast i8 addrspace(4)* %13 to i16 addrspace(4)*
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%15 = load i16, i16 addrspace(4)* %14, align 4
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2017-10-27 01:54:09 +08:00
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%16 = zext i16 %15 to i32
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%17 = mul i32 %12, %16
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%18 = add i32 %17, %11
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2018-02-14 02:00:25 +08:00
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%19 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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2017-10-27 01:54:09 +08:00
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%20 = zext i32 %18 to i64
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2018-02-14 02:00:25 +08:00
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%21 = bitcast i8 addrspace(4)* %19 to i64 addrspace(4)*
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%22 = load i64, i64 addrspace(4)* %21, align 8
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2017-10-27 01:54:09 +08:00
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%23 = add i64 %22, %20
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%24 = getelementptr inbounds i32, i32 addrspace(1)* %9, i64 %23
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store i32 %8, i32 addrspace(1)* %24, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_global
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2017-11-21 02:24:21 +08:00
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; GCN: v_add_u32_e32 v{{[0-9]+}}, vcc, 0x888, v{{[0-9]+}}
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2017-10-27 01:54:09 +08:00
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; GCN: flat_store_dword
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; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
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; GCN-NEXT: s_barrier
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define amdgpu_kernel void @test_global(i32 addrspace(1)*) {
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2018-01-31 06:32:39 +08:00
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%2 = alloca i32 addrspace(1)*, align 4, addrspace(5)
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%3 = alloca i32, align 4, addrspace(5)
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store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4
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store i32 0, i32 addrspace(5)* %3, align 4
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2017-10-27 01:54:09 +08:00
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br label %4
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; <label>:4: ; preds = %58, %1
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2018-01-31 06:32:39 +08:00
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%5 = load i32, i32 addrspace(5)* %3, align 4
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2017-10-27 01:54:09 +08:00
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%6 = sext i32 %5 to i64
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2018-02-14 02:00:25 +08:00
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%7 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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2017-10-27 01:54:09 +08:00
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%8 = call i32 @llvm.amdgcn.workitem.id.x()
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%9 = call i32 @llvm.amdgcn.workgroup.id.x()
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2018-02-14 02:00:25 +08:00
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%10 = getelementptr inbounds i8, i8 addrspace(4)* %7, i64 4
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%11 = bitcast i8 addrspace(4)* %10 to i16 addrspace(4)*
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%12 = load i16, i16 addrspace(4)* %11, align 4
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2017-10-27 01:54:09 +08:00
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%13 = zext i16 %12 to i32
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%14 = mul i32 %9, %13
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%15 = add i32 %14, %8
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2018-02-14 02:00:25 +08:00
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%16 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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2017-10-27 01:54:09 +08:00
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%17 = zext i32 %15 to i64
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2018-02-14 02:00:25 +08:00
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%18 = bitcast i8 addrspace(4)* %16 to i64 addrspace(4)*
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%19 = load i64, i64 addrspace(4)* %18, align 8
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2017-10-27 01:54:09 +08:00
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%20 = add i64 %19, %17
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%21 = icmp ult i64 %6, %20
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br i1 %21, label %22, label %61
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; <label>:22: ; preds = %4
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2018-02-14 02:00:25 +08:00
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%23 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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2017-10-27 01:54:09 +08:00
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%24 = call i32 @llvm.amdgcn.workitem.id.x()
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%25 = call i32 @llvm.amdgcn.workgroup.id.x()
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2018-02-14 02:00:25 +08:00
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%26 = getelementptr inbounds i8, i8 addrspace(4)* %23, i64 4
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%27 = bitcast i8 addrspace(4)* %26 to i16 addrspace(4)*
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%28 = load i16, i16 addrspace(4)* %27, align 4
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2017-10-27 01:54:09 +08:00
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%29 = zext i16 %28 to i32
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%30 = mul i32 %25, %29
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%31 = add i32 %30, %24
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2018-02-14 02:00:25 +08:00
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%32 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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2017-10-27 01:54:09 +08:00
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%33 = zext i32 %31 to i64
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2018-02-14 02:00:25 +08:00
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%34 = bitcast i8 addrspace(4)* %32 to i64 addrspace(4)*
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%35 = load i64, i64 addrspace(4)* %34, align 8
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2017-10-27 01:54:09 +08:00
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%36 = add i64 %35, %33
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%37 = add i64 %36, 2184
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%38 = trunc i64 %37 to i32
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2018-01-31 06:32:39 +08:00
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%39 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
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%40 = load i32, i32 addrspace(5)* %3, align 4
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2017-10-27 01:54:09 +08:00
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%41 = sext i32 %40 to i64
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2018-02-14 02:00:25 +08:00
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%42 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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2017-10-27 01:54:09 +08:00
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%43 = call i32 @llvm.amdgcn.workitem.id.x()
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%44 = call i32 @llvm.amdgcn.workgroup.id.x()
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2018-02-14 02:00:25 +08:00
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%45 = getelementptr inbounds i8, i8 addrspace(4)* %42, i64 4
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%46 = bitcast i8 addrspace(4)* %45 to i16 addrspace(4)*
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%47 = load i16, i16 addrspace(4)* %46, align 4
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2017-10-27 01:54:09 +08:00
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%48 = zext i16 %47 to i32
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%49 = mul i32 %44, %48
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%50 = add i32 %49, %43
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2018-02-14 02:00:25 +08:00
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%51 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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2017-10-27 01:54:09 +08:00
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%52 = zext i32 %50 to i64
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2018-02-14 02:00:25 +08:00
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%53 = bitcast i8 addrspace(4)* %51 to i64 addrspace(4)*
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%54 = load i64, i64 addrspace(4)* %53, align 8
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2017-10-27 01:54:09 +08:00
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%55 = add i64 %54, %52
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%56 = add i64 %41, %55
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%57 = getelementptr inbounds i32, i32 addrspace(1)* %39, i64 %56
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store i32 %38, i32 addrspace(1)* %57, align 4
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fence syncscope("workgroup") release
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call void @llvm.amdgcn.s.barrier()
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fence syncscope("workgroup") acquire
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br label %58
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; <label>:58: ; preds = %22
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2018-01-31 06:32:39 +08:00
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%59 = load i32, i32 addrspace(5)* %3, align 4
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2017-10-27 01:54:09 +08:00
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%60 = add nsw i32 %59, 1
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2018-01-31 06:32:39 +08:00
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store i32 %60, i32 addrspace(5)* %3, align 4
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2017-10-27 01:54:09 +08:00
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br label %4
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; <label>:61: ; preds = %4
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ret void
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}
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; GCN-LABEL: {{^}}test_global_local
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; GCN: v_mov_b32_e32 v[[VAL:[0-9]+]], 0x999
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; GCN: ds_write_b32 v{{[0-9]+}}, v[[VAL]]
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; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
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; GCN-NEXT: s_barrier
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; GCN: flat_store_dword
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define amdgpu_kernel void @test_global_local(i32 addrspace(1)*) {
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2018-01-31 06:32:39 +08:00
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%2 = alloca i32 addrspace(1)*, align 4, addrspace(5)
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store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4
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%3 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
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2018-02-14 02:00:25 +08:00
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%4 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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2017-10-27 01:54:09 +08:00
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%5 = call i32 @llvm.amdgcn.workitem.id.x()
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%6 = call i32 @llvm.amdgcn.workgroup.id.x()
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2018-02-14 02:00:25 +08:00
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%7 = getelementptr inbounds i8, i8 addrspace(4)* %4, i64 4
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%8 = bitcast i8 addrspace(4)* %7 to i16 addrspace(4)*
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%9 = load i16, i16 addrspace(4)* %8, align 4
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2017-10-27 01:54:09 +08:00
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%10 = zext i16 %9 to i32
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%11 = mul i32 %6, %10
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%12 = add i32 %11, %5
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2018-02-14 02:00:25 +08:00
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%13 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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2017-10-27 01:54:09 +08:00
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%14 = zext i32 %12 to i64
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2018-02-14 02:00:25 +08:00
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%15 = bitcast i8 addrspace(4)* %13 to i64 addrspace(4)*
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%16 = load i64, i64 addrspace(4)* %15, align 8
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2017-10-27 01:54:09 +08:00
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%17 = add i64 %16, %14
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%18 = getelementptr inbounds i32, i32 addrspace(1)* %3, i64 %17
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store i32 1, i32 addrspace(1)* %18, align 4
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%19 = call i32 @llvm.amdgcn.workitem.id.x()
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%20 = zext i32 %19 to i64
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%21 = icmp eq i64 %20, 0
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br i1 %21, label %22, label %23
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; <label>:22: ; preds = %1
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store i32 2457, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_global_local.temp, i64 0, i64 0), align 4
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br label %23
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; <label>:23: ; preds = %22, %1
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fence syncscope("workgroup") release
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call void @llvm.amdgcn.s.barrier()
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fence syncscope("workgroup") acquire
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%24 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_global_local.temp, i64 0, i64 0), align 4
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2018-01-31 06:32:39 +08:00
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%25 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
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2018-02-14 02:00:25 +08:00
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%26 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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2017-10-27 01:54:09 +08:00
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%27 = call i32 @llvm.amdgcn.workitem.id.x()
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%28 = call i32 @llvm.amdgcn.workgroup.id.x()
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2018-02-14 02:00:25 +08:00
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%29 = getelementptr inbounds i8, i8 addrspace(4)* %26, i64 4
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%30 = bitcast i8 addrspace(4)* %29 to i16 addrspace(4)*
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%31 = load i16, i16 addrspace(4)* %30, align 4
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2017-10-27 01:54:09 +08:00
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%32 = zext i16 %31 to i32
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%33 = mul i32 %28, %32
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%34 = add i32 %33, %27
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2018-02-14 02:00:25 +08:00
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%35 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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2017-10-27 01:54:09 +08:00
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%36 = zext i32 %34 to i64
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2018-02-14 02:00:25 +08:00
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%37 = bitcast i8 addrspace(4)* %35 to i64 addrspace(4)*
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%38 = load i64, i64 addrspace(4)* %37, align 8
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2017-10-27 01:54:09 +08:00
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%39 = add i64 %38, %36
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%40 = getelementptr inbounds i32, i32 addrspace(1)* %25, i64 %39
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store i32 %24, i32 addrspace(1)* %40, align 4
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ret void
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}
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