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llvm-project/clang/test/CodeGen/target-data.c

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Convert test to FileCheck. llvm-svn: 197269
2013-12-14 04:11:02 +08:00
// RUN: %clang_cc1 -triple i686-unknown-unknown -emit-llvm -o - %s | \
// RUN: FileCheck --check-prefix=I686-UNKNOWN %s
Reland "Change the X86 datalayout to add three address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers." This reverts 57076d3199fc2b0af4a3736b7749dd5462cacda5. Original review at https://reviews.llvm.org/D64931. Review for added fix at https://reviews.llvm.org/D66843. llvm-svn: 371568
2019-09-11 07:15:38 +08:00
// I686-UNKNOWN: target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:32-n8:16:32-S128"
Convert test to FileCheck. llvm-svn: 197269
2013-12-14 04:11:02 +08:00
// RUN: %clang_cc1 -triple i686-apple-darwin9 -emit-llvm -o - %s | \
// RUN: FileCheck --check-prefix=I686-DARWIN %s
Reland "Change the X86 datalayout to add three address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers." This reverts 57076d3199fc2b0af4a3736b7749dd5462cacda5. Original review at https://reviews.llvm.org/D64931. Review for added fix at https://reviews.llvm.org/D66843. llvm-svn: 371568
2019-09-11 07:15:38 +08:00
// I686-DARWIN: target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:128-n8:16:32-S128"
Convert test to FileCheck. llvm-svn: 197269
2013-12-14 04:11:02 +08:00
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple i686-unknown-win32 -emit-llvm -o - %s | \
// RUN: FileCheck --check-prefix=I686-WIN32 %s
[X86][MS] Change the alignment of f80 to 16 bytes on Windows 32bits to match with ICC MSVC currently doesn't support 80 bits long double. ICC supports it when the option `/Qlong-double` is specified. Changing the alignment of f80 to 16 bytes so that we can be compatible with ICC's option. Reviewed By: rnk, craig.topper Differential Revision: https://reviews.llvm.org/D115942
2022-01-23 09:14:58 +08:00
// I686-WIN32: target datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32-a:0:32-S32"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple i686-unknown-cygwin -emit-llvm -o - %s | \
// RUN: FileCheck --check-prefix=I686-CYGWIN %s
Reland "Change the X86 datalayout to add three address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers." This reverts 57076d3199fc2b0af4a3736b7749dd5462cacda5. Original review at https://reviews.llvm.org/D64931. Review for added fix at https://reviews.llvm.org/D66843. llvm-svn: 371568
2019-09-11 07:15:38 +08:00
// I686-CYGWIN: target datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:32-n8:16:32-a:0:32-S32"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
Fix the data layout mangling specification for 'i686-pc-macho' Use 'o' for the mangling specification instead of 'e'. This fixes an error in the backend caused by a mismatch between the data layouts generated by the backend and the frontend. rdar://problem/64168540
2020-07-22 03:58:17 +08:00
// RUN: %clang_cc1 -triple i686-pc-macho -emit-llvm -o - %s | \
// RUN: FileCheck --check-prefix=I686-MACHO %s
// I686-MACHO: target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:32-n8:16:32-S128"
Convert test to FileCheck. llvm-svn: 197269
2013-12-14 04:11:02 +08:00
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | \
// RUN: FileCheck --check-prefix=X86_64 %s
Reland "Change the X86 datalayout to add three address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers." This reverts 57076d3199fc2b0af4a3736b7749dd5462cacda5. Original review at https://reviews.llvm.org/D64931. Review for added fix at https://reviews.llvm.org/D66843. llvm-svn: 371568
2019-09-11 07:15:38 +08:00
// X86_64: target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
Consolidate DataLayout string testing in one file. llvm-svn: 197276
2013-12-14 05:49:53 +08:00
// RUN: %clang_cc1 -triple xcore-unknown-unknown -emit-llvm -o - %s | \
// RUN: FileCheck --check-prefix=XCORE %s
Update for llvm's DataLayout including mangling information. llvm-svn: 198439
2014-01-04 03:22:05 +08:00
// XCORE: target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32"
Consolidate DataLayout string testing in one file. llvm-svn: 197276
2013-12-14 05:49:53 +08:00
// RUN: %clang_cc1 -triple sparc-sun-solaris -emit-llvm -o - %s | \
// RUN: FileCheck %s --check-prefix=SPARC-V8
Update for llvm's DataLayout including mangling information. llvm-svn: 198439
2014-01-04 03:22:05 +08:00
// SPARC-V8: target datalayout = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"
Consolidate DataLayout string testing in one file. llvm-svn: 197276
2013-12-14 05:49:53 +08:00
// RUN: %clang_cc1 -triple sparcv9-sun-solaris -emit-llvm -o - %s | \
// RUN: FileCheck %s --check-prefix=SPARC-V9
Update for llvm's DataLayout including mangling information. llvm-svn: 198439
2014-01-04 03:22:05 +08:00
// SPARC-V9: target datalayout = "E-m:e-i64:64-n32:64-S128"
Consolidate DataLayout string testing in one file. llvm-svn: 197276
2013-12-14 05:49:53 +08:00
// RUN: %clang_cc1 -triple mipsel-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-32EL
[driver][mips] Support MIPS R6 target triples This change adds support for the following MIPS target triples: mipsisa32r6-linux-gnu mipsisa32r6el-linux-gnu mipsisa64r6-linux-gnuabi64 mipsisa64r6el-linux-gnuabi64 mipsisa64r6-linux-gnuabin32 mipsisa64r6el-linux-gnuabin32 Patch by Yun Qiang Su. Differential revision: https://reviews.llvm.org/D50850 llvm-svn: 344608
2018-10-16 22:29:27 +08:00
// RUN: %clang_cc1 -triple mipsisa32r6el-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-32EL
Update for llvm's DataLayout including mangling information. llvm-svn: 198439
2014-01-04 03:22:05 +08:00
// MIPS-32EL: target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
Consolidate DataLayout string testing in one file. llvm-svn: 197276
2013-12-14 05:49:53 +08:00
// RUN: %clang_cc1 -triple mips-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-32EB
[driver][mips] Support MIPS R6 target triples This change adds support for the following MIPS target triples: mipsisa32r6-linux-gnu mipsisa32r6el-linux-gnu mipsisa64r6-linux-gnuabi64 mipsisa64r6el-linux-gnuabi64 mipsisa64r6-linux-gnuabin32 mipsisa64r6el-linux-gnuabin32 Patch by Yun Qiang Su. Differential revision: https://reviews.llvm.org/D50850 llvm-svn: 344608
2018-10-16 22:29:27 +08:00
// RUN: %clang_cc1 -triple mipsisa32r6-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-32EB
Update for llvm's DataLayout including mangling information. llvm-svn: 198439
2014-01-04 03:22:05 +08:00
// MIPS-32EB: target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
Consolidate DataLayout string testing in one file. llvm-svn: 197276
2013-12-14 05:49:53 +08:00
// RUN: %clang_cc1 -triple mips64el-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EL
[mips] Fix handling of GNUABIN32 environment in a target triple The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 llvm-svn: 344570
2018-10-16 06:43:23 +08:00
// RUN: %clang_cc1 -triple mips64el-linux-gnuabi64 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EL
[driver][mips] Support MIPS R6 target triples This change adds support for the following MIPS target triples: mipsisa32r6-linux-gnu mipsisa32r6el-linux-gnu mipsisa64r6-linux-gnuabi64 mipsisa64r6el-linux-gnuabi64 mipsisa64r6-linux-gnuabin32 mipsisa64r6el-linux-gnuabin32 Patch by Yun Qiang Su. Differential revision: https://reviews.llvm.org/D50850 llvm-svn: 344608
2018-10-16 22:29:27 +08:00
// RUN: %clang_cc1 -triple mipsisa64r6el-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EL
// RUN: %clang_cc1 -triple mipsisa64r6el-linux-gnuabi64 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EL
[mips] Group similar commands in the test case. NFC llvm-svn: 344583
2018-10-16 13:18:36 +08:00
// MIPS-64EL: target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
[mips] Fix handling of GNUABIN32 environment in a target triple The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 llvm-svn: 344570
2018-10-16 06:43:23 +08:00
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple mips64el-linux-gnu -o - -emit-llvm -target-abi n32 \
// RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32
[mips] Fix handling of GNUABIN32 environment in a target triple The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 llvm-svn: 344570
2018-10-16 06:43:23 +08:00
// RUN: %clang_cc1 -triple mips64el-linux-gnuabin32 -o - -emit-llvm \
// RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32
[driver][mips] Support MIPS R6 target triples This change adds support for the following MIPS target triples: mipsisa32r6-linux-gnu mipsisa32r6el-linux-gnu mipsisa64r6-linux-gnuabi64 mipsisa64r6el-linux-gnuabi64 mipsisa64r6-linux-gnuabin32 mipsisa64r6el-linux-gnuabin32 Patch by Yun Qiang Su. Differential revision: https://reviews.llvm.org/D50850 llvm-svn: 344608
2018-10-16 22:29:27 +08:00
// RUN: %clang_cc1 -triple mipsisa64r6el-linux-gnu -o - -emit-llvm -target-abi n32 \
// RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32
// RUN: %clang_cc1 -triple mipsisa64r6el-linux-gnuabin32 -o - -emit-llvm \
// RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32
[mips] Group similar commands in the test case. NFC llvm-svn: 344583
2018-10-16 13:18:36 +08:00
// MIPS-64EL-N32: target datalayout = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"
[mips] Fix handling of GNUABIN32 environment in a target triple The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 llvm-svn: 344570
2018-10-16 06:43:23 +08:00
Consolidate DataLayout string testing in one file. llvm-svn: 197276
2013-12-14 05:49:53 +08:00
// RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EB
[mips] Fix handling of GNUABIN32 environment in a target triple The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 llvm-svn: 344570
2018-10-16 06:43:23 +08:00
// RUN: %clang_cc1 -triple mips64-linux-gnuabi64 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EB
[driver][mips] Support MIPS R6 target triples This change adds support for the following MIPS target triples: mipsisa32r6-linux-gnu mipsisa32r6el-linux-gnu mipsisa64r6-linux-gnuabi64 mipsisa64r6el-linux-gnuabi64 mipsisa64r6-linux-gnuabin32 mipsisa64r6el-linux-gnuabin32 Patch by Yun Qiang Su. Differential revision: https://reviews.llvm.org/D50850 llvm-svn: 344608
2018-10-16 22:29:27 +08:00
// RUN: %clang_cc1 -triple mipsisa64r6-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EB
// RUN: %clang_cc1 -triple mipsisa64r6-linux-gnuabi64 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EB
[mips] Group similar commands in the test case. NFC llvm-svn: 344583
2018-10-16 13:18:36 +08:00
// MIPS-64EB: target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
[mips] Fix handling of GNUABIN32 environment in a target triple The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 llvm-svn: 344570
2018-10-16 06:43:23 +08:00
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s -target-abi n32 \
// RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32
[mips] Fix handling of GNUABIN32 environment in a target triple The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 llvm-svn: 344570
2018-10-16 06:43:23 +08:00
// RUN: %clang_cc1 -triple mips64-linux-gnuabin32 -o - -emit-llvm %s \
// RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32
[driver][mips] Support MIPS R6 target triples This change adds support for the following MIPS target triples: mipsisa32r6-linux-gnu mipsisa32r6el-linux-gnu mipsisa64r6-linux-gnuabi64 mipsisa64r6el-linux-gnuabi64 mipsisa64r6-linux-gnuabin32 mipsisa64r6el-linux-gnuabin32 Patch by Yun Qiang Su. Differential revision: https://reviews.llvm.org/D50850 llvm-svn: 344608
2018-10-16 22:29:27 +08:00
// RUN: %clang_cc1 -triple mipsisa64r6-linux-gnu -o - -emit-llvm %s -target-abi n32 \
// RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32
// RUN: %clang_cc1 -triple mipsisa64r6-linux-gnuabin32 -o - -emit-llvm %s \
// RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32
[mips] Group similar commands in the test case. NFC llvm-svn: 344583
2018-10-16 13:18:36 +08:00
// MIPS-64EB-N32: target datalayout = "E-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"
[mips] Fix handling of GNUABIN32 environment in a target triple The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 llvm-svn: 344570
2018-10-16 06:43:23 +08:00
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple powerpc64-lv2 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=PS3
Update for llvm's DataLayout including mangling information. llvm-svn: 198439
2014-01-04 03:22:05 +08:00
// PS3: target datalayout = "E-m:e-p:32:32-i64:64-n32:64"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple i686-nacl -o - -emit-llvm %s | \
Split this test into one per supporter nacl arch. Right now clang produces the same DataLayout for all of them, but it could, for example, add 'n' specifications when the end architecture is given. No functionality change, this should just make future changes easier to read. llvm-svn: 197549
2013-12-18 12:35:56 +08:00
// RUN: FileCheck %s -check-prefix=I686-NACL
Reland "Change the X86 datalayout to add three address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers." This reverts 57076d3199fc2b0af4a3736b7749dd5462cacda5. Original review at https://reviews.llvm.org/D64931. Review for added fix at https://reviews.llvm.org/D66843. llvm-svn: 371568
2019-09-11 07:15:38 +08:00
// I686-NACL: target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-n8:16:32-S128"
Split this test into one per supporter nacl arch. Right now clang produces the same DataLayout for all of them, but it could, for example, add 'n' specifications when the end architecture is given. No functionality change, this should just make future changes easier to read. llvm-svn: 197549
2013-12-18 12:35:56 +08:00
// RUN: %clang_cc1 -triple x86_64-nacl -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=X86_64-NACL
Reland "Change the X86 datalayout to add three address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers." This reverts 57076d3199fc2b0af4a3736b7749dd5462cacda5. Original review at https://reviews.llvm.org/D64931. Review for added fix at https://reviews.llvm.org/D66843. llvm-svn: 371568
2019-09-11 07:15:38 +08:00
// X86_64-NACL: target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-n8:16:32:64-S128"
Split this test into one per supporter nacl arch. Right now clang produces the same DataLayout for all of them, but it could, for example, add 'n' specifications when the end architecture is given. No functionality change, this should just make future changes easier to read. llvm-svn: 197549
2013-12-18 12:35:56 +08:00
Add driver support for Native Client SDK Add Tool and ToolChain support for clang to target the NaCl OS using the NaCl SDK for x86-32, x86-64 and ARM. Includes nacltools::Assemble and Link which are derived from gnutools. They are similar to Linux but different enought that they warrant their own class. Also includes a NaCl_TC in ToolChains derived from Generic_ELF with library and include paths suitable for an SDK and independent of the system tools. Differential Revision: http://reviews.llvm.org/D8590 llvm-svn: 233594
2015-03-31 04:31:33 +08:00
// RUN: %clang_cc1 -triple arm-nacl -o - -emit-llvm %s | \
Split this test into one per supporter nacl arch. Right now clang produces the same DataLayout for all of them, but it could, for example, add 'n' specifications when the end architecture is given. No functionality change, this should just make future changes easier to read. llvm-svn: 197549
2013-12-18 12:35:56 +08:00
// RUN: FileCheck %s -check-prefix=ARM-NACL
[IR][ARM] Add function pointer alignment to datalayout Use this feature to fix a bug on ARM where 4 byte alignment is incorrectly assumed. Differential Revision: https://reviews.llvm.org/D57335 llvm-svn: 355685
2019-03-08 18:44:06 +08:00
// ARM-NACL: target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128"
Split this test into one per supporter nacl arch. Right now clang produces the same DataLayout for all of them, but it could, for example, add 'n' specifications when the end architecture is given. No functionality change, this should just make future changes easier to read. llvm-svn: 197549
2013-12-18 12:35:56 +08:00
Add a test for mipsel-nacl too. llvm-svn: 197617
2013-12-19 06:40:42 +08:00
// RUN: %clang_cc1 -triple mipsel-nacl -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-NACL
Update for llvm's DataLayout including mangling information. llvm-svn: 198439
2014-01-04 03:22:05 +08:00
// MIPS-NACL: target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
Add a test for mipsel-nacl too. llvm-svn: 197617
2013-12-19 06:40:42 +08:00
[WebAssembly] Initial WebAssembly support in clang This implements basic support for compiling (though not yet assembling or linking) for a WebAssembly target. Note that ABI details are not yet finalized, and may change. Differential Revision: http://reviews.llvm.org/D12002 llvm-svn: 246814
2015-09-04 06:51:53 +08:00
// RUN: %clang_cc1 -triple wasm32-unknown-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=WEBASSEMBLY32
[WebAssembly] Implementation of table.get/set for reftypes in LLVM IR This change implements new DAG nodes TABLE_GET/TABLE_SET, and lowering methods for load and stores of reference types from IR arrays. These global LLVM IR arrays represent tables at the Wasm level. Differential Revision: https://reviews.llvm.org/D111154
2021-10-07 18:10:52 +08:00
// WEBASSEMBLY32: target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-n32:64-S128-ni:1:10:20"
[WebAssembly] Initial WebAssembly support in clang This implements basic support for compiling (though not yet assembling or linking) for a WebAssembly target. Note that ABI details are not yet finalized, and may change. Differential Revision: http://reviews.llvm.org/D12002 llvm-svn: 246814
2015-09-04 06:51:53 +08:00
// RUN: %clang_cc1 -triple wasm64-unknown-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=WEBASSEMBLY64
[WebAssembly] Implementation of table.get/set for reftypes in LLVM IR This change implements new DAG nodes TABLE_GET/TABLE_SET, and lowering methods for load and stores of reference types from IR arrays. These global LLVM IR arrays represent tables at the Wasm level. Differential Revision: https://reviews.llvm.org/D111154
2021-10-07 18:10:52 +08:00
// WEBASSEMBLY64: target datalayout = "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-n32:64-S128-ni:1:10:20"
[WebAssembly] Initial WebAssembly support in clang This implements basic support for compiling (though not yet assembling or linking) for a WebAssembly target. Note that ABI details are not yet finalized, and may change. Differential Revision: http://reviews.llvm.org/D12002 llvm-svn: 246814
2015-09-04 06:51:53 +08:00
[lanai] Add Lanai backend to clang driver. Changes to clang to add Lanai backend. Adds a new target, ABI and toolchain. General Lanai backend discussion on llvm-dev thread "[RFC] Lanai backend" (http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html). Differential Revision: http://reviews.llvm.org/D17002 llvm-svn: 264655
2016-03-29 05:02:54 +08:00
// RUN: %clang_cc1 -triple lanai-unknown-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=LANAI
// LANAI: target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple powerpc-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=PPC
Update for llvm's DataLayout including mangling information. llvm-svn: 198439
2014-01-04 03:22:05 +08:00
// PPC: target datalayout = "E-m:e-p:32:32-i64:64-n32"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
[PowerPC] Support powerpcle target in Clang [3/5] Add powerpcle support to clang. For FreeBSD, assume a freestanding environment for now, as we only need it in the first place to build loader, which runs in the OpenFirmware environment instead of the FreeBSD environment. For Linux, recognize glibc and musl environments to match current usage in Void Linux PPC. Adjust driver to match current binutils behavior regarding machine naming. Adjust and expand tests. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D93919
2021-01-03 02:17:58 +08:00
// RUN: %clang_cc1 -triple powerpcle-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=PPCLE
// PPCLE: target datalayout = "e-m:e-p:32:32-i64:64-n32"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple powerpc64-freebsd -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=PPC64-FREEBSD
Update for llvm's DataLayout including mangling information. llvm-svn: 198439
2014-01-04 03:22:05 +08:00
// PPC64-FREEBSD: target datalayout = "E-m:e-i64:64-n32:64"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
[PPC] Fix platform definitions when compiling FreeBSD powerpc64 as LE As a prerequisite to doing experimental buids of pieces of FreeBSD PowerPC64 as little-endian, allow actually targeting it. This is needed so basic platform definitions are pulled in. Without it, the compiler will only run freestanding. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D73425
2020-08-29 18:02:51 +08:00
// RUN: %clang_cc1 -triple powerpc64le-freebsd -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=PPC64LE-FREEBSD
// PPC64LE-FREEBSD: target datalayout = "e-m:e-i64:64-n32:64"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple powerpc64-linux -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=PPC64-LINUX
[PowerPC] Change target data layout for 16-byte stack alignment This changes the target data layout to make stack align to 16 bytes on Power10. Before this change, stack was being aligned to 32 bytes. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D96265
2021-02-08 22:36:20 +08:00
// PPC64-LINUX: target datalayout = "E-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
[PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types This patch legalizes the v256i1 and v512i1 types that will be used for MMA. It implements loads and stores of these types. v256i1 is a pair of VSX registers, so for this type, we load/store the two underlying registers. v512i1 is used for MMA accumulators. So in addition to loading and storing the 4 associated VSX registers, we generate instructions to prime (copy the VSX registers to the accumulator) after loading and unprime (copy the accumulator back to the VSX registers) before storing. This patch also adds the UACC register class that is necessary to implement the loads and stores. This class represents accumulator in their unprimed form and allow the distinction between primed and unprimed accumulators to avoid invalid copies of the VSX registers associated with primed accumulators. Differential Revision: https://reviews.llvm.org/D84968
2020-09-29 03:12:14 +08:00
// RUN: %clang_cc1 -triple powerpc64-linux -o - -emit-llvm -target-cpu future %s | \
// RUN: FileCheck %s -check-prefix=PPC64-FUTURE
[PowerPC] Change target data layout for 16-byte stack alignment This changes the target data layout to make stack align to 16 bytes on Power10. Before this change, stack was being aligned to 32 bytes. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D96265
2021-02-08 22:36:20 +08:00
// PPC64-FUTURE: target datalayout = "E-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
[PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types This patch legalizes the v256i1 and v512i1 types that will be used for MMA. It implements loads and stores of these types. v256i1 is a pair of VSX registers, so for this type, we load/store the two underlying registers. v512i1 is used for MMA accumulators. So in addition to loading and storing the 4 associated VSX registers, we generate instructions to prime (copy the VSX registers to the accumulator) after loading and unprime (copy the accumulator back to the VSX registers) before storing. This patch also adds the UACC register class that is necessary to implement the loads and stores. This class represents accumulator in their unprimed form and allow the distinction between primed and unprimed accumulators to avoid invalid copies of the VSX registers associated with primed accumulators. Differential Revision: https://reviews.llvm.org/D84968
2020-09-29 03:12:14 +08:00
// RUN: %clang_cc1 -triple powerpc64-linux -o - -emit-llvm -target-cpu pwr10 %s | \
// RUN: FileCheck %s -check-prefix=PPC64-P10
[PowerPC] Change target data layout for 16-byte stack alignment This changes the target data layout to make stack align to 16 bytes on Power10. Before this change, stack was being aligned to 32 bytes. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D96265
2021-02-08 22:36:20 +08:00
// PPC64-P10: target datalayout = "E-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
Update DataLayout/DescriptionString for ppc64le Update DataLayout/DescriptionString for ppc64le Similar LLVM change made in r203664 Testcase included. llvm-svn: 204613
2014-03-24 23:48:02 +08:00
// RUN: %clang_cc1 -triple powerpc64le-linux -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=PPC64LE-LINUX
[PowerPC] Change target data layout for 16-byte stack alignment This changes the target data layout to make stack align to 16 bytes on Power10. Before this change, stack was being aligned to 32 bytes. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D96265
2021-02-08 22:36:20 +08:00
// PPC64LE-LINUX: target datalayout = "e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
[PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types This patch legalizes the v256i1 and v512i1 types that will be used for MMA. It implements loads and stores of these types. v256i1 is a pair of VSX registers, so for this type, we load/store the two underlying registers. v512i1 is used for MMA accumulators. So in addition to loading and storing the 4 associated VSX registers, we generate instructions to prime (copy the VSX registers to the accumulator) after loading and unprime (copy the accumulator back to the VSX registers) before storing. This patch also adds the UACC register class that is necessary to implement the loads and stores. This class represents accumulator in their unprimed form and allow the distinction between primed and unprimed accumulators to avoid invalid copies of the VSX registers associated with primed accumulators. Differential Revision: https://reviews.llvm.org/D84968
2020-09-29 03:12:14 +08:00
// RUN: %clang_cc1 -triple powerpc64le-linux -o - -emit-llvm -target-cpu future %s | \
// RUN: FileCheck %s -check-prefix=PPC64LE-FUTURE
[PowerPC] Change target data layout for 16-byte stack alignment This changes the target data layout to make stack align to 16 bytes on Power10. Before this change, stack was being aligned to 32 bytes. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D96265
2021-02-08 22:36:20 +08:00
// PPC64LE-FUTURE: target datalayout = "e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
[PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types This patch legalizes the v256i1 and v512i1 types that will be used for MMA. It implements loads and stores of these types. v256i1 is a pair of VSX registers, so for this type, we load/store the two underlying registers. v512i1 is used for MMA accumulators. So in addition to loading and storing the 4 associated VSX registers, we generate instructions to prime (copy the VSX registers to the accumulator) after loading and unprime (copy the accumulator back to the VSX registers) before storing. This patch also adds the UACC register class that is necessary to implement the loads and stores. This class represents accumulator in their unprimed form and allow the distinction between primed and unprimed accumulators to avoid invalid copies of the VSX registers associated with primed accumulators. Differential Revision: https://reviews.llvm.org/D84968
2020-09-29 03:12:14 +08:00
// RUN: %clang_cc1 -triple powerpc64le-linux -o - -emit-llvm -target-cpu pwr10 %s | \
// RUN: FileCheck %s -check-prefix=PPC64LE-P10
[PowerPC] Change target data layout for 16-byte stack alignment This changes the target data layout to make stack align to 16 bytes on Power10. Before this change, stack was being aligned to 32 bytes. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D96265
2021-02-08 22:36:20 +08:00
// PPC64LE-P10: target datalayout = "e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
Update DataLayout/DescriptionString for ppc64le Update DataLayout/DescriptionString for ppc64le Similar LLVM change made in r203664 Testcase included. llvm-svn: 204613
2014-03-24 23:48:02 +08:00
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple nvptx-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=NVPTX
[NVPTX] Add lowering of i128 params. The patch adds support of i128 params lowering. The changes are quite trivial to support i128 as a "special case" of integer type. With this patch, we lower i128 params the same way as aggregates of size 16 bytes: .param .b8 _ [16]. Currently, NVPTX can't deal with the 128 bit integers: * in some cases because of failed assertions like ValVTs.size() == OutVals.size() && "Bad return value decomposition" * in other cases emitting PTX with .i128 or .u128 types (which are not valid [1]) [1] http://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fundamental-types Differential Revision: https://reviews.llvm.org/D34555 Patch by: Denys Zariaiev (denys.zariaiev@gmail.com) llvm-svn: 308675
2017-07-21 05:16:03 +08:00
// NVPTX: target datalayout = "e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple nvptx64-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=NVPTX64
[NVPTX] Add lowering of i128 params. The patch adds support of i128 params lowering. The changes are quite trivial to support i128 as a "special case" of integer type. With this patch, we lower i128 params the same way as aggregates of size 16 bytes: .param .b8 _ [16]. Currently, NVPTX can't deal with the 128 bit integers: * in some cases because of failed assertions like ValVTs.size() == OutVals.size() && "Bad return value decomposition" * in other cases emitting PTX with .i128 or .u128 types (which are not valid [1]) [1] http://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fundamental-types Differential Revision: https://reviews.llvm.org/D34555 Patch by: Denys Zariaiev (denys.zariaiev@gmail.com) llvm-svn: 308675
2017-07-21 05:16:03 +08:00
// NVPTX64: target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple r600-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=R600
[AMDGPU] Set the default globals address space to 1 This will ensure that passes that add new global variables will create them in address space 1 once the passes have been updated to no longer default to the implicit address space zero. This also changes AutoUpgrade.cpp to add -G1 to the DataLayout if it wasn't already to present to ensure bitcode backwards compatibility. Reviewed by: arsenm Differential Revision: https://reviews.llvm.org/D84345
2020-07-22 21:41:06 +08:00
// R600: target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple r600-unknown -target-cpu cayman -o - -emit-llvm %s \
// RUN: | FileCheck %s -check-prefix=R600D
[AMDGPU] Set the default globals address space to 1 This will ensure that passes that add new global variables will create them in address space 1 once the passes have been updated to no longer default to the implicit address space zero. This also changes AutoUpgrade.cpp to add -G1 to the DataLayout if it wasn't already to present to ensure bitcode backwards compatibility. Reviewed by: arsenm Differential Revision: https://reviews.llvm.org/D84345
2020-07-22 21:41:06 +08:00
// R600D: target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
R600: Handle amdgcn triple For now there is no difference between amdgcn and r600. llvm-svn: 225294
2015-01-07 04:34:47 +08:00
// RUN: %clang_cc1 -triple amdgcn-unknown -target-cpu hawaii -o - -emit-llvm %s \
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: | FileCheck %s -check-prefix=R600SI
[AMDGPU] Set the default globals address space to 1 This will ensure that passes that add new global variables will create them in address space 1 once the passes have been updated to no longer default to the implicit address space zero. This also changes AutoUpgrade.cpp to add -G1 to the DataLayout if it wasn't already to present to ensure bitcode backwards compatibility. Reviewed by: arsenm Differential Revision: https://reviews.llvm.org/D84345
2020-07-22 21:41:06 +08:00
// R600SI: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
R600: Use a Southern Islands GPU as the default for the amdgcn target llvm-svn: 227315
2015-01-28 23:38:44 +08:00
// Test default -target-cpu
// RUN: %clang_cc1 -triple amdgcn-unknown -o - -emit-llvm %s \
// RUN: | FileCheck %s -check-prefix=R600SIDefault
[AMDGPU] Set the default globals address space to 1 This will ensure that passes that add new global variables will create them in address space 1 once the passes have been updated to no longer default to the implicit address space zero. This also changes AutoUpgrade.cpp to add -G1 to the DataLayout if it wasn't already to present to ensure bitcode backwards compatibility. Reviewed by: arsenm Differential Revision: https://reviews.llvm.org/D84345
2020-07-22 21:41:06 +08:00
// R600SIDefault: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
R600: Use a Southern Islands GPU as the default for the amdgcn target llvm-svn: 227315
2015-01-28 23:38:44 +08:00
[ARM64] Port remaining relevant AArch64 clang tests over to ARM64 llvm-svn: 207632
2014-04-30 18:52:05 +08:00
// RUN: %clang_cc1 -triple arm64-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=AARCH64
[AArch64] Change the preferred alignment for char and short. This reinstates commits r273280 and r273289. Original Review: http://reviews.llvm.org/D21414. llvm-svn: 274791
2016-07-08 04:02:25 +08:00
// AARCH64: target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
AArch64: add arm64_32 support to Clang.
2018-09-18 17:34:39 +08:00
// RUN: %clang_cc1 -triple arm64_32-apple-ios7.0 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=AARCH64-ILP32
// AARCH64-ILP32: target datalayout = "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128"
Fix the data layout mangling specification for 'arm64-pc-win32-macho' rdar://problem/70410504
2020-11-11 10:36:10 +08:00
// RUN: %clang_cc1 -triple arm64-pc-win32-macho -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=AARCH64-WIN32-MACHO
// AARCH64-WIN32-MACHO: target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
Use triples that match the -target-abi option. llvm-svn: 197522
2013-12-18 05:01:22 +08:00
// RUN: %clang_cc1 -triple thumb-unknown-gnueabi -o - -emit-llvm %s | \
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: FileCheck %s -check-prefix=THUMB
[IR][ARM] Add function pointer alignment to datalayout Use this feature to fix a bug on ARM where 4 byte alignment is incorrectly assumed. Differential Revision: https://reviews.llvm.org/D57335 llvm-svn: 355685
2019-03-08 18:44:06 +08:00
// THUMB: target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
Use triples that match the -target-abi option. llvm-svn: 197522
2013-12-18 05:01:22 +08:00
// RUN: %clang_cc1 -triple arm-unknown-gnueabi -o - -emit-llvm %s | \
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: FileCheck %s -check-prefix=ARM
[IR][ARM] Add function pointer alignment to datalayout Use this feature to fix a bug on ARM where 4 byte alignment is incorrectly assumed. Differential Revision: https://reviews.llvm.org/D57335 llvm-svn: 355685
2019-03-08 18:44:06 +08:00
// ARM: target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple thumb-unknown -o - -emit-llvm -target-abi apcs-gnu \
// RUN: %s | FileCheck %s -check-prefix=THUMB-GNU
[IR][ARM] Add function pointer alignment to datalayout Use this feature to fix a bug on ARM where 4 byte alignment is incorrectly assumed. Differential Revision: https://reviews.llvm.org/D57335 llvm-svn: 355685
2019-03-08 18:44:06 +08:00
// THUMB-GNU: target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple arm-unknown -o - -emit-llvm -target-abi apcs-gnu \
// RUN: %s | FileCheck %s -check-prefix=ARM-GNU
[IR][ARM] Add function pointer alignment to datalayout Use this feature to fix a bug on ARM where 4 byte alignment is incorrectly assumed. Differential Revision: https://reviews.llvm.org/D57335 llvm-svn: 355685
2019-03-08 18:44:06 +08:00
// ARM-GNU: target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
[clang][ARC] Add ARCTargetInfo Based-on-patch-by: Pete Couperus <petecoup@synopsys.com> Differential Revision: https://reviews.llvm.org/D53100 llvm-svn: 347699
2018-11-28 03:52:10 +08:00
// RUN: %clang_cc1 -triple arc-unknown-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=ARC
// ARC: target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-f32:32:32-i64:32-f64:32-a:0:32-n32"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple hexagon-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=HEXAGON
[Hexagon] Specify vector alignment in DataLayout string The DataLayout can calculate alignment of vectors based on the alignment of the element type and the number of elements. In fact, it is the product of these two values. The problem is that for vectors of N x i1, this will return the alignment of N bytes, since the alignment of i1 is 8 bits. The vector types of vNi1 should be aligned to N bits instead. Provide explicit alignment for HVX vectors to avoid such complications. llvm-svn: 260680
2016-02-12 22:48:34 +08:00
// HEXAGON: target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
[SytemZ] Disable vector ABI when using option -march=arch[8|9|10] When specifying -march=arch[8|9|10], those CPU types do NOT support the vector extension. In this case the vector ABI must be disabled. The generated data layout should NOT contain 64-v128. Reviewers: uweigand Differential Revision: https://reviews.llvm.org/D74146
2020-02-06 04:08:19 +08:00
// RUN: %clang_cc1 -triple s390x-unknown -target-cpu z10 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SYSTEMZ
[SystemZ] Support -msoft-float This is needed when building the Linux kernel. Review: Ulrich Weigand Differential Revision: https://reviews.llvm.org/D72189
2020-01-04 07:39:07 +08:00
// RUN: %clang_cc1 -triple s390x-unknown -target-cpu z13 -target-feature +soft-float -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SYSTEMZ
Update for llvm's DataLayout including mangling information. llvm-svn: 198439
2014-01-04 03:22:05 +08:00
// SYSTEMZ: target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
[SystemZ] Add support for z13 and its vector facility This patch adds support for the z13 architecture type. For compatibility with GCC, a pair of options -mvx / -mno-vx can be used to selectively enable/disable use of the vector facility. When the vector facility is present, we default to the new vector ABI. This is characterized by two major differences: - Vector types are passed/returned in vector registers (except for unnamed arguments of a variable-argument list function). - Vector types are at most 8-byte aligned. The reason for the choice of 8-byte vector alignment is that the hardware is able to efficiently load vectors at 8-byte alignment, and the ABI only guarantees 8-byte alignment of the stack pointer, so requiring any higher alignment for vectors would require dynamic stack re-alignment code. However, for compatibility with old code that may use vector types, when *not* using the vector facility, the old alignment rules (vector types are naturally aligned) remain in use. These alignment rules are not only implemented at the C language level, but also at the LLVM IR level. This is done by selecting a different DataLayout string depending on whether the vector ABI is in effect or not. Based on a patch by Richard Sandiford. llvm-svn: 236531
2015-05-06 03:35:52 +08:00
// RUN: %clang_cc1 -triple s390x-unknown -target-cpu z13 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SYSTEMZ-VECTOR
// SYSTEMZ-VECTOR: target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
[SystemZ][z/OS] Add GOFF Support to the DataLayout - This patch adds in the GOFF mangling support to the LLVM data layout string. A corresponding additional line has been added into the data layout section in the language reference documentation. - Furthermore, this patch also sets the right data layout string for the z/OS target in the SystemZ backend. Reviewed By: uweigand, Kai, abhina.sreeskantharajan, MaskRay Differential Revision: https://reviews.llvm.org/D109362
2021-09-25 02:05:55 +08:00
// RUN: %clang_cc1 -triple s390x-none-zos -target-cpu z10 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=ZOS
// RUN: %clang_cc1 -triple s390x-none-zos -target-cpu z13 -target-feature +soft-float -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=ZOS
// RUN: %clang_cc1 -triple s390x-none-zos -target-cpu z13 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=ZOS
// ZOS: target datalayout = "E-m:l-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple msp430-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MSP430
[MSP430] Fix data layout string. Summary: Change data layout string so it would be compatible with MSP430 EABI. Depends on D34561 Reviewers: asl, awygle Reviewed By: asl Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D34562 llvm-svn: 306161
2017-06-24 05:12:56 +08:00
// MSP430: target datalayout = "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple tce-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=TCE
target-data test update for TCE and TCELE llvm-svn: 287115
2016-11-17 00:21:59 +08:00
// TCE: target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:32-v128:32:32-v256:32:32-v512:32:32-v1024:32:32-a0:0:32-n32"
// RUN: %clang_cc1 -triple tcele-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=TCELE
// TCELE: target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:32-v128:32:32-v256:32:32-v512:32:32-v1024:32:32-a0:0:32-n32"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple spir-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SPIR
The preferred alignment defaults to the ABI one. Omit it if it is the same. llvm-svn: 197440
2013-12-17 07:27:41 +08:00
// SPIR: target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
Add tests for all DescriptionString in Targets.cpp. These right now just test that the same string is present in two files, but will become more useful as clang's handling of DataLayout is refactored. llvm-svn: 197347
2013-12-16 01:53:44 +08:00
// RUN: %clang_cc1 -triple spir64-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=SPIR64
The preferred alignment defaults to the ABI one. Omit it if it is the same. llvm-svn: 197440
2013-12-17 07:27:41 +08:00
// SPIR64: target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
[bpf] add support for BPF backend add support for bpfel/bpfeb targets llvm-svn: 239496
2015-06-11 06:59:13 +08:00
// RUN: %clang_cc1 -triple bpfel -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=BPFEL
[BPF] support 128bit int explicitly in layout spec Currently, bpf does not specify 128bit alignment in its layout spec. So for a structure like struct ipv6_key_t { unsigned pid; unsigned __int128 saddr; unsigned short lport; }; clang will generate IR type %struct.ipv6_key_t = type { i32, [12 x i8], i128, i16, [14 x i8] } Additional padding is to ensure later IR->MIR can generate correct stack layout with target layout spec. But it is common practice for a tracing program to be first compiled with target flag (e.g., x86_64 or aarch64) through clang to generate IR and then go through llc to generate bpf byte code. Tracing program often refers to kernel internal data structures which needs to be compiled with non-bpf target. But such a compilation model may cause a problem on aarch64. The bcc issue https://github.com/iovisor/bcc/issues/2827 reported such a problem. For the above structure, since aarch64 has "i128:128" in its layout string, the generated IR will have %struct.ipv6_key_t = type { i32, i128, i16 } Since bpf does not have "i128:128" in its spec string, the selectionDAG assumes alignment 8 for i128 and computes the stack storage size for the above is 32 bytes, which leads incorrect code later. The x86_64 does not have this issue as it does not have "i128:128" in its layout spec as it does permits i128 to be alignmented at 8 bytes at stack. Its IR type looks like %struct.ipv6_key_t = type { i32, [12 x i8], i128, i16, [14 x i8] } The fix here is add i128 support in layout spec, the same as aarch64. The only downside is we may have less optimal stack allocation in certain cases since we require 16byte alignment for i128 instead of 8. But this is probably fine as i128 is not used widely and in most cases users should already have proper alignment. Differential Revision: https://reviews.llvm.org/D76587
2020-03-22 13:54:20 +08:00
// BPFEL: target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
[bpf] add support for BPF backend add support for bpfel/bpfeb targets llvm-svn: 239496
2015-06-11 06:59:13 +08:00
// RUN: %clang_cc1 -triple bpfeb -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=BPFEB
[BPF] support 128bit int explicitly in layout spec Currently, bpf does not specify 128bit alignment in its layout spec. So for a structure like struct ipv6_key_t { unsigned pid; unsigned __int128 saddr; unsigned short lport; }; clang will generate IR type %struct.ipv6_key_t = type { i32, [12 x i8], i128, i16, [14 x i8] } Additional padding is to ensure later IR->MIR can generate correct stack layout with target layout spec. But it is common practice for a tracing program to be first compiled with target flag (e.g., x86_64 or aarch64) through clang to generate IR and then go through llc to generate bpf byte code. Tracing program often refers to kernel internal data structures which needs to be compiled with non-bpf target. But such a compilation model may cause a problem on aarch64. The bcc issue https://github.com/iovisor/bcc/issues/2827 reported such a problem. For the above structure, since aarch64 has "i128:128" in its layout string, the generated IR will have %struct.ipv6_key_t = type { i32, i128, i16 } Since bpf does not have "i128:128" in its spec string, the selectionDAG assumes alignment 8 for i128 and computes the stack storage size for the above is 32 bytes, which leads incorrect code later. The x86_64 does not have this issue as it does not have "i128:128" in its layout spec as it does permits i128 to be alignmented at 8 bytes at stack. Its IR type looks like %struct.ipv6_key_t = type { i32, [12 x i8], i128, i16, [14 x i8] } The fix here is add i128 support in layout spec, the same as aarch64. The only downside is we may have less optimal stack allocation in certain cases since we require 16byte alignment for i128 instead of 8. But this is probably fine as i128 is not used widely and in most cases users should already have proper alignment. Differential Revision: https://reviews.llvm.org/D76587
2020-03-22 13:54:20 +08:00
// BPFEB: target datalayout = "E-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
[VE] Correct stack alignment Summary: Change stack alignment from 64 bits to 128 bits to follow ABI correctly. And add a regression test for datalayout. Reviewers: simoll, k-ishizaka Reviewed By: simoll Subscribers: hiraditya, cfe-commits, llvm-commits Tags: #llvm, #ve, #clang Differential Revision: https://reviews.llvm.org/D83173
2020-07-06 15:46:52 +08:00
// RUN: %clang_cc1 -triple ve -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=VE
[VE] Specify vector alignments Specify alignments for all vector types. Update a regression test also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92256
2020-11-28 10:58:44 +08:00
// VE: target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v512:64:64-v1024:64:64-v2048:64:64-v4096:64:64-v8192:64:64-v16384:64:64"