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llvm-project/llvm/test/CodeGen/AArch64/bitreverse.ll

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[SDAG] Introduce a new BITREVERSE node along with a corresponding LLVM intrinsic Several backends have instructions to reverse the order of bits in an integer. Conceptually matching such patterns is similar to @llvm.bswap, and it was mentioned in http://reviews.llvm.org/D14234 that it would be best if these patterns were matched in InstCombine instead of reimplemented in every different target. This patch introduces an intrinsic @llvm.bitreverse.i* that operates similarly to @llvm.bswap. For plumbing purposes there is also a new ISD node ISD::BITREVERSE, with simple expansion and promotion support. The intention is that InstCombine's BSWAP detection logic will be extended to support BITREVERSE too, and @llvm.bitreverse intrinsics emitted (if the backend supports lowering it efficiently). llvm-svn: 252878
2015-11-12 20:29:09 +08:00
; RUN: llc -mtriple=aarch64-eabi %s -o - | FileCheck %s
; These tests just check that the plumbing is in place for @llvm.bitreverse. The
; actual output is massive at the moment as llvm.bitreverse is not yet legal.
declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
define <2 x i16> @f(<2 x i16> %a) {
; CHECK-LABEL: f:
; CHECK: ushr
%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
ret <2 x i16> %b
}
declare i8 @llvm.bitreverse.i8(i8) readnone
[AArch64] Check the expansion of BITREVERSE in regression test Something I missed from Hal's review, rightly pointed out by Ben Kramer - we should make sure the expansion is properly checked as it can be easy for bugs to creep in. I've checked the scalar i8 expansion here and the vector i8 expansion in a previous commit. llvm-svn: 253024
2015-11-13 18:05:31 +08:00
; Unfortunately some of the shift-and-inserts become BFIs, and some do not :(
[SDAG] Introduce a new BITREVERSE node along with a corresponding LLVM intrinsic Several backends have instructions to reverse the order of bits in an integer. Conceptually matching such patterns is similar to @llvm.bswap, and it was mentioned in http://reviews.llvm.org/D14234 that it would be best if these patterns were matched in InstCombine instead of reimplemented in every different target. This patch introduces an intrinsic @llvm.bitreverse.i* that operates similarly to @llvm.bswap. For plumbing purposes there is also a new ISD node ISD::BITREVERSE, with simple expansion and promotion support. The intention is that InstCombine's BSWAP detection logic will be extended to support BITREVERSE too, and @llvm.bitreverse intrinsics emitted (if the backend supports lowering it efficiently). llvm-svn: 252878
2015-11-12 20:29:09 +08:00
define i8 @g(i8 %a) {
; CHECK-LABEL: g:
[AArch64] Check the expansion of BITREVERSE in regression test Something I missed from Hal's review, rightly pointed out by Ben Kramer - we should make sure the expansion is properly checked as it can be easy for bugs to creep in. I've checked the scalar i8 expansion here and the vector i8 expansion in a previous commit. llvm-svn: 253024
2015-11-13 18:05:31 +08:00
; CHECK-DAG: lsr [[S5:w.*]], w0, #5
; CHECK-DAG: lsr [[S4:w.*]], w0, #4
; CHECK-DAG: lsr [[S3:w.*]], w0, #3
; CHECK-DAG: lsr [[S2:w.*]], w0, #2
; CHECK-DAG: lsl [[L1:w.*]], w0, #29
; CHECK-DAG: lsl [[L2:w.*]], w0, #19
; CHECK-DAG: lsl [[L3:w.*]], w0, #17
; CHECK-DAG: and [[T1:w.*]], [[L1]], #0x40000000
; CHECK-DAG: bfi [[T1]], w0, #31, #1
; CHECK-DAG: bfi [[T1]], [[S2]], #29, #1
; CHECK-DAG: bfi [[T1]], [[S3]], #28, #1
; CHECK-DAG: bfi [[T1]], [[S4]], #27, #1
; CHECK-DAG: bfi [[T1]], [[S5]], #26, #1
; CHECK-DAG: and [[T2:w.*]], [[L2]], #0x2000000
; CHECK-DAG: and [[T3:w.*]], [[L3]], #0x1000000
; CHECK-DAG: orr [[T4:w.*]], [[T1]], [[T2]]
; CHECK-DAG: orr [[T5:w.*]], [[T4]], [[T3]]
; CHECK: lsr w0, [[T5]], #24
[SDAG] Introduce a new BITREVERSE node along with a corresponding LLVM intrinsic Several backends have instructions to reverse the order of bits in an integer. Conceptually matching such patterns is similar to @llvm.bswap, and it was mentioned in http://reviews.llvm.org/D14234 that it would be best if these patterns were matched in InstCombine instead of reimplemented in every different target. This patch introduces an intrinsic @llvm.bitreverse.i* that operates similarly to @llvm.bswap. For plumbing purposes there is also a new ISD node ISD::BITREVERSE, with simple expansion and promotion support. The intention is that InstCombine's BSWAP detection logic will be extended to support BITREVERSE too, and @llvm.bitreverse intrinsics emitted (if the backend supports lowering it efficiently). llvm-svn: 252878
2015-11-12 20:29:09 +08:00
%b = call i8 @llvm.bitreverse.i8(i8 %a)
ret i8 %b
}
[SDAG] Fix expansion of BITREVERSE Richard Trieu noted that UBSan detected an overflowing shift, and the obvious fix caused a crash. What was happening was that the shiftee (1U) was indeed too small for the possible range of shifts it had to handle, but also we were using "VT.getSizeInBits()" to get the maximum type bitwidth, but we wanted "VT.getScalarSizeInBits()" to get the vector lane size instead of the entire vector size. Use an APInt for the shift and VT.getScalarSizeInBits(). llvm-svn: 253023
2015-11-13 18:02:36 +08:00
declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>) readnone
define <8 x i8> @g_vec(<8 x i8> %a) {
; Try and match as much of the sequence as precisely as possible.
; CHECK-LABEL: g_vec:
; CHECK-DAG: movi [[M1:v.*]], #0x80
; CHECK-DAG: movi [[M2:v.*]], #0x40
; CHECK-DAG: movi [[M3:v.*]], #0x20
; CHECK-DAG: movi [[M4:v.*]], #0x10
; CHECK-DAG: movi [[M5:v.*]], #0x8
; CHECK-DAG: movi [[M6:v.*]], #0x4{{$}}
; CHECK-DAG: movi [[M7:v.*]], #0x2{{$}}
; CHECK-DAG: movi [[M8:v.*]], #0x1{{$}}
; CHECK-DAG: shl [[S1:v.*]], v0.8b, #7
; CHECK-DAG: shl [[S2:v.*]], v0.8b, #5
; CHECK-DAG: shl [[S3:v.*]], v0.8b, #3
; CHECK-DAG: shl [[S4:v.*]], v0.8b, #1
; CHECK-DAG: ushr [[S5:v.*]], v0.8b, #1
; CHECK-DAG: ushr [[S6:v.*]], v0.8b, #3
; CHECK-DAG: ushr [[S7:v.*]], v0.8b, #5
; CHECK-DAG: ushr [[S8:v.*]], v0.8b, #7
; CHECK-DAG: and [[A1:v.*]], [[S1]], [[M1]]
; CHECK-DAG: and [[A2:v.*]], [[S2]], [[M2]]
; CHECK-DAG: and [[A3:v.*]], [[S3]], [[M3]]
; CHECK-DAG: and [[A4:v.*]], [[S4]], [[M4]]
; CHECK-DAG: and [[A5:v.*]], [[S5]], [[M5]]
; CHECK-DAG: and [[A6:v.*]], [[S6]], [[M6]]
; CHECK-DAG: and [[A7:v.*]], [[S7]], [[M7]]
; CHECK-DAG: and [[A8:v.*]], [[S8]], [[M8]]
; The rest can be ORRed together in any order; it's not worth the test
; maintenance to match them precisely.
; CHECK-DAG: orr
; CHECK-DAG: orr
; CHECK-DAG: orr
; CHECK-DAG: orr
; CHECK-DAG: orr
; CHECK-DAG: orr
; CHECK-DAG: orr
; CHECK: ret
%b = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %a)
ret <8 x i8> %b
}