forked from OSchip/llvm-project
56 lines
1.5 KiB
Plaintext
56 lines
1.5 KiB
Plaintext
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{
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"arrays" : [
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{
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"name" : "MemRef_C1",
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"sizes" : [ "*" ],
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"type" : "double"
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},
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{
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"name" : "MemRef_A",
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"sizes" : [ "*", "1024" ],
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"type" : "double"
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},
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{
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"name" : "MemRef_B",
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"sizes" : [ "*", "1024" ],
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"type" : "double"
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},
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{
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"name" : "MemRef_C",
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"sizes" : [ "*", "1024" ],
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"type" : "double"
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}
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],
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"context" : "{ : }",
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"name" : "%for.body---%for.end24",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "{ Stmt_for_body6[i0, i1, i2] -> MemRef_C1[0] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_for_body6[i0, i1, i2] -> MemRef_A[i0, i2] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_for_body6[i0, i1, i2] -> MemRef_B[i2, i1] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_for_body6[i0, i1, i2] -> MemRef_C[i0, i1] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_for_body6[i0, i1, i2] -> MemRef_C[i0, i1] }"
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}
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],
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"domain" : "{ Stmt_for_body6[i0, i1, i2] : 0 <= i0 <= 1023 and 0 <= i1 <= 1023 and 0 <= i2 <= 1023 }",
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"name" : "Stmt_for_body6",
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"schedule" : "{ Stmt_for_body6[i0, i1, i2] -> [i0, i1, i2] }"
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}
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]
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}
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