2005-10-16 13:39:50 +08:00
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//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
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2005-04-22 07:30:14 +08:00
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//
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2004-06-22 00:55:25 +08:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 07:30:14 +08:00
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//
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2004-06-22 00:55:25 +08:00
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//===----------------------------------------------------------------------===//
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2005-04-22 07:30:14 +08:00
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//
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2005-08-16 07:47:04 +08:00
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// Top-level implementation for the PowerPC target.
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2004-06-22 00:55:25 +08:00
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//
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//===----------------------------------------------------------------------===//
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2005-10-15 07:59:06 +08:00
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#include "PPCTargetMachine.h"
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2012-03-18 02:46:09 +08:00
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#include "PPC.h"
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2015-01-14 19:23:27 +08:00
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#include "PPCTargetObjectFile.h"
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2015-01-31 19:17:59 +08:00
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#include "PPCTargetTransformInfo.h"
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2012-02-03 13:12:41 +08:00
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#include "llvm/CodeGen/Passes.h"
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2014-10-06 14:45:36 +08:00
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#include "llvm/IR/Function.h"
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2015-02-13 18:01:29 +08:00
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#include "llvm/IR/LegacyPassManager.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/MC/MCStreamer.h"
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2012-06-08 23:38:21 +08:00
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#include "llvm/Support/CommandLine.h"
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2009-07-15 04:18:05 +08:00
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#include "llvm/Support/FormattedStream.h"
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2011-08-25 02:08:43 +08:00
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#include "llvm/Support/TargetRegistry.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Target/TargetOptions.h"
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2014-11-21 12:35:51 +08:00
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#include "llvm/Transforms/Scalar.h"
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2004-06-22 00:55:25 +08:00
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using namespace llvm;
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2012-06-08 23:38:21 +08:00
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static cl::
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2012-06-09 03:19:53 +08:00
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opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
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cl::desc("Disable CTR loops for PPC"));
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2012-06-08 23:38:21 +08:00
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[PowerPC] Prepare loops for pre-increment loads/stores
PowerPC supports pre-increment load/store instructions (except for Altivec/VSX
vector load/stores). Using these on embedded cores can be very important, but
most loops are not naturally set up to use them. We can often change that,
however, by placing loops into a non-canonical form. Generically, this means
transforming loops like this:
for (int i = 0; i < n; ++i)
array[i] = c;
to look like this:
T *p = array[-1];
for (int i = 0; i < n; ++i)
*++p = c;
the key point is that addresses accessed are pulled into dedicated PHIs and
"pre-decremented" in the loop preheader. This allows the use of pre-increment
load/store instructions without loop peeling.
A target-specific late IR-level pass (running post-LSR), PPCLoopPreIncPrep, is
introduced to perform this transformation. I've used this code out-of-tree for
generating code for the PPC A2 for over a year. Somewhat to my surprise,
running the test suite + externals on a P7 with this transformation enabled
showed no performance regressions, and one speedup:
External/SPEC/CINT2006/483.xalancbmk/483.xalancbmk
-2.32514% +/- 1.03736%
So I'm going to enable it on everything for now. I was surprised by this
because, on the POWER cores, these pre-increment load/store instructions are
cracked (and, thus, harder to schedule effectively). But seeing no regressions,
and feeling that it is generally easier to split instructions apart late than
it is to combine them late, this might be the better approach regardless.
In the future, we might want to integrate this functionality into LSR (but
currently LSR does not create new PHI nodes, so (for that and other reasons)
significant work would need to be done).
llvm-svn: 228328
2015-02-06 02:43:00 +08:00
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static cl::
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opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
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cl::desc("Disable PPC loop preinc prep"));
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[PowerPC] Select between VSX A-type and M-type FMA instructions just before RA
The VSX instruction set has two types of FMA instructions: A-type (where the
addend is taken from the output register) and M-type (where one of the product
operands is taken from the output register). This adds a small pass that runs
just after MI scheduling (and, thus, just before register allocation) that
mutates A-type instructions (that are created during isel) into M-type
instructions when:
1. This will eliminate an otherwise-necessary copy of the addend
2. One of the product operands is killed by the instruction
The "right" moment to make this decision is in between scheduling and register
allocation, because only there do we know whether or not one of the product
operands is killed by any particular instruction. Unfortunately, this also
makes the implementation somewhat complicated, because the MIs are not in SSA
form and we need to preserve the LiveIntervals analysis.
As a simple example, if we have:
%vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
%vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
%RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
...
%vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19,
%RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19
...
We can eliminate the copy by changing from the A-type to the
M-type instruction. This means:
%vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
%RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
is replaced by:
%vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9,
%RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9
and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
llvm-svn: 204768
2014-03-26 07:29:21 +08:00
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static cl::opt<bool>
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VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
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cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
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2014-11-21 12:35:51 +08:00
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static cl::opt<bool>
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EnableGEPOpt("ppc-gep-opt", cl::Hidden,
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cl::desc("Enable optimizations on complex GEPs"),
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cl::init(true));
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2009-07-25 14:49:55 +08:00
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extern "C" void LLVMInitializePowerPCTarget() {
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// Register the targets
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2012-02-03 13:12:30 +08:00
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RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
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2009-07-25 14:49:55 +08:00
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RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
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2013-07-26 09:35:43 +08:00
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RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
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2009-07-25 14:49:55 +08:00
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}
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2009-06-17 04:12:29 +08:00
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2015-01-27 03:03:15 +08:00
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/// Return the datalayout string of a subtarget.
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static std::string getDataLayoutString(const Triple &T) {
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bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
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std::string Ret;
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// Most PPC* platforms are big endian, PPC64LE is little endian.
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if (T.getArch() == Triple::ppc64le)
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Ret = "e";
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else
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Ret = "E";
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Ret += DataLayout::getManglingComponent(T);
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// PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
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// pointers.
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if (!is64Bit || T.getOS() == Triple::Lv2)
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Ret += "-p:32:32";
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// Note, the alignment values for f64 and i64 on ppc64 in Darwin
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// documentation are wrong; these are correct (i.e. "what gcc does").
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if (is64Bit || !T.isOSDarwin())
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Ret += "-i64:64";
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else
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Ret += "-f64:32:64";
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// PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
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if (is64Bit)
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Ret += "-n32:64";
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else
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Ret += "-n32";
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return Ret;
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}
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2014-10-02 04:38:26 +08:00
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static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
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std::string FullFS = FS;
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Triple TargetTriple(TT);
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// Make sure 64-bit features are available when CPUname is generic
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if (TargetTriple.getArch() == Triple::ppc64 ||
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TargetTriple.getArch() == Triple::ppc64le) {
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if (!FullFS.empty())
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FullFS = "+64bit," + FullFS;
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else
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FullFS = "+64bit";
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}
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if (OL >= CodeGenOpt::Default) {
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if (!FullFS.empty())
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FullFS = "+crbits," + FullFS;
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else
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FullFS = "+crbits";
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}
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[PowerPC] Loosen ELFv1 PPC64 func descriptor loads for indirect calls
Function pointers under PPC64 ELFv1 (which is used on PPC64/Linux on the
POWER7, A2 and earlier cores) are really pointers to a function descriptor, a
structure with three pointers: the actual pointer to the code to which to jump,
the pointer to the TOC needed by the callee, and an environment pointer. We
used to chain these loads, and make them opaque to the rest of the optimizer,
so that they'd always occur directly before the call. This is not necessary,
and in fact, highly suboptimal on embedded cores. Once the function pointer is
known, the loads can be performed ahead of time; in fact, they can be hoisted
out of loops.
Now these function descriptors are almost always generated by the linker, and
thus the contents of the descriptors are invariant. As a result, by default,
we'll mark the associated loads as invariant (allowing them to be hoisted out
of loops). I've added a target feature to turn this off, however, just in case
someone needs that option (constructing an on-stack descriptor, casting it to a
function pointer, and then calling it cannot be well-defined C/C++ code, but I
can imagine some JIT-compilation system doing so).
Consider this simple test:
$ cat call.c
typedef void (*fp)();
void bar(fp x) {
for (int i = 0; i < 1600000000; ++i)
x();
}
$ cat main.c
typedef void (*fp)();
void bar(fp x);
void foo() {}
int main() {
bar(foo);
}
On the PPC A2 (the BG/Q supercomputer), marking the function-descriptor loads
as invariant brings the execution time down to ~8 seconds from ~32 seconds with
the loads in the loop.
The difference on the POWER7 is smaller. Compiling with:
gcc -std=c99 -O3 -mcpu=native call.c main.c : ~6 seconds [this is 4.8.2]
clang -O3 -mcpu=native call.c main.c : ~5.3 seconds
clang -O3 -mcpu=native call.c main.c -mno-invariant-function-descriptors : ~4 seconds
(looks like we'd benefit from additional loop unrolling here, as a first
guess, because this is faster with the extra loads)
The -mno-invariant-function-descriptors will be added to Clang shortly.
llvm-svn: 226207
2015-01-16 05:17:34 +08:00
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if (OL != CodeGenOpt::None) {
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if (!FullFS.empty())
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FullFS = "+invariant-function-descriptors," + FullFS;
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else
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FullFS = "+invariant-function-descriptors";
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}
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2014-10-02 04:38:26 +08:00
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return FullFS;
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}
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2014-11-13 17:26:31 +08:00
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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// If it isn't a Mach-O file then it's going to be a linux ELF
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// object file.
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if (TT.isOSDarwin())
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return make_unique<TargetLoweringObjectFileMachO>();
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return make_unique<PPC64LinuxTargetObjectFile>();
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}
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2015-02-17 14:45:15 +08:00
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static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
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const TargetOptions &Options) {
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if (Options.MCOptions.getABIName().startswith("elfv1"))
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return PPCTargetMachine::PPC_ABI_ELFv1;
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else if (Options.MCOptions.getABIName().startswith("elfv2"))
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return PPCTargetMachine::PPC_ABI_ELFv2;
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assert(Options.MCOptions.getABIName().empty() &&
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"Unknown target-abi option!");
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if (!TT.isMacOSX()) {
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switch (TT.getArch()) {
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case Triple::ppc64le:
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return PPCTargetMachine::PPC_ABI_ELFv2;
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case Triple::ppc64:
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return PPCTargetMachine::PPC_ABI_ELFv1;
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default:
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// Fallthrough.
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;
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}
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}
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return PPCTargetMachine::PPC_ABI_UNKNOWN;
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}
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2014-10-02 04:38:26 +08:00
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// The FeatureString here is a little subtle. We are modifying the feature string
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// with what are (currently) non-function specific overrides as it goes into the
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// LLVMTargetMachine constructor and then using the stored value in the
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// Subtarget constructor below it.
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2014-06-11 08:53:17 +08:00
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PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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2011-07-20 15:51:56 +08:00
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Reloc::Model RM, CodeModel::Model CM,
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2014-08-09 12:38:56 +08:00
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CodeGenOpt::Level OL)
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2014-10-02 04:38:26 +08:00
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: LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
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CM, OL),
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2014-11-13 17:26:31 +08:00
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TLOF(createTLOF(Triple(getTargetTriple()))),
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2015-02-17 14:45:15 +08:00
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TargetABI(computeTargetABI(Triple(TT), Options)),
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2015-01-27 03:03:15 +08:00
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DL(getDataLayoutString(Triple(TT))), Subtarget(TT, CPU, TargetFS, *this) {
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2013-05-13 09:16:13 +08:00
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initAsmInfo();
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2005-10-16 13:39:50 +08:00
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}
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2014-11-21 07:37:18 +08:00
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PPCTargetMachine::~PPCTargetMachine() {}
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2011-12-20 10:50:00 +08:00
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void PPC32TargetMachine::anchor() { }
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2012-02-03 13:12:30 +08:00
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PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
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2011-07-20 15:51:56 +08:00
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StringRef CPU, StringRef FS,
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2011-12-03 06:16:29 +08:00
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const TargetOptions &Options,
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2011-11-16 16:38:26 +08:00
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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2014-08-09 12:38:56 +08:00
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: PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
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2006-06-16 09:37:27 +08:00
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}
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2011-12-20 10:50:00 +08:00
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void PPC64TargetMachine::anchor() { }
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2006-06-16 09:37:27 +08:00
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2012-02-03 13:12:30 +08:00
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PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
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2011-07-20 15:51:56 +08:00
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StringRef CPU, StringRef FS,
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2011-12-03 06:16:29 +08:00
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const TargetOptions &Options,
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2011-11-16 16:38:26 +08:00
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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2014-08-09 12:38:56 +08:00
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: PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
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2006-06-16 09:37:27 +08:00
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}
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2014-10-06 14:45:36 +08:00
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const PPCSubtarget *
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PPCTargetMachine::getSubtargetImpl(const Function &F) const {
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2015-02-14 10:54:07 +08:00
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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2014-10-06 14:45:36 +08:00
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
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}
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return I.get();
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}
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2004-08-11 15:40:04 +08:00
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2006-09-04 12:14:57 +08:00
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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2004-08-11 15:40:04 +08:00
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2012-02-03 13:12:41 +08:00
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namespace {
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/// PPC Code Generator Pass Configuration Options.
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class PPCPassConfig : public TargetPassConfig {
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public:
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2012-02-04 10:56:59 +08:00
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PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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2012-02-03 13:12:41 +08:00
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PPCTargetMachine &getPPCTargetMachine() const {
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return getTM<PPCTargetMachine>();
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}
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2014-09-24 04:46:49 +08:00
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void addIRPasses() override;
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2014-04-29 15:57:37 +08:00
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bool addPreISel() override;
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bool addILPOpts() override;
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bool addInstSelector() override;
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2014-12-12 05:26:47 +08:00
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void addPreRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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2012-02-03 13:12:41 +08:00
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};
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} // namespace
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2012-02-04 10:56:59 +08:00
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TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
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2012-06-09 11:14:50 +08:00
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return new PPCPassConfig(this, PM);
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2012-02-03 13:12:41 +08:00
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}
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2014-09-24 04:46:49 +08:00
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void PPCPassConfig::addIRPasses() {
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addPass(createAtomicExpandPass(&getPPCTargetMachine()));
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2014-11-21 12:35:51 +08:00
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if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
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// Call SeparateConstOffsetFromGEP pass to extract constants within indices
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// and lower a GEP with multiple indices to either arithmetic operations or
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// multiple GEPs with single index.
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addPass(createSeparateConstOffsetFromGEPPass(TM, true));
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// Call EarlyCSE pass to find and remove subexpressions in the lowered
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// result.
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addPass(createEarlyCSEPass());
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// Do loop invariant code motion in case part of the lowered result is
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// invariant.
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addPass(createLICMPass());
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}
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2014-09-24 04:46:49 +08:00
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TargetPassConfig::addIRPasses();
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}
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Implement PPC counter loops as a late IR-level pass
The old PPCCTRLoops pass, like the Hexagon pass version from which it was
derived, could only handle some simple loops in canonical form. We cannot
directly adapt the new Hexagon hardware loops pass, however, because the
Hexagon pass contains a fundamental assumption that non-constant-trip-count
loops will contain a guard, and this is not always true (the result being that
incorrect negative counts can be generated). With this commit, we replace the
pass with a late IR-level pass which makes use of SE to calculate the
backedge-taken counts and safely generate the loop-count expressions (including
any necessary max() parts). This IR level pass inserts custom intrinsics that
are lowered into the desired decrement-and-branch instructions.
The most fragile part of this new implementation is that interfering uses of
the counter register must be detected on the IR level (and, on PPC, this also
includes any indirect branches in addition to function calls). Also, to make
all of this work, we need a variant of the mtctr instruction that is marked
as having side effects. Without this, machine-code level CSE, DCE, etc.
illegally transform the resulting code. Hopefully, this can be improved
in the future.
This new pass is smaller than the original (and much smaller than the new
Hexagon hardware loops pass), and can handle many additional cases correctly.
In addition, the preheader-creation code has been copied from LoopSimplify, and
after we decide on where it belongs, this code will be refactored so that it
can be explicitly shared (making this implementation even smaller).
The new test-case files ctrloop-{le,lt,ne}.ll have been adapted from tests for
the new Hexagon pass. There are a few classes of loops that this pass does not
transform (noted by FIXMEs in the files), but these deficiencies can be
addressed within the SE infrastructure (thus helping many other passes as well).
llvm-svn: 181927
2013-05-16 05:37:41 +08:00
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bool PPCPassConfig::addPreISel() {
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[PowerPC] Prepare loops for pre-increment loads/stores
PowerPC supports pre-increment load/store instructions (except for Altivec/VSX
vector load/stores). Using these on embedded cores can be very important, but
most loops are not naturally set up to use them. We can often change that,
however, by placing loops into a non-canonical form. Generically, this means
transforming loops like this:
for (int i = 0; i < n; ++i)
array[i] = c;
to look like this:
T *p = array[-1];
for (int i = 0; i < n; ++i)
*++p = c;
the key point is that addresses accessed are pulled into dedicated PHIs and
"pre-decremented" in the loop preheader. This allows the use of pre-increment
load/store instructions without loop peeling.
A target-specific late IR-level pass (running post-LSR), PPCLoopPreIncPrep, is
introduced to perform this transformation. I've used this code out-of-tree for
generating code for the PPC A2 for over a year. Somewhat to my surprise,
running the test suite + externals on a P7 with this transformation enabled
showed no performance regressions, and one speedup:
External/SPEC/CINT2006/483.xalancbmk/483.xalancbmk
-2.32514% +/- 1.03736%
So I'm going to enable it on everything for now. I was surprised by this
because, on the POWER cores, these pre-increment load/store instructions are
cracked (and, thus, harder to schedule effectively). But seeing no regressions,
and feeling that it is generally easier to split instructions apart late than
it is to combine them late, this might be the better approach regardless.
In the future, we might want to integrate this functionality into LSR (but
currently LSR does not create new PHI nodes, so (for that and other reasons)
significant work would need to be done).
llvm-svn: 228328
2015-02-06 02:43:00 +08:00
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if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
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addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
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2012-06-09 03:19:53 +08:00
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if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
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Implement PPC counter loops as a late IR-level pass
The old PPCCTRLoops pass, like the Hexagon pass version from which it was
derived, could only handle some simple loops in canonical form. We cannot
directly adapt the new Hexagon hardware loops pass, however, because the
Hexagon pass contains a fundamental assumption that non-constant-trip-count
loops will contain a guard, and this is not always true (the result being that
incorrect negative counts can be generated). With this commit, we replace the
pass with a late IR-level pass which makes use of SE to calculate the
backedge-taken counts and safely generate the loop-count expressions (including
any necessary max() parts). This IR level pass inserts custom intrinsics that
are lowered into the desired decrement-and-branch instructions.
The most fragile part of this new implementation is that interfering uses of
the counter register must be detected on the IR level (and, on PPC, this also
includes any indirect branches in addition to function calls). Also, to make
all of this work, we need a variant of the mtctr instruction that is marked
as having side effects. Without this, machine-code level CSE, DCE, etc.
illegally transform the resulting code. Hopefully, this can be improved
in the future.
This new pass is smaller than the original (and much smaller than the new
Hexagon hardware loops pass), and can handle many additional cases correctly.
In addition, the preheader-creation code has been copied from LoopSimplify, and
after we decide on where it belongs, this code will be refactored so that it
can be explicitly shared (making this implementation even smaller).
The new test-case files ctrloop-{le,lt,ne}.ll have been adapted from tests for
the new Hexagon pass. There are a few classes of loops that this pass does not
transform (noted by FIXMEs in the files), but these deficiencies can be
addressed within the SE infrastructure (thus helping many other passes as well).
llvm-svn: 181927
2013-05-16 05:37:41 +08:00
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addPass(createPPCCTRLoops(getPPCTargetMachine()));
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2012-06-08 23:38:21 +08:00
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return false;
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}
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2013-04-06 07:29:01 +08:00
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bool PPCPassConfig::addILPOpts() {
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2014-05-22 07:40:26 +08:00
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addPass(&EarlyIfConverterID);
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return true;
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2013-04-06 07:29:01 +08:00
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}
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2012-02-03 13:12:41 +08:00
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bool PPCPassConfig::addInstSelector() {
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2005-08-18 03:33:30 +08:00
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// Install an instruction selector.
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2012-07-03 03:48:31 +08:00
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addPass(createPPCISelDag(getPPCTargetMachine()));
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Add a PPCCTRLoops verification pass
When asserts are enabled, this adds a verification pass for PPC counter-loop
formation. Unfortunately, without sacrificing code quality, there is no better
way of forming counter-based loops except at the (late) IR level. This means
that we need to recognize, at the IR level, anything which might turn into a
function call (or indirect branch). Because this is currently a finite set of
things, and because SelectionDAG lowering is basic-block local, this can be
done. Nevertheless, it is fragile, and failure results in a miscompile. This
verification pass checks that all (reachable) counter-based branches are
dominated by a loop mtctr instruction, and that no instructions in between
clobber the counter register. If these conditions are not satisfied, then an
ICE will be triggered.
In short, this is to help us sleep better at night.
llvm-svn: 182295
2013-05-21 00:08:17 +08:00
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#ifndef NDEBUG
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if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
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addPass(createPPCCTRLoopsVerify());
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#endif
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2014-05-22 09:21:35 +08:00
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addPass(createPPCVSXCopyPass());
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2006-09-04 12:14:57 +08:00
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return false;
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}
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2004-08-11 15:40:04 +08:00
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2014-12-12 05:26:47 +08:00
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void PPCPassConfig::addPreRegAlloc() {
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2014-05-22 09:21:35 +08:00
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initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
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insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
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&PPCVSXFMAMutateID);
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2015-02-11 03:09:05 +08:00
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if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
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addPass(createPPCTLSDynamicCallPass());
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[PowerPC] Select between VSX A-type and M-type FMA instructions just before RA
The VSX instruction set has two types of FMA instructions: A-type (where the
addend is taken from the output register) and M-type (where one of the product
operands is taken from the output register). This adds a small pass that runs
just after MI scheduling (and, thus, just before register allocation) that
mutates A-type instructions (that are created during isel) into M-type
instructions when:
1. This will eliminate an otherwise-necessary copy of the addend
2. One of the product operands is killed by the instruction
The "right" moment to make this decision is in between scheduling and register
allocation, because only there do we know whether or not one of the product
operands is killed by any particular instruction. Unfortunately, this also
makes the implementation somewhat complicated, because the MIs are not in SSA
form and we need to preserve the LiveIntervals analysis.
As a simple example, if we have:
%vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
%vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
%RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
...
%vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19,
%RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19
...
We can eliminate the copy by changing from the A-type to the
M-type instruction. This means:
%vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
%RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
is replaced by:
%vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9,
%RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9
and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
llvm-svn: 204768
2014-03-26 07:29:21 +08:00
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}
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2014-12-12 05:26:47 +08:00
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void PPCPassConfig::addPreSched2() {
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2013-04-10 06:58:37 +08:00
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if (getOptLevel() != CodeGenOpt::None)
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addPass(&IfConverterID);
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}
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2014-12-12 05:26:47 +08:00
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void PPCPassConfig::addPreEmitPass() {
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2013-04-09 00:24:03 +08:00
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if (getOptLevel() != CodeGenOpt::None)
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2014-12-12 05:26:47 +08:00
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addPass(createPPCEarlyReturnPass(), false);
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2006-09-04 12:14:57 +08:00
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// Must run branch selection immediately preceding the asm printer.
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2014-12-12 05:26:47 +08:00
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addPass(createPPCBranchSelectionPass(), false);
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2004-08-11 15:40:04 +08:00
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}
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2015-02-01 21:20:00 +08:00
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TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
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return TargetIRAnalysis(
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[this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });
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2013-01-26 07:05:59 +08:00
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}
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