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llvm-project/clang/test/Preprocessor/x86_target_features.c

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Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=core2 -msse4 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SSE4 %s
More x86 target feature support. - Apologies for the extremely gross code duplication, I want to get this working and then decide how to get this information out of the back end. - This replaces -m[no-]sse4[12] by -m[no-]sse4, it appears gcc doesn't distinguish them? - -msse, etc. now properly disable/enable related features. - Don't always define __SSE3__... - The main missing functionality bit here is that we don't initialize the features based on the CPU for all -march options. llvm-svn: 71117
2009-05-07 05:07:50 +08:00
Convert test to FileCheck. llvm-svn: 185645
2013-07-04 23:08:20 +08:00
// SSE4: #define __SSE2_MATH__ 1
// SSE4: #define __SSE2__ 1
// SSE4: #define __SSE3__ 1
// SSE4: #define __SSE4_1__ 1
// SSE4: #define __SSE4_2__ 1
// SSE4: #define __SSE_MATH__ 1
// SSE4: #define __SSE__ 1
// SSE4: #define __SSSE3__ 1
More x86 target feature support. - Apologies for the extremely gross code duplication, I want to get this working and then decide how to get this information out of the back end. - This replaces -m[no-]sse4[12] by -m[no-]sse4, it appears gcc doesn't distinguish them? - -msse, etc. now properly disable/enable related features. - Don't always define __SSE3__... - The main missing functionality bit here is that we don't initialize the features based on the CPU for all -march options. llvm-svn: 71117
2009-05-07 05:07:50 +08:00
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=core2 -msse4.1 -mno-sse4 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOSSE4 %s
Make the msse4/mno-sse4 flags aliases of the maximum sse values they enable/disable. This fixes two things: a) sse4 isn't actually a target feature, don't treat it as one. b) we weren't correctly disabling sse4.1 when we'd pass -mno-sse4 after enabling it, thus passing preprocessor directives and (soon) passing the function attribute as well when we shouldn't. llvm-svn: 233223
2015-03-26 06:09:26 +08:00
// NOSSE4-NOT: #define __SSE4_1__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=core2 -msse4 -mno-sse2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SSE %s
Handle -march for the LLVM recognized cpu names. - x86 target feature handling should not be feature complete, even if the code quality is lacking. llvm-svn: 71123
2009-05-07 05:56:32 +08:00
Convert test to FileCheck. llvm-svn: 185645
2013-07-04 23:08:20 +08:00
// SSE-NOT: #define __SSE2_MATH__ 1
// SSE-NOT: #define __SSE2__ 1
// SSE-NOT: #define __SSE3__ 1
// SSE-NOT: #define __SSE4_1__ 1
// SSE-NOT: #define __SSE4_2__ 1
// SSE: #define __SSE_MATH__ 1
// SSE: #define __SSE__ 1
// SSE-NOT: #define __SSSE3__ 1
More x86 target feature support. - Apologies for the extremely gross code duplication, I want to get this working and then decide how to get this information out of the back end. - This replaces -m[no-]sse4[12] by -m[no-]sse4, it appears gcc doesn't distinguish them? - -msse, etc. now properly disable/enable related features. - Don't always define __SSE3__... - The main missing functionality bit here is that we don't initialize the features based on the CPU for all -march options. llvm-svn: 71117
2009-05-07 05:07:50 +08:00
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentium-m -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SSE2 %s
More x86 target feature support. - Apologies for the extremely gross code duplication, I want to get this working and then decide how to get this information out of the back end. - This replaces -m[no-]sse4[12] by -m[no-]sse4, it appears gcc doesn't distinguish them? - -msse, etc. now properly disable/enable related features. - Don't always define __SSE3__... - The main missing functionality bit here is that we don't initialize the features based on the CPU for all -march options. llvm-svn: 71117
2009-05-07 05:07:50 +08:00
Convert test to FileCheck. llvm-svn: 185645
2013-07-04 23:08:20 +08:00
// SSE2: #define __SSE2_MATH__ 1
// SSE2: #define __SSE2__ 1
// SSE2-NOT: #define __SSE3__ 1
// SSE2-NOT: #define __SSE4_1__ 1
// SSE2-NOT: #define __SSE4_2__ 1
// SSE2: #define __SSE_MATH__ 1
// SSE2: #define __SSE__ 1
// SSE2-NOT: #define __SSSE3__ 1
Centralize the logic for handling -m* options and fix pr16943. This moves the logic for handling -mfoo -mno-foo from the driver to -cc1. It also changes -cc1 to apply the options in order, fixing pr16943. The handling of -mno-mmx -msse is now an explicit special case. llvm-svn: 188817
2013-08-21 02:57:55 +08:00
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentium-m -mno-sse -mavx -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX %s
Centralize the logic for handling -m* options and fix pr16943. This moves the logic for handling -mfoo -mno-foo from the driver to -cc1. It also changes -cc1 to apply the options in order, fixing pr16943. The handling of -mno-mmx -msse is now an explicit special case. llvm-svn: 188817
2013-08-21 02:57:55 +08:00
// AVX: #define __AVX__ 1
// AVX: #define __SSE2_MATH__ 1
// AVX: #define __SSE2__ 1
// AVX: #define __SSE3__ 1
// AVX: #define __SSE4_1__ 1
// AVX: #define __SSE4_2__ 1
// AVX: #define __SSE_MATH__ 1
// AVX: #define __SSE__ 1
// AVX: #define __SSSE3__ 1
Don't disable SSE4A when disabling AVX. Thanks for Craig Topper for noticing it. llvm-svn: 188902
2013-08-21 21:28:02 +08:00
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentium-m -mxop -mno-avx -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SSE4A %s
Don't disable SSE4A when disabling AVX. Thanks for Craig Topper for noticing it. llvm-svn: 188902
2013-08-21 21:28:02 +08:00
// SSE4A: #define __SSE2_MATH__ 1
// SSE4A: #define __SSE2__ 1
// SSE4A: #define __SSE3__ 1
// SSE4A: #define __SSE4A__ 1
// SSE4A: #define __SSE4_1__ 1
// SSE4A: #define __SSE4_2__ 1
// SSE4A: #define __SSE_MATH__ 1
// SSE4A: #define __SSE__ 1
// SSE4A: #define __SSSE3__ 1
Add test cases for avx512 feature flags. Fix typo in avx512pf options. llvm-svn: 188984
2013-08-22 12:32:55 +08:00
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512f -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512F %s
Add test cases for avx512 feature flags. Fix typo in avx512pf options. llvm-svn: 188984
2013-08-22 12:32:55 +08:00
// AVX512F: #define __AVX2__ 1
// AVX512F: #define __AVX512F__ 1
// AVX512F: #define __AVX__ 1
// AVX512F: #define __SSE2_MATH__ 1
// AVX512F: #define __SSE2__ 1
// AVX512F: #define __SSE3__ 1
// AVX512F: #define __SSE4_1__ 1
// AVX512F: #define __SSE4_2__ 1
// AVX512F: #define __SSE_MATH__ 1
// AVX512F: #define __SSE__ 1
// AVX512F: #define __SSSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512cd -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512CD %s
Add test cases for avx512 feature flags. Fix typo in avx512pf options. llvm-svn: 188984
2013-08-22 12:32:55 +08:00
// AVX512CD: #define __AVX2__ 1
// AVX512CD: #define __AVX512CD__ 1
// AVX512CD: #define __AVX512F__ 1
// AVX512CD: #define __AVX__ 1
// AVX512CD: #define __SSE2_MATH__ 1
// AVX512CD: #define __SSE2__ 1
// AVX512CD: #define __SSE3__ 1
// AVX512CD: #define __SSE4_1__ 1
// AVX512CD: #define __SSE4_2__ 1
// AVX512CD: #define __SSE_MATH__ 1
// AVX512CD: #define __SSE__ 1
// AVX512CD: #define __SSSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512er -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512ER %s
Add test cases for avx512 feature flags. Fix typo in avx512pf options. llvm-svn: 188984
2013-08-22 12:32:55 +08:00
// AVX512ER: #define __AVX2__ 1
// AVX512ER: #define __AVX512ER__ 1
// AVX512ER: #define __AVX512F__ 1
// AVX512ER: #define __AVX__ 1
// AVX512ER: #define __SSE2_MATH__ 1
// AVX512ER: #define __SSE2__ 1
// AVX512ER: #define __SSE3__ 1
// AVX512ER: #define __SSE4_1__ 1
// AVX512ER: #define __SSE4_2__ 1
// AVX512ER: #define __SSE_MATH__ 1
// AVX512ER: #define __SSE__ 1
// AVX512ER: #define __SSSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512pf -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512PF %s
Add test cases for avx512 feature flags. Fix typo in avx512pf options. llvm-svn: 188984
2013-08-22 12:32:55 +08:00
// AVX512PF: #define __AVX2__ 1
// AVX512PF: #define __AVX512F__ 1
// AVX512PF: #define __AVX512PF__ 1
// AVX512PF: #define __AVX__ 1
// AVX512PF: #define __SSE2_MATH__ 1
// AVX512PF: #define __SSE2__ 1
// AVX512PF: #define __SSE3__ 1
// AVX512PF: #define __SSE4_1__ 1
// AVX512PF: #define __SSE4_2__ 1
// AVX512PF: #define __SSE_MATH__ 1
// AVX512PF: #define __SSE__ 1
// AVX512PF: #define __SSSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512dq -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512DQ %s
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// AVX512DQ: #define __AVX2__ 1
// AVX512DQ: #define __AVX512DQ__ 1
// AVX512DQ: #define __AVX512F__ 1
// AVX512DQ: #define __AVX__ 1
// AVX512DQ: #define __SSE2_MATH__ 1
// AVX512DQ: #define __SSE2__ 1
// AVX512DQ: #define __SSE3__ 1
// AVX512DQ: #define __SSE4_1__ 1
// AVX512DQ: #define __SSE4_2__ 1
// AVX512DQ: #define __SSE_MATH__ 1
// AVX512DQ: #define __SSE__ 1
// AVX512DQ: #define __SSSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BW %s
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// AVX512BW: #define __AVX2__ 1
// AVX512BW: #define __AVX512BW__ 1
// AVX512BW: #define __AVX512F__ 1
// AVX512BW: #define __AVX__ 1
// AVX512BW: #define __SSE2_MATH__ 1
// AVX512BW: #define __SSE2__ 1
// AVX512BW: #define __SSE3__ 1
// AVX512BW: #define __SSE4_1__ 1
// AVX512BW: #define __SSE4_2__ 1
// AVX512BW: #define __SSE_MATH__ 1
// AVX512BW: #define __SSE__ 1
// AVX512BW: #define __SSSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vl -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512VL %s
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// AVX512VL: #define __AVX2__ 1
// AVX512VL: #define __AVX512F__ 1
// AVX512VL: #define __AVX512VL__ 1
// AVX512VL: #define __AVX__ 1
// AVX512VL: #define __SSE2_MATH__ 1
// AVX512VL: #define __SSE2__ 1
// AVX512VL: #define __SSE3__ 1
// AVX512VL: #define __SSE4_1__ 1
// AVX512VL: #define __SSE4_2__ 1
// AVX512VL: #define __SSE_MATH__ 1
// AVX512VL: #define __SSE__ 1
// AVX512VL: #define __SSSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512pf -mno-avx512f -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512F2 %s
Add test cases for avx512 feature flags. Fix typo in avx512pf options. llvm-svn: 188984
2013-08-22 12:32:55 +08:00
// AVX512F2: #define __AVX2__ 1
// AVX512F2-NOT: #define __AVX512F__ 1
// AVX512F2-NOT: #define __AVX512PF__ 1
// AVX512F2: #define __AVX__ 1
// AVX512F2: #define __SSE2_MATH__ 1
// AVX512F2: #define __SSE2__ 1
// AVX512F2: #define __SSE3__ 1
// AVX512F2: #define __SSE4_1__ 1
// AVX512F2: #define __SSE4_2__ 1
// AVX512F2: #define __SSE_MATH__ 1
// AVX512F2: #define __SSE__ 1
// AVX512F2: #define __SSSE3__ 1
Separate popcnt and sse4.2 feature control somewhat to match gcc behavior. Enabling sse4.2 will implicitly enable popcnt unless popcnt is explicitly disabled. Disabling sse4.2 will not disable popcnt if popcnt is explicitly enabled. llvm-svn: 190387
2013-09-10 14:55:47 +08:00
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512ifma -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512IFMA %s
[X86] Disabling avx512f should also disable avx512vbmi and avx512ifma. Enabling avx512vbmi or avx512ifma should enable avx512f. Add command line switches and header defines for avx512ifma and avx512vbmi. llvm-svn: 262201
2016-02-29 14:51:38 +08:00
// AVX512IFMA: #define __AVX2__ 1
// AVX512IFMA: #define __AVX512F__ 1
// AVX512IFMA: #define __AVX512IFMA__ 1
// AVX512IFMA: #define __AVX__ 1
// AVX512IFMA: #define __SSE2_MATH__ 1
// AVX512IFMA: #define __SSE2__ 1
// AVX512IFMA: #define __SSE3__ 1
// AVX512IFMA: #define __SSE4_1__ 1
// AVX512IFMA: #define __SSE4_2__ 1
// AVX512IFMA: #define __SSE_MATH__ 1
// AVX512IFMA: #define __SSE__ 1
// AVX512IFMA: #define __SSSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vbmi -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512VBMI %s
[X86] Disabling avx512f should also disable avx512vbmi and avx512ifma. Enabling avx512vbmi or avx512ifma should enable avx512f. Add command line switches and header defines for avx512ifma and avx512vbmi. llvm-svn: 262201
2016-02-29 14:51:38 +08:00
// AVX512VBMI: #define __AVX2__ 1
[AVX-512] Make VBMI instruction set enabling imply that the BWI instruction set is also enabled. Summary: This is needed to make the v64i8 and v32i16 types legal for the 512-bit VBMI instructions. Fixes PR30912. Reviewers: delena, zvi Subscribers: RKSimon, cfe-commits Differential Revision: https://reviews.llvm.org/D26306 llvm-svn: 286340
2016-11-09 12:51:03 +08:00
// AVX512VBMI: #define __AVX512BW__ 1
[X86] Disabling avx512f should also disable avx512vbmi and avx512ifma. Enabling avx512vbmi or avx512ifma should enable avx512f. Add command line switches and header defines for avx512ifma and avx512vbmi. llvm-svn: 262201
2016-02-29 14:51:38 +08:00
// AVX512VBMI: #define __AVX512F__ 1
// AVX512VBMI: #define __AVX512VBMI__ 1
// AVX512VBMI: #define __AVX__ 1
// AVX512VBMI: #define __SSE2_MATH__ 1
// AVX512VBMI: #define __SSE2__ 1
// AVX512VBMI: #define __SSE3__ 1
// AVX512VBMI: #define __SSE4_1__ 1
// AVX512VBMI: #define __SSE4_2__ 1
// AVX512VBMI: #define __SSE_MATH__ 1
// AVX512VBMI: #define __SSE__ 1
// AVX512VBMI: #define __SSSE3__ 1
[AVX-512] Make VBMI instruction set enabling imply that the BWI instruction set is also enabled. Summary: This is needed to make the v64i8 and v32i16 types legal for the 512-bit VBMI instructions. Fixes PR30912. Reviewers: delena, zvi Subscribers: RKSimon, cfe-commits Differential Revision: https://reviews.llvm.org/D26306 llvm-svn: 286340
2016-11-09 12:51:03 +08:00
[x86][icelake][bitalg] added bitalg feature recognition added intrinsics support for bitalg instructions _mm512_popcnt_epi16 _mm512_mask_popcnt_epi16 _mm512_maskz_popcnt_epi16 _mm512_popcnt_epi8 _mm512_mask_popcnt_epi8 _mm512_maskz_popcnt_epi8 _mm512_mask_bitshuffle_epi64_mask _mm512_bitshuffle_epi64_mask _mm256_popcnt_epi16 _mm256_mask_popcnt_epi16 _mm256_maskz_popcnt_epi16 _mm128_popcnt_epi16 _mm128_mask_popcnt_epi16 _mm128_maskz_popcnt_epi16 _mm256_popcnt_epi8 _mm256_mask_popcnt_epi8 _mm256_maskz_popcnt_epi8 _mm128_popcnt_epi8 _mm128_mask_popcnt_epi8 _mm128_maskz_popcnt_epi8 _mm256_mask_bitshuffle_epi32_mask _mm256_bitshuffle_epi32_mask _mm128_mask_bitshuffle_epi16_mask _mm128_bitshuffle_epi16_mask matching a similar work on the backend (D40222) Differential Revision: https://reviews.llvm.org/D41564 llvm-svn: 321483
2017-12-27 18:01:00 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bitalg -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BITALG %s
// AVX512BITALG: #define __AVX2__ 1
// AVX512BITALG: #define __AVX512BITALG__ 1
// AVX512BITALG: #define __AVX512BW__ 1
// AVX512BITALG: #define __AVX512F__ 1
// AVX512BITALG: #define __AVX__ 1
// AVX512BITALG: #define __SSE2_MATH__ 1
// AVX512BITALG: #define __SSE2__ 1
// AVX512BITALG: #define __SSE3__ 1
// AVX512BITALG: #define __SSE4_1__ 1
// AVX512BITALG: #define __SSE4_2__ 1
// AVX512BITALG: #define __SSE_MATH__ 1
// AVX512BITALG: #define __SSE__ 1
// AVX512BITALG: #define __SSSE3__ 1
[AVX-512] Make VBMI instruction set enabling imply that the BWI instruction set is also enabled. Summary: This is needed to make the v64i8 and v32i16 types legal for the 512-bit VBMI instructions. Fixes PR30912. Reviewers: delena, zvi Subscribers: RKSimon, cfe-commits Differential Revision: https://reviews.llvm.org/D26306 llvm-svn: 286340
2016-11-09 12:51:03 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vbmi -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512VBMINOAVX512BW %s
// AVX512VBMINOAVX512BW-NOT: #define __AVX512BW__ 1
// AVX512VBMINOAVX512BW-NOT: #define __AVX512VBMI__ 1
[X86] Disabling avx512f should also disable avx512vbmi and avx512ifma. Enabling avx512vbmi or avx512ifma should enable avx512f. Add command line switches and header defines for avx512ifma and avx512vbmi. llvm-svn: 262201
2016-02-29 14:51:38 +08:00
[x86][icelake][vbmi2] added vbmi2 feature recognition added intrinsics support for vbmi2 instructions _mm[128,256,512]_mask[z]_compress_epi[16,32] _mm[128,256,512]_mask_compressstoreu_epi[16,32] _mm[128,256,512]_mask[z]_expand_epi[16,32] _mm[128,256,512]_mask[z]_expandloadu_epi[16,32] _mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64] _mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64] matching a similar work on the backend (D40206) Differential Revision: https://reviews.llvm.org/D41557 llvm-svn: 321487
2017-12-27 19:25:07 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vbmi2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512VBMI2 %s
// AVX512VBMI2: #define __AVX2__ 1
// AVX512VBMI2: #define __AVX512BW__ 1
// AVX512VBMI2: #define __AVX512F__ 1
// AVX512VBMI2: #define __AVX512VBMI2__ 1
// AVX512VBMI2: #define __AVX__ 1
// AVX512VBMI2: #define __SSE2_MATH__ 1
// AVX512VBMI2: #define __SSE2__ 1
// AVX512VBMI2: #define __SSE3__ 1
// AVX512VBMI2: #define __SSE4_1__ 1
// AVX512VBMI2: #define __SSE4_2__ 1
// AVX512VBMI2: #define __SSE_MATH__ 1
// AVX512VBMI2: #define __SSE__ 1
// AVX512VBMI2: #define __SSSE3__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vbmi2 -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512VBMI2NOAVX512BW %s
// AVX512VBMI2NOAVX512BW-NOT: #define __AVX512BW__ 1
// AVX512VBMI2NOAVX512BW-NOT: #define __AVX512VBMI2__ 1
[x86][icelake][bitalg] added bitalg feature recognition added intrinsics support for bitalg instructions _mm512_popcnt_epi16 _mm512_mask_popcnt_epi16 _mm512_maskz_popcnt_epi16 _mm512_popcnt_epi8 _mm512_mask_popcnt_epi8 _mm512_maskz_popcnt_epi8 _mm512_mask_bitshuffle_epi64_mask _mm512_bitshuffle_epi64_mask _mm256_popcnt_epi16 _mm256_mask_popcnt_epi16 _mm256_maskz_popcnt_epi16 _mm128_popcnt_epi16 _mm128_mask_popcnt_epi16 _mm128_maskz_popcnt_epi16 _mm256_popcnt_epi8 _mm256_mask_popcnt_epi8 _mm256_maskz_popcnt_epi8 _mm128_popcnt_epi8 _mm128_mask_popcnt_epi8 _mm128_maskz_popcnt_epi8 _mm256_mask_bitshuffle_epi32_mask _mm256_bitshuffle_epi32_mask _mm128_mask_bitshuffle_epi16_mask _mm128_bitshuffle_epi16_mask matching a similar work on the backend (D40222) Differential Revision: https://reviews.llvm.org/D41564 llvm-svn: 321483
2017-12-27 18:01:00 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bitalg -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BITALGNOAVX512BW %s
// AVX512BITALGNOAVX512BW-NOT: #define __AVX512BITALG__ 1
// AVX512BITALGNOAVX512BW-NOT: #define __AVX512BW__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -msse4.2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SSE42POPCNT %s
Separate popcnt and sse4.2 feature control somewhat to match gcc behavior. Enabling sse4.2 will implicitly enable popcnt unless popcnt is explicitly disabled. Disabling sse4.2 will not disable popcnt if popcnt is explicitly enabled. llvm-svn: 190387
2013-09-10 14:55:47 +08:00
// SSE42POPCNT: #define __POPCNT__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-popcnt -msse4.2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SSE42NOPOPCNT %s
Separate popcnt and sse4.2 feature control somewhat to match gcc behavior. Enabling sse4.2 will implicitly enable popcnt unless popcnt is explicitly disabled. Disabling sse4.2 will not disable popcnt if popcnt is explicitly enabled. llvm-svn: 190387
2013-09-10 14:55:47 +08:00
// SSE42NOPOPCNT-NOT: #define __POPCNT__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mpopcnt -mno-sse4.2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOSSE42POPCNT %s
Separate popcnt and sse4.2 feature control somewhat to match gcc behavior. Enabling sse4.2 will implicitly enable popcnt unless popcnt is explicitly disabled. Disabling sse4.2 will not disable popcnt if popcnt is explicitly enabled. llvm-svn: 190387
2013-09-10 14:55:47 +08:00
// NOSSE42POPCNT: #define __POPCNT__ 1
Fix a bug where -msse followed by -mno-sse would leave MMX enabled. llvm-svn: 190496
2013-09-11 14:48:53 +08:00
[X86] Explicitly add popcnt feature to Intel CPUs with SSE4.2 in the frontend. Previously we inferred it if sse4.2 ended up being enabled after all feature processing. But writing -march=nehalem -mno-sse4.2 should have popcnt enabled.
2020-06-29 02:06:40 +08:00
// RUN: %clang -target i386-unknown-unknown -march=nehalem -mno-sse4.2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=CPUPOPCNT %s
// RUN: %clang -target i386-unknown-unknown -march=silvermont -mno-sse4.2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=CPUPOPCNT %s
// RUN: %clang -target i386-unknown-unknown -march=knl -mno-sse4.2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=CPUPOPCNT %s
// CPUPOPCNT: #define __POPCNT__ 1
[X86] Add 'mmx' to all CPUs that have a version of 'sse' and weren't already enabling '3dnow' All SSE capable CPUs have MMX. 3dnow implicitly enables MMX. We have code that detects if sse is enabled and implicitly enables MMX unless -mno-mmx is passed. So in most cases we were already enabling MMX if march passed a CPU that supported SSE. The exception to this is if you pass -march for a cpu supports SSE and also pass -mno-sse. We should still enable MMX since its part of the CPU capability.
2019-11-07 01:58:51 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentium -msse -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SSEMMX %s
Fix a bug where -msse followed by -mno-sse would leave MMX enabled. llvm-svn: 190496
2013-09-11 14:48:53 +08:00
// SSEMMX: #define __MMX__ 1
[X86] Add 'mmx' to all CPUs that have a version of 'sse' and weren't already enabling '3dnow' All SSE capable CPUs have MMX. 3dnow implicitly enables MMX. We have code that detects if sse is enabled and implicitly enables MMX unless -mno-mmx is passed. So in most cases we were already enabling MMX if march passed a CPU that supported SSE. The exception to this is if you pass -march for a cpu supports SSE and also pass -mno-sse. We should still enable MMX since its part of the CPU capability.
2019-11-07 01:58:51 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentium -msse -mno-sse -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SSENOSSEMMX %s
Fix a bug where -msse followed by -mno-sse would leave MMX enabled. llvm-svn: 190496
2013-09-11 14:48:53 +08:00
// SSENOSSEMMX-NOT: #define __MMX__ 1
[X86] Add 'mmx' to all CPUs that have a version of 'sse' and weren't already enabling '3dnow' All SSE capable CPUs have MMX. 3dnow implicitly enables MMX. We have code that detects if sse is enabled and implicitly enables MMX unless -mno-mmx is passed. So in most cases we were already enabling MMX if march passed a CPU that supported SSE. The exception to this is if you pass -march for a cpu supports SSE and also pass -mno-sse. We should still enable MMX since its part of the CPU capability.
2019-11-07 01:58:51 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentium -msse -mno-mmx -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SSENOMMX %s
Fix a bug where -msse followed by -mno-sse would leave MMX enabled. llvm-svn: 190496
2013-09-11 14:48:53 +08:00
// SSENOMMX-NOT: #define __MMX__ 1
Make F16C feature imply AVX. Matches GCC behavior. llvm-svn: 190776
2013-09-16 12:54:13 +08:00
[X86] Add 'mmx' to all CPUs that have a version of 'sse' and weren't already enabling '3dnow' All SSE capable CPUs have MMX. 3dnow implicitly enables MMX. We have code that detects if sse is enabled and implicitly enables MMX unless -mno-mmx is passed. So in most cases we were already enabling MMX if march passed a CPU that supported SSE. The exception to this is if you pass -march for a cpu supports SSE and also pass -mno-sse. We should still enable MMX since its part of the CPU capability.
2019-11-07 01:58:51 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentium3 -mno-sse -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MARCHMMXNOSSE %s
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-sse -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MARCHMMXNOSSE %s
// RUN: %clang -target i386-unknown-unknown -march=knl -mno-sse -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MARCHMMXNOSSE %s
// RUN: %clang -target i386-unknown-unknown -march=btver1 -mno-sse -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MARCHMMXNOSSE %s
// RUN: %clang -target i386-unknown-unknown -march=znver1 -mno-sse -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MARCHMMXNOSSE %s
// MARCHMMXNOSSE: #define __MMX__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mf16c -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=F16C %s
Make F16C feature imply AVX. Matches GCC behavior. llvm-svn: 190776
2013-09-16 12:54:13 +08:00
// F16C: #define __AVX__ 1
// F16C: #define __F16C__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mf16c -mno-avx -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=F16CNOAVX %s
Make F16C feature imply AVX. Matches GCC behavior. llvm-svn: 190776
2013-09-16 12:54:13 +08:00
// F16CNOAVX-NOT: #define __AVX__ 1
// F16CNOAVX-NOT: #define __F16C__ 1
Disabling sse2 should disable aes and pclmul support. llvm-svn: 190977
2013-09-19 08:01:05 +08:00
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mpclmul -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=PCLMUL %s
Disabling sse2 should disable aes and pclmul support. llvm-svn: 190977
2013-09-19 08:01:05 +08:00
// PCLMUL: #define __PCLMUL__ 1
// PCLMUL: #define __SSE2__ 1
// PCLMUL-NOT: #define __SSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mpclmul -mno-sse2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=PCLMULNOSSE2 %s
Disabling sse2 should disable aes and pclmul support. llvm-svn: 190977
2013-09-19 08:01:05 +08:00
// PCLMULNOSSE2-NOT: #define __PCLMUL__ 1
// PCLMULNOSSE2-NOT: #define __SSE2__ 1
// PCLMULNOSSE2-NOT: #define __SSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -maes -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AES %s
Disabling sse2 should disable aes and pclmul support. llvm-svn: 190977
2013-09-19 08:01:05 +08:00
// AES: #define __AES__ 1
// AES: #define __SSE2__ 1
// AES-NOT: #define __SSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -maes -mno-sse2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AESNOSSE2 %s
Disabling sse2 should disable aes and pclmul support. llvm-svn: 190977
2013-09-19 08:01:05 +08:00
// AESNOSSE2-NOT: #define __AES__ 1
// AESNOSSE2-NOT: #define __SSE2__ 1
// AESNOSSE2-NOT: #define __SSE3__ 1
Add C intrinsics for Intel SHA Extensions Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is enabled. SHA implies SSE2, which is needed for the __m128i type. Also add the -msha/-mno-sha option. llvm-svn: 190999
2013-09-19 21:22:04 +08:00
[X86][LWP] Add __LWP__ macro tests Missed in rL302418 Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302445
2017-05-09 01:25:48 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mlwp -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=LWP %s
// LWP: #define __LWP__ 1
// RUN: %clang -target i386-unknown-unknown -march=bdver1 -mno-lwp -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOLWP %s
// NOLWP-NOT: #define __LWP__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -msha -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SHA %s
Add C intrinsics for Intel SHA Extensions Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is enabled. SHA implies SSE2, which is needed for the __m128i type. Also add the -msha/-mno-sha option. llvm-svn: 190999
2013-09-19 21:22:04 +08:00
// SHA: #define __SHA__ 1
// SHA: #define __SSE2__ 1
// SHA-NOT: #define __SSE3__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -msha -mno-sha -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SHANOSHA %s
Add C intrinsics for Intel SHA Extensions Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is enabled. SHA implies SSE2, which is needed for the __m128i type. Also add the -msha/-mno-sha option. llvm-svn: 190999
2013-09-19 21:22:04 +08:00
// SHANOSHA-NOT: #define __SHA__ 1
// SHANOSHA-NOT: #define __SSE2__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -msha -mno-sse2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SHANOSSE2 %s
Add C intrinsics for Intel SHA Extensions Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is enabled. SHA implies SSE2, which is needed for the __m128i type. Also add the -msha/-mno-sha option. llvm-svn: 190999
2013-09-19 21:22:04 +08:00
Fix broken RUN lines llvm-svn: 201475
2014-02-16 15:28:32 +08:00
// SHANOSSE2-NOT: #define __SHA__ 1
// SHANOSSE2-NOT: #define __SSE2__ 1
// SHANOSSE2-NOT: #define __SSE3__ 1
Adding -mtbm and -mno-tbm command line options to the clang front end for the x86 TBM instruction set. Also adding a __TBM__ macro if the TBM feature is enabled. Otherwise there should be no functionality change to existing features. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1693 llvm-svn: 191326
2013-09-25 03:00:58 +08:00
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mtbm -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=TBM %s
Adding -mtbm and -mno-tbm command line options to the clang front end for the x86 TBM instruction set. Also adding a __TBM__ macro if the TBM feature is enabled. Otherwise there should be no functionality change to existing features. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1693 llvm-svn: 191326
2013-09-25 03:00:58 +08:00
// TBM: #define __TBM__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=bdver2 -mno-tbm -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOTBM %s
Adding -mtbm and -mno-tbm command line options to the clang front end for the x86 TBM instruction set. Also adding a __TBM__ macro if the TBM feature is enabled. Otherwise there should be no functionality change to existing features. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1693 llvm-svn: 191326
2013-09-25 03:00:58 +08:00
// NOTBM-NOT: #define __TBM__ 1
Add support for -mcx16, and predefine __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 when it is enabled. Also enable it on the same architectures that GCC does. llvm-svn: 192045
2013-10-06 04:14:27 +08:00
[X86] Only define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 in 64-bit mode. Summary: This define should correspond to CMPXCHG16B being available which requires 64-bit mode. I checked and gcc also seems to only define this in 64-bit mode. Reviewers: RKSimon, spatel, efriedma, jyknight, jfb Reviewed By: jfb Subscribers: jfb, cfe-commits, llvm-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59287 llvm-svn: 356118
2019-03-14 13:45:42 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16-32 %s
Add support for -mcx16, and predefine __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 when it is enabled. Also enable it on the same architectures that GCC does. llvm-svn: 192045
2013-10-06 04:14:27 +08:00
[X86] Only define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 in 64-bit mode. Summary: This define should correspond to CMPXCHG16B being available which requires 64-bit mode. I checked and gcc also seems to only define this in 64-bit mode. Reviewers: RKSimon, spatel, efriedma, jyknight, jfb Reviewed By: jfb Subscribers: jfb, cfe-commits, llvm-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59287 llvm-svn: 356118
2019-03-14 13:45:42 +08:00
// MCX16-32-NOT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16-64 %s
// MCX16-64: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=PRFCHW %s
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// PRFCHW: #define __PRFCHW__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=btver2 -mno-prfchw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOPRFCHW %s
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// NOPRFCHW-NOT: #define __PRFCHW__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -m3dnow -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=3DNOWPRFCHW %s
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
[X86] Don't imply -mprfchw when -m3dnow is specified. Enable prefetchw in the backend with 3dnow feature. The PREFETCHW instruction was originally part of the 3DNow. But it was given its own CPUID bit on later CPUs just before 3DNow was deprecated. We were setting the -mprfchw flag if -m3dnow was passed or the CPU supported 3dnow unless -mno-prfchw was passed. But -march=native on a CPU without the PRFCHW CPUID bit set will pass -mno-prfchw. So -march=k8 will behave differently than -march=native on a K8 for example. So remove this implicit setting from the frontend and instead enable the backend to use PREFETCHW if 3dnow OR prfchw is enabled. Also enable PRFCHW flag on amdfam10/barcelona which seems to be where this CPUID bit was introduced. That CPU also supported 3dnow.
2020-06-26 02:45:09 +08:00
// 3DNOWPRFCHW: #define __3dNOW__ 1
// 3DNOWPRFCHW-NOT: #define __PRFCHW__ 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-prfchw -m3dnow -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=3DNOWNOPRFCHW %s
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
[X86] Don't imply -mprfchw when -m3dnow is specified. Enable prefetchw in the backend with 3dnow feature. The PREFETCHW instruction was originally part of the 3DNow. But it was given its own CPUID bit on later CPUs just before 3DNow was deprecated. We were setting the -mprfchw flag if -m3dnow was passed or the CPU supported 3dnow unless -mno-prfchw was passed. But -march=native on a CPU without the PRFCHW CPUID bit set will pass -mno-prfchw. So -march=k8 will behave differently than -march=native on a K8 for example. So remove this implicit setting from the frontend and instead enable the backend to use PREFETCHW if 3dnow OR prfchw is enabled. Also enable PRFCHW flag on amdfam10/barcelona which seems to be where this CPUID bit was introduced. That CPU also supported 3dnow.
2020-06-26 02:45:09 +08:00
// 3DNOWNOPRFCHW: #define __3dNOW__ 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// 3DNOWNOPRFCHW-NOT: #define __PRFCHW__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -mno-3dnow -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NO3DNOWPRFCHW %s
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// NO3DNOWPRFCHW: #define __PRFCHW__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -madx -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=ADX %s
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// ADX: #define __ADX__ 1
[X86] Define __IBT__ when -mibt is specified. llvm-svn: 323543
2018-01-27 02:31:14 +08:00
// RUN: %clang -target i386-unknown-unknown -mshstk -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SHSTK %s
Control-Flow Enforcement Technology - Shadow Stack and Indirect Branch Tracking support (Clang side) Shadow stack solution introduces a new stack for return addresses only. The stack has a Shadow Stack Pointer (SSP) that points to the last address to which we expect to return. If we return to a different address an exception is triggered. This patch includes shadow stack intrinsics as well as the corresponding CET header. It includes CET clang flags for shadow stack and Indirect Branch Tracking. For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40224 Change-Id: I79ad0925a028bbc94c8ecad75f6daa2f214171f1 llvm-svn: 318995
2017-11-26 20:34:54 +08:00
[X86] Define __IBT__ when -mibt is specified. llvm-svn: 323543
2018-01-27 02:31:14 +08:00
// SHSTK: #define __SHSTK__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mrdseed -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=RDSEED %s
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// RDSEED: #define __RDSEED__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mxsave -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=XSAVE %s
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// XSAVE: #define __XSAVE__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mxsaveopt -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=XSAVEOPT %s
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// XSAVEOPT: #define __XSAVEOPT__ 1
// XSAVEOPT: #define __XSAVE__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mxsavec -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=XSAVEC %s
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// XSAVEC: #define __XSAVEC__ 1
// XSAVEC: #define __XSAVE__ 1
Clean up a couple more preprocessor tests to use match-full-lines. llvm-svn: 265187
2016-04-02 05:33:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mxsaves -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=XSAVES %s
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// XSAVES: #define __XSAVES__ 1
// XSAVES: #define __XSAVE__ 1
[X86] Make XSAVEC/XSAVEOPT/XSAVES properly depend on XSAVE in both the frontend and the backend. These features implicitly enabled XSAVE in the frontend, but not the backend. Disabling XSAVE in the frontend disabled XSAVEOPT, but not the other 2. Nothing happened in the backend.
2020-06-26 15:14:58 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mxsaveopt -mxsavec -mxsaves -mno-xsave -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOXSAVE %s
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
[X86] Make XSAVEC/XSAVEOPT/XSAVES properly depend on XSAVE in both the frontend and the backend. These features implicitly enabled XSAVE in the frontend, but not the backend. Disabling XSAVE in the frontend disabled XSAVEOPT, but not the other 2. Nothing happened in the backend.
2020-06-26 15:14:58 +08:00
// NOXSAVE-NOT: #define __XSAVEC__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// NOXSAVE-NOT: #define __XSAVEOPT__ 1
[X86] Make XSAVEC/XSAVEOPT/XSAVES properly depend on XSAVE in both the frontend and the backend. These features implicitly enabled XSAVE in the frontend, but not the backend. Disabling XSAVE in the frontend disabled XSAVEOPT, but not the other 2. Nothing happened in the backend.
2020-06-26 15:14:58 +08:00
// NOXSAVE-NOT: #define __XSAVES__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// NOXSAVE-NOT: #define __XSAVE__ 1
[X86] Add -mclflushopt/-mno-clflushopt command line support and __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
2017-02-08 14:48:58 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mclflushopt -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=CLFLUSHOPT %s
// CLFLUSHOPT: #define __CLFLUSHOPT__ 1
[x86][icelake][vaes] added vaes feature recognition added intrinsics support for vaes instructions, matching a similar work on the backend (D40078) _mm256_aesenc_epi128 _mm512_aesenc_epi128 _mm256_aesenclast_epi128 _mm512_aesenclast_epi128 _mm256_aesdec_epi128 _mm512_aesdec_epi128 _mm256_aesdeclast_epi128 _mm512_aesdeclast_epi128 llvm-svn: 321474
2017-12-27 16:16:54 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mvaes -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=VAES %s
// VAES: #define __AES__ 1
// VAES: #define __VAES__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mvaes -mno-aes -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=VAESNOAES %s
// VAESNOAES-NOT: #define __AES__ 1
// VAESNOAES-NOT: #define __VAES__ 1
[x86][icelake][gfni] added gfni feature recognition added intrinsics support for gfni instructions _mm_gf2p8affineinv_epi64_epi8 _mm_mask_gf2p8affineinv_epi64_epi8 _mm_maskz_gf2p8affineinv_epi64_epi8 _mm256_gf2p8affineinv_epi64_epi8 _mm256_mask_gf2p8affineinv_epi64_epi8 _mm256_maskz_gf2p8affineinv_epi64_epi8 _mm512_gf2p8affineinv_epi64_epi8 _mm512_mask_gf2p8affineinv_epi64_epi8 _mm512_maskz_gf2p8affineinv_epi64_epi8 _mm_gf2p8affine_epi64_epi8 _mm_mask_gf2p8affine_epi64_epi8 _mm_maskz_gf2p8affine_epi64_epi8 _mm256_gf2p8affine_epi64_epi8 _mm256_mask_gf2p8affine_epi64_epi8 _mm256_maskz_gf2p8affine_epi64_epi8 _mm512_gf2p8affine_epi64_epi8 _mm512_mask_gf2p8affine_epi64_epi8 _mm512_maskz_gf2p8affine_epi64_epi8 _mm_gf2p8mul_epi8 _mm_mask_gf2p8mul_epi8 _mm_maskz_gf2p8mul_epi8 _mm256_gf2p8mul_epi8 _mm256_mask_gf2p8mul_epi8 _mm256_maskz_gf2p8mul_epi8 _mm512_gf2p8mul_epi8 _mm512_mask_gf2p8mul_epi8 _mm512_maskz_gf2p8mul_epi8 matching a similar work on the backend (D40373) Differential Revision: https://reviews.llvm.org/D41582 llvm-svn: 321477
2017-12-27 16:37:47 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mgfni -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=GFNI %s
// GFNI: #define __GFNI__ 1
// GFNI: #define __SSE2__ 1
[x86][icelake][vpclmulqdq] added vpclmulqdq feature recognition added intrinsics support for vpclmulqdq instructions _mm256_clmulepi64_epi128 _mm512_clmulepi64_epi128 matching a similar work on the backend (D40101) Differential Revision: https://reviews.llvm.org/D41573 llvm-svn: 321480
2017-12-27 17:00:31 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mvpclmulqdq -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=VPCLMULQDQ %s
// VPCLMULQDQ: #define __PCLMUL__ 1
// VPCLMULQDQ: #define __VPCLMULQDQ__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mvpclmulqdq -mno-pclmul -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=VPCLMULQDQNOPCLMUL %s
// VPCLMULQDQNOPCLMUL-NOT: #define __PCLMUL__ 1
// VPCLMULQDQNOPCLMUL-NOT: #define __VPCLMULQDQ__ 1
[X86] Add rdpid command line option and intrinsics. Summary: This patch adds -mrdpid/-mno-rdpid and the rdpid intrinsic. The corresponding LLVM commit has already been made. Reviewers: RKSimon, spatel, zvi, AndreiGrischenko Reviewed By: RKSimon Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D42272 llvm-svn: 323047
2018-01-21 02:36:52 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mrdpid -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=RDPID %s
// RDPID: #define __RDPID__ 1
Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake Summary: 1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake; 2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision. For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference Patch by LiuTianle Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon Reviewed By: craig.topper Subscribers: mgorny, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D60552 llvm-svn: 360018
2019-05-06 16:25:11 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bf16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BF16 %s
// AVX512BF16: #define __AVX512BF16__ 1
// AVX512BF16: #define __AVX512BW__ 1
[X86] Stop implicitly enabling avx512vl when avx512bf16 is enabled. Previously we were doing this so that the 256 bit selectw builtin could be used in the implementation of the 512->256 bit conversion intrinsic. After this commit we now use a masked convert builtin that will emit the intrinsic call and the 256-bit select from custom code in CGBuiltin. Then the header only needs to call that one intrinsic. llvm-svn: 360924
2019-05-17 02:28:17 +08:00
// AVX512BF16-NOT: #define __AVX512VL__ 1
Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake Summary: 1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake; 2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision. For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference Patch by LiuTianle Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon Reviewed By: craig.topper Subscribers: mgorny, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D60552 llvm-svn: 360018
2019-05-06 16:25:11 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bf16 -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BF16_NOAVX512BW %s
// AVX512BF16_NOAVX512BW-NOT: #define __AVX512BF16__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bf16 -mno-avx512vl -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BF16_NOAVX512VL %s
[X86] Stop implicitly enabling avx512vl when avx512bf16 is enabled. Previously we were doing this so that the 256 bit selectw builtin could be used in the implementation of the 512->256 bit conversion intrinsic. After this commit we now use a masked convert builtin that will emit the intrinsic call and the 256-bit select from custom code in CGBuiltin. Then the header only needs to call that one intrinsic. llvm-svn: 360924
2019-05-17 02:28:17 +08:00
// AVX512BF16_NOAVX512VL: #define __AVX512BF16__ 1
Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake Summary: 1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake; 2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision. For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference Patch by LiuTianle Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon Reviewed By: craig.topper Subscribers: mgorny, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D60552 llvm-svn: 360018
2019-05-06 16:25:11 +08:00
[X86] Add VP2INTERSECT instructions Support intel AVX512 VP2INTERSECT instructions in clang Patch by Xiang Zhang (xiangzhangllvm) Differential Revision: https://reviews.llvm.org/D62367 llvm-svn: 362196
2019-05-31 14:09:35 +08:00
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -x c -E -dM -o - %s | FileCheck -check-prefix=VP2INTERSECT %s
// VP2INTERSECT: #define __AVX512F__ 1
// VP2INTERSECT: #define __AVX512VP2INTERSECT__ 1
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512vp2intersect -x c -E -dM -o - %s | FileCheck -check-prefix=NOVP2INTERSECT %s
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -mno-avx512f -x c -E -dM -o - %s | FileCheck -check-prefix=NOVP2INTERSECT %s
// NOVP2INTERSECT-NOT: #define __AVX512VP2INTERSECT__ 1
[X86] Support Intel Key Locker Key Locker provides a mechanism to encrypt and decrypt data with an AES key without having access to the raw key value by converting AES keys into “handles”. These handles can be used to perform the same encryption and decryption operations as the original AES keys, but they only work on the current system and only until they are revoked. If software revokes Key Locker handles (e.g., on a reboot), then any previous handles can no longer be used. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D88398
2020-09-30 18:01:15 +08:00
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mkl -x c -E -dM -o - %s | FileCheck -check-prefix=KEYLOCKER %s
// KEYLOCKER: #define __KL__ 1
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-kl -x c -E -dM -o - %s | FileCheck -check-prefix=NOKEYLOCKER %s
// NOKEYLOCKER-NOT: #define __KL__ 1
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mwidekl -x c -E -dM -o - %s | FileCheck -check-prefix=KEYLOCKERW %s
// KEYLOCKERW: #define __KL__ 1
// KEYLOCKERW: #define __WIDEKL__ 1
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-widekl -x c -E -dM -o - %s | FileCheck -check-prefix=NOKEYLOCKERW %s
// NOKEYLOCKERW-NOT: #define __KL__ 1
// NOKEYLOCKERW-NOT: #define __WIDEKL__ 1
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mwidekl -mno-kl -x c -E -dM -o - %s | FileCheck -check-prefix=NOKEYLOCKERW2 %s
// NOKEYLOCKERW2-NOT: #define __KL__ 1
// NOKEYLOCKERW2-NOT: #define __WIDEKL__ 1
[X86] Add ENQCMD instructions For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference. Patch by Tianqing Wang (tianqing) Differential Revision: https://reviews.llvm.org/D62282 llvm-svn: 362685
2019-06-06 16:28:42 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -menqcmd -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=ENQCMD %s
// ENQCMD: #define __ENQCMD__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-enqcmd -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOENQCMD %s
// NOENQCMD-NOT: #define __ENQCMD__ 1
[X86] Add SERIALIZE instruction. Summary: For more details about this instruction, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference Reviewers: craig.topper, RKSimon, LuoYuanke Reviewed By: craig.topper Subscribers: mgorny, hiraditya, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D77193
2020-04-02 16:15:34 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mserialize -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SERIALIZE %s
// SERIALIZE: #define __SERIALIZE__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-serialize -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOSERIALIZE %s
// NOSERIALIZE-NOT: #define __SERIALIZE__ 1
[X86] Add TSXLDTRK instructions. Summary: For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference Reviewers: craig.topper, RKSimon, LuoYuanke Reviewed By: craig.topper Subscribers: mgorny, hiraditya, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D77205
2020-04-09 13:15:42 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mtsxldtrk -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=TSXLDTRK %s
// TSXLDTRK: #define __TSXLDTRK__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-tsxldtrk -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOTSXLDTRK %s
// NOTSXLDTRK-NOT: #define __TSXLDTRK__ 1
[X86] Add HRESET instruction. For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89102
2020-10-13 08:42:46 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mhreset -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=HRESET %s
// HRESET: #define __HRESET__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-hreset -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOHRESET %s
// NOHRESET-NOT: #define __HRESET__ 1
[X86] Add User Interrupts(UINTR) instructions For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89301
2020-10-22 16:46:07 +08:00
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -muintr -x c -E -dM -o - %s | FileCheck -check-prefix=UINTR %s
// UINTR: #define __UINTR__ 1
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-uintr -x c -E -dM -o - %s | FileCheck -check-prefix=NOUINTR %s
// NOUINTR-NOT: #define __UINTR__ 1
[X86] Support Intel avxvnni This patch mainly made the following changes: 1. Support AVX-VNNI instructions; 2. Introduce ExplicitVEXPrefix flag so that vpdpbusd/vpdpbusds/vpdpbusds/vpdpbusds instructions only use vex-encoding when user explicity add {vex} prefix. Differential Revision: https://reviews.llvm.org/D89105
2020-10-30 12:58:05 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavxvnni -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVXVNNI %s
// AVXVNNI: #define __AVX2__ 1
// AVXVNNI: #define __AVXVNNI__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-avxvnni -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOAVXVNNI %s
// NOAVXVNNI-NOT: #define __AVXVNNI__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mavxvnni -mno-avx2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVXVNNINOAVX2 %s
// AVXVNNINOAVX2-NOT: #define __AVX2__ 1
// AVXVNNINOAVX2-NOT: #define __AVXVNNI__ 1