forked from OSchip/llvm-project
655 lines
22 KiB
C++
655 lines
22 KiB
C++
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//===----- ScheduleDAGFast.cpp - Fast poor list scheduler -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a fast scheduler.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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STATISTIC(NumUnfolds, "Number of nodes unfolded");
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STATISTIC(NumDups, "Number of duplicated nodes");
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STATISTIC(NumCCCopies, "Number of cross class copies");
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static RegisterScheduler
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fastDAGScheduler("fast", " Fast suboptimal list scheduling",
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createFastDAGScheduler);
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namespace {
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/// FastPriorityQueue - A degenerate priority queue that considers
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/// all nodes to have the same priority.
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///
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struct VISIBILITY_HIDDEN FastPriorityQueue {
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std::vector<SUnit *> Queue;
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bool empty() const { return Queue.empty(); }
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void push(SUnit *U) {
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Queue.push_back(U);
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}
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SUnit *pop() {
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if (empty()) return NULL;
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SUnit *V = Queue.back();
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Queue.pop_back();
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return V;
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}
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};
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//===----------------------------------------------------------------------===//
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/// ScheduleDAGFast - The actual "fast" list scheduler implementation.
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///
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class VISIBILITY_HIDDEN ScheduleDAGFast : public ScheduleDAG {
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private:
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/// AvailableQueue - The priority queue to use for the available SUnits.
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FastPriorityQueue AvailableQueue;
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/// LiveRegs / LiveRegDefs - A set of physical registers and their definition
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/// that are "live". These nodes must be scheduled before any other nodes that
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/// modifies the registers can be scheduled.
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SmallSet<unsigned, 4> LiveRegs;
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std::vector<SUnit*> LiveRegDefs;
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std::vector<unsigned> LiveRegCycles;
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public:
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ScheduleDAGFast(SelectionDAG &dag, MachineBasicBlock *bb,
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const TargetMachine &tm)
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: ScheduleDAG(dag, bb, tm) {}
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void Schedule();
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/// AddPred - This adds the specified node X as a predecessor of
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/// the current node Y if not already.
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/// This returns true if this is a new predecessor.
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bool AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial,
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unsigned PhyReg = 0, int Cost = 1);
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/// RemovePred - This removes the specified node N from the predecessors of
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/// the current node M.
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bool RemovePred(SUnit *M, SUnit *N, bool isCtrl, bool isSpecial);
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private:
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void ReleasePred(SUnit*, bool, unsigned);
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void ScheduleNodeBottomUp(SUnit*, unsigned);
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SUnit *CopyAndMoveSuccessors(SUnit*);
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void InsertCCCopiesAndMoveSuccs(SUnit*, unsigned,
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const TargetRegisterClass*,
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const TargetRegisterClass*,
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SmallVector<SUnit*, 2>&);
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bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&);
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void ListScheduleBottomUp();
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/// CreateNewSUnit - Creates a new SUnit and returns a pointer to it.
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SUnit *CreateNewSUnit(SDNode *N) {
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SUnit *NewNode = NewSUnit(N);
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return NewNode;
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}
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/// CreateClone - Creates a new SUnit from an existing one.
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SUnit *CreateClone(SUnit *N) {
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SUnit *NewNode = Clone(N);
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return NewNode;
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}
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};
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} // end anonymous namespace
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/// Schedule - Schedule the DAG using list scheduling.
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void ScheduleDAGFast::Schedule() {
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DOUT << "********** List Scheduling **********\n";
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LiveRegDefs.resize(TRI->getNumRegs(), NULL);
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LiveRegCycles.resize(TRI->getNumRegs(), 0);
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// Build scheduling units.
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BuildSchedUnits();
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(&DAG));
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// Execute the actual scheduling loop.
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ListScheduleBottomUp();
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}
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//===----------------------------------------------------------------------===//
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// Bottom-Up Scheduling
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//===----------------------------------------------------------------------===//
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
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/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
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void ScheduleDAGFast::ReleasePred(SUnit *PredSU, bool isChain,
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unsigned CurCycle) {
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// FIXME: the distance between two nodes is not always == the predecessor's
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// latency. For example, the reader can very well read the register written
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// by the predecessor later than the issue cycle. It also depends on the
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// interrupt model (drain vs. freeze).
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PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
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--PredSU->NumSuccsLeft;
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#ifndef NDEBUG
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if (PredSU->NumSuccsLeft < 0) {
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cerr << "*** List scheduling failed! ***\n";
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PredSU->dump(&DAG);
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cerr << " has been released too many times!\n";
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assert(0);
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}
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#endif
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if (PredSU->NumSuccsLeft == 0) {
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PredSU->isAvailable = true;
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AvailableQueue.push(PredSU);
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}
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}
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/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
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/// count of its predecessors. If a predecessor pending count is zero, add it to
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/// the Available queue.
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void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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DOUT << "*** Scheduling [" << CurCycle << "]: ";
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DEBUG(SU->dump(&DAG));
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SU->Cycle = CurCycle;
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// Bottom up: release predecessors
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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ReleasePred(I->Dep, I->isCtrl, CurCycle);
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if (I->Cost < 0) {
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// This is a physical register dependency and it's impossible or
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// expensive to copy the register. Make sure nothing that can
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// clobber the register is scheduled between the predecessor and
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// this node.
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if (LiveRegs.insert(I->Reg)) {
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LiveRegDefs[I->Reg] = I->Dep;
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LiveRegCycles[I->Reg] = CurCycle;
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}
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}
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}
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// Release all the implicit physical register defs that are live.
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->Cost < 0) {
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if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
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LiveRegs.erase(I->Reg);
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assert(LiveRegDefs[I->Reg] == SU &&
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"Physical register dependency violated?");
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LiveRegDefs[I->Reg] = NULL;
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LiveRegCycles[I->Reg] = 0;
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}
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}
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}
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SU->isScheduled = true;
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}
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/// AddPred - adds an edge from SUnit X to SUnit Y.
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bool ScheduleDAGFast::AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial,
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unsigned PhyReg, int Cost) {
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return Y->addPred(X, isCtrl, isSpecial, PhyReg, Cost);
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}
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/// RemovePred - This removes the specified node N from the predecessors of
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/// the current node M.
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bool ScheduleDAGFast::RemovePred(SUnit *M, SUnit *N,
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bool isCtrl, bool isSpecial) {
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return M->removePred(N, isCtrl, isSpecial);
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}
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/// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
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/// successors to the newly created node.
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SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
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if (SU->FlaggedNodes.size())
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return NULL;
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SDNode *N = SU->Node;
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if (!N)
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return NULL;
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SUnit *NewSU;
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bool TryUnfold = false;
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for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
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MVT VT = N->getValueType(i);
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if (VT == MVT::Flag)
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return NULL;
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else if (VT == MVT::Other)
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TryUnfold = true;
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}
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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const SDValue &Op = N->getOperand(i);
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MVT VT = Op.getNode()->getValueType(Op.getResNo());
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if (VT == MVT::Flag)
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return NULL;
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}
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if (TryUnfold) {
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SmallVector<SDNode*, 2> NewNodes;
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if (!TII->unfoldMemoryOperand(DAG, N, NewNodes))
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return NULL;
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DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
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assert(NewNodes.size() == 2 && "Expected a load folding node!");
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N = NewNodes[1];
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SDNode *LoadNode = NewNodes[0];
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unsigned NumVals = N->getNumValues();
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unsigned OldNumVals = SU->Node->getNumValues();
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for (unsigned i = 0; i != NumVals; ++i)
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DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i));
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DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1),
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SDValue(LoadNode, 1));
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SUnit *NewSU = CreateNewSUnit(N);
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NewSU->NodeNum);
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const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
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for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
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if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
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NewSU->isTwoAddress = true;
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break;
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}
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}
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if (TID.isCommutable())
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NewSU->isCommutable = true;
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// FIXME: Calculate height / depth and propagate the changes?
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NewSU->Depth = SU->Depth;
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NewSU->Height = SU->Height;
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ComputeLatency(NewSU);
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// LoadNode may already exist. This can happen when there is another
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// load from the same location and producing the same type of value
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// but it has different alignment or volatileness.
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bool isNewLoad = true;
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SUnit *LoadSU;
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if (LoadNode->getNodeId() != -1) {
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LoadSU = &SUnits[LoadNode->getNodeId()];
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isNewLoad = false;
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} else {
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LoadSU = CreateNewSUnit(LoadNode);
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LoadNode->setNodeId(LoadSU->NodeNum);
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LoadSU->Depth = SU->Depth;
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LoadSU->Height = SU->Height;
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ComputeLatency(LoadSU);
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}
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SUnit *ChainPred = NULL;
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SmallVector<SDep, 4> ChainSuccs;
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SmallVector<SDep, 4> LoadPreds;
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SmallVector<SDep, 4> NodePreds;
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SmallVector<SDep, 4> NodeSuccs;
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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if (I->isCtrl)
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ChainPred = I->Dep;
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else if (I->Dep->Node && I->Dep->Node->isOperandOf(LoadNode))
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LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
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else
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NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
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}
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isCtrl)
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ChainSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
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I->isCtrl, I->isSpecial));
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else
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NodeSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
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I->isCtrl, I->isSpecial));
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}
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if (ChainPred) {
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RemovePred(SU, ChainPred, true, false);
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if (isNewLoad)
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AddPred(LoadSU, ChainPred, true, false);
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}
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for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
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SDep *Pred = &LoadPreds[i];
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RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial);
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if (isNewLoad) {
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AddPred(LoadSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial,
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Pred->Reg, Pred->Cost);
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}
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}
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for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
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SDep *Pred = &NodePreds[i];
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RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial);
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AddPred(NewSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial,
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Pred->Reg, Pred->Cost);
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}
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for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
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SDep *Succ = &NodeSuccs[i];
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RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial);
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AddPred(Succ->Dep, NewSU, Succ->isCtrl, Succ->isSpecial,
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Succ->Reg, Succ->Cost);
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}
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for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
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SDep *Succ = &ChainSuccs[i];
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RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial);
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if (isNewLoad) {
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AddPred(Succ->Dep, LoadSU, Succ->isCtrl, Succ->isSpecial,
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Succ->Reg, Succ->Cost);
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}
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}
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if (isNewLoad) {
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AddPred(NewSU, LoadSU, false, false);
|
||
|
|
}
|
||
|
|
|
||
|
|
++NumUnfolds;
|
||
|
|
|
||
|
|
if (NewSU->NumSuccsLeft == 0) {
|
||
|
|
NewSU->isAvailable = true;
|
||
|
|
return NewSU;
|
||
|
|
}
|
||
|
|
SU = NewSU;
|
||
|
|
}
|
||
|
|
|
||
|
|
DOUT << "Duplicating SU # " << SU->NodeNum << "\n";
|
||
|
|
NewSU = CreateClone(SU);
|
||
|
|
|
||
|
|
// New SUnit has the exact same predecessors.
|
||
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
||
|
|
I != E; ++I)
|
||
|
|
if (!I->isSpecial) {
|
||
|
|
AddPred(NewSU, I->Dep, I->isCtrl, false, I->Reg, I->Cost);
|
||
|
|
NewSU->Depth = std::max(NewSU->Depth, I->Dep->Depth+1);
|
||
|
|
}
|
||
|
|
|
||
|
|
// Only copy scheduled successors. Cut them from old node's successor
|
||
|
|
// list and move them over.
|
||
|
|
SmallVector<std::pair<SUnit*, bool>, 4> DelDeps;
|
||
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
||
|
|
I != E; ++I) {
|
||
|
|
if (I->isSpecial)
|
||
|
|
continue;
|
||
|
|
if (I->Dep->isScheduled) {
|
||
|
|
NewSU->Height = std::max(NewSU->Height, I->Dep->Height+1);
|
||
|
|
AddPred(I->Dep, NewSU, I->isCtrl, false, I->Reg, I->Cost);
|
||
|
|
DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
|
||
|
|
SUnit *Succ = DelDeps[i].first;
|
||
|
|
bool isCtrl = DelDeps[i].second;
|
||
|
|
RemovePred(Succ, SU, isCtrl, false);
|
||
|
|
}
|
||
|
|
|
||
|
|
++NumDups;
|
||
|
|
return NewSU;
|
||
|
|
}
|
||
|
|
|
||
|
|
/// InsertCCCopiesAndMoveSuccs - Insert expensive cross register class copies
|
||
|
|
/// and move all scheduled successors of the given SUnit to the last copy.
|
||
|
|
void ScheduleDAGFast::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
|
||
|
|
const TargetRegisterClass *DestRC,
|
||
|
|
const TargetRegisterClass *SrcRC,
|
||
|
|
SmallVector<SUnit*, 2> &Copies) {
|
||
|
|
SUnit *CopyFromSU = CreateNewSUnit(NULL);
|
||
|
|
CopyFromSU->CopySrcRC = SrcRC;
|
||
|
|
CopyFromSU->CopyDstRC = DestRC;
|
||
|
|
|
||
|
|
SUnit *CopyToSU = CreateNewSUnit(NULL);
|
||
|
|
CopyToSU->CopySrcRC = DestRC;
|
||
|
|
CopyToSU->CopyDstRC = SrcRC;
|
||
|
|
|
||
|
|
// Only copy scheduled successors. Cut them from old node's successor
|
||
|
|
// list and move them over.
|
||
|
|
SmallVector<std::pair<SUnit*, bool>, 4> DelDeps;
|
||
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
||
|
|
I != E; ++I) {
|
||
|
|
if (I->isSpecial)
|
||
|
|
continue;
|
||
|
|
if (I->Dep->isScheduled) {
|
||
|
|
AddPred(I->Dep, CopyToSU, I->isCtrl, false, I->Reg, I->Cost);
|
||
|
|
DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
|
||
|
|
SUnit *Succ = DelDeps[i].first;
|
||
|
|
bool isCtrl = DelDeps[i].second;
|
||
|
|
RemovePred(Succ, SU, isCtrl, false);
|
||
|
|
}
|
||
|
|
|
||
|
|
AddPred(CopyFromSU, SU, false, false, Reg, -1);
|
||
|
|
AddPred(CopyToSU, CopyFromSU, false, false, Reg, 1);
|
||
|
|
|
||
|
|
Copies.push_back(CopyFromSU);
|
||
|
|
Copies.push_back(CopyToSU);
|
||
|
|
|
||
|
|
++NumCCCopies;
|
||
|
|
}
|
||
|
|
|
||
|
|
/// getPhysicalRegisterVT - Returns the ValueType of the physical register
|
||
|
|
/// definition of the specified node.
|
||
|
|
/// FIXME: Move to SelectionDAG?
|
||
|
|
static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
|
||
|
|
const TargetInstrInfo *TII) {
|
||
|
|
const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
|
||
|
|
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
|
||
|
|
unsigned NumRes = TID.getNumDefs();
|
||
|
|
for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
|
||
|
|
if (Reg == *ImpDef)
|
||
|
|
break;
|
||
|
|
++NumRes;
|
||
|
|
}
|
||
|
|
return N->getValueType(NumRes);
|
||
|
|
}
|
||
|
|
|
||
|
|
/// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
|
||
|
|
/// scheduling of the given node to satisfy live physical register dependencies.
|
||
|
|
/// If the specific node is the last one that's available to schedule, do
|
||
|
|
/// whatever is necessary (i.e. backtracking or cloning) to make it possible.
|
||
|
|
bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
|
||
|
|
SmallVector<unsigned, 4> &LRegs){
|
||
|
|
if (LiveRegs.empty())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
SmallSet<unsigned, 4> RegAdded;
|
||
|
|
// If this node would clobber any "live" register, then it's not ready.
|
||
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
||
|
|
I != E; ++I) {
|
||
|
|
if (I->Cost < 0) {
|
||
|
|
unsigned Reg = I->Reg;
|
||
|
|
if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
|
||
|
|
if (RegAdded.insert(Reg))
|
||
|
|
LRegs.push_back(Reg);
|
||
|
|
}
|
||
|
|
for (const unsigned *Alias = TRI->getAliasSet(Reg);
|
||
|
|
*Alias; ++Alias)
|
||
|
|
if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
|
||
|
|
if (RegAdded.insert(*Alias))
|
||
|
|
LRegs.push_back(*Alias);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) {
|
||
|
|
SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
|
||
|
|
if (!Node || !Node->isMachineOpcode())
|
||
|
|
continue;
|
||
|
|
const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode());
|
||
|
|
if (!TID.ImplicitDefs)
|
||
|
|
continue;
|
||
|
|
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
|
||
|
|
if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
|
||
|
|
if (RegAdded.insert(*Reg))
|
||
|
|
LRegs.push_back(*Reg);
|
||
|
|
}
|
||
|
|
for (const unsigned *Alias = TRI->getAliasSet(*Reg);
|
||
|
|
*Alias; ++Alias)
|
||
|
|
if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
|
||
|
|
if (RegAdded.insert(*Alias))
|
||
|
|
LRegs.push_back(*Alias);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return !LRegs.empty();
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
|
||
|
|
/// schedulers.
|
||
|
|
void ScheduleDAGFast::ListScheduleBottomUp() {
|
||
|
|
unsigned CurCycle = 0;
|
||
|
|
// Add root to Available queue.
|
||
|
|
if (!SUnits.empty()) {
|
||
|
|
SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()];
|
||
|
|
assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
|
||
|
|
RootSU->isAvailable = true;
|
||
|
|
AvailableQueue.push(RootSU);
|
||
|
|
}
|
||
|
|
|
||
|
|
// While Available queue is not empty, grab the node with the highest
|
||
|
|
// priority. If it is not ready put it back. Schedule the node.
|
||
|
|
SmallVector<SUnit*, 4> NotReady;
|
||
|
|
DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;
|
||
|
|
Sequence.reserve(SUnits.size());
|
||
|
|
while (!AvailableQueue.empty()) {
|
||
|
|
bool Delayed = false;
|
||
|
|
LRegsMap.clear();
|
||
|
|
SUnit *CurSU = AvailableQueue.pop();
|
||
|
|
while (CurSU) {
|
||
|
|
if (CurSU->CycleBound <= CurCycle) {
|
||
|
|
SmallVector<unsigned, 4> LRegs;
|
||
|
|
if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
|
||
|
|
break;
|
||
|
|
Delayed = true;
|
||
|
|
LRegsMap.insert(std::make_pair(CurSU, LRegs));
|
||
|
|
}
|
||
|
|
|
||
|
|
CurSU->isPending = true; // This SU is not in AvailableQueue right now.
|
||
|
|
NotReady.push_back(CurSU);
|
||
|
|
CurSU = AvailableQueue.pop();
|
||
|
|
}
|
||
|
|
|
||
|
|
// All candidates are delayed due to live physical reg dependencies.
|
||
|
|
// Try code duplication or inserting cross class copies
|
||
|
|
// to resolve it.
|
||
|
|
if (Delayed && !CurSU) {
|
||
|
|
if (!CurSU) {
|
||
|
|
// Try duplicating the nodes that produces these
|
||
|
|
// "expensive to copy" values to break the dependency. In case even
|
||
|
|
// that doesn't work, insert cross class copies.
|
||
|
|
SUnit *TrySU = NotReady[0];
|
||
|
|
SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
|
||
|
|
assert(LRegs.size() == 1 && "Can't handle this yet!");
|
||
|
|
unsigned Reg = LRegs[0];
|
||
|
|
SUnit *LRDef = LiveRegDefs[Reg];
|
||
|
|
SUnit *NewDef = CopyAndMoveSuccessors(LRDef);
|
||
|
|
if (!NewDef) {
|
||
|
|
// Issue expensive cross register class copies.
|
||
|
|
MVT VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
|
||
|
|
const TargetRegisterClass *RC =
|
||
|
|
TRI->getPhysicalRegisterRegClass(Reg, VT);
|
||
|
|
const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
|
||
|
|
if (!DestRC) {
|
||
|
|
assert(false && "Don't know how to copy this physical register!");
|
||
|
|
abort();
|
||
|
|
}
|
||
|
|
SmallVector<SUnit*, 2> Copies;
|
||
|
|
InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
|
||
|
|
DOUT << "Adding an edge from SU # " << TrySU->NodeNum
|
||
|
|
<< " to SU #" << Copies.front()->NodeNum << "\n";
|
||
|
|
AddPred(TrySU, Copies.front(), true, true);
|
||
|
|
NewDef = Copies.back();
|
||
|
|
}
|
||
|
|
|
||
|
|
DOUT << "Adding an edge from SU # " << NewDef->NodeNum
|
||
|
|
<< " to SU #" << TrySU->NodeNum << "\n";
|
||
|
|
LiveRegDefs[Reg] = NewDef;
|
||
|
|
AddPred(NewDef, TrySU, true, true);
|
||
|
|
TrySU->isAvailable = false;
|
||
|
|
CurSU = NewDef;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!CurSU) {
|
||
|
|
assert(false && "Unable to resolve live physical register dependencies!");
|
||
|
|
abort();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Add the nodes that aren't ready back onto the available list.
|
||
|
|
for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
|
||
|
|
NotReady[i]->isPending = false;
|
||
|
|
// May no longer be available due to backtracking.
|
||
|
|
if (NotReady[i]->isAvailable)
|
||
|
|
AvailableQueue.push(NotReady[i]);
|
||
|
|
}
|
||
|
|
NotReady.clear();
|
||
|
|
|
||
|
|
if (!CurSU)
|
||
|
|
Sequence.push_back(0);
|
||
|
|
else {
|
||
|
|
ScheduleNodeBottomUp(CurSU, CurCycle);
|
||
|
|
Sequence.push_back(CurSU);
|
||
|
|
}
|
||
|
|
++CurCycle;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Reverse the order if it is bottom up.
|
||
|
|
std::reverse(Sequence.begin(), Sequence.end());
|
||
|
|
|
||
|
|
|
||
|
|
#ifndef NDEBUG
|
||
|
|
// Verify that all SUnits were scheduled.
|
||
|
|
bool AnyNotSched = false;
|
||
|
|
unsigned DeadNodes = 0;
|
||
|
|
unsigned Noops = 0;
|
||
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
||
|
|
if (!SUnits[i].isScheduled) {
|
||
|
|
if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) {
|
||
|
|
++DeadNodes;
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
if (!AnyNotSched)
|
||
|
|
cerr << "*** List scheduling failed! ***\n";
|
||
|
|
SUnits[i].dump(&DAG);
|
||
|
|
cerr << "has not been scheduled!\n";
|
||
|
|
AnyNotSched = true;
|
||
|
|
}
|
||
|
|
if (SUnits[i].NumSuccsLeft != 0) {
|
||
|
|
if (!AnyNotSched)
|
||
|
|
cerr << "*** List scheduling failed! ***\n";
|
||
|
|
SUnits[i].dump(&DAG);
|
||
|
|
cerr << "has successors left!\n";
|
||
|
|
AnyNotSched = true;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
|
||
|
|
if (!Sequence[i])
|
||
|
|
++Noops;
|
||
|
|
assert(!AnyNotSched);
|
||
|
|
assert(Sequence.size() + DeadNodes - Noops == SUnits.size() &&
|
||
|
|
"The number of nodes scheduled doesn't match the expected number!");
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Public Constructor Functions
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS,
|
||
|
|
SelectionDAG *DAG,
|
||
|
|
MachineBasicBlock *BB, bool) {
|
||
|
|
return new ScheduleDAGFast(*DAG, BB, DAG->getTarget());
|
||
|
|
}
|