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llvm-project/lld/test/ELF/arm-thumb-undefined-weak.s

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[ELF] Move `// REQUIRES:` line to the top llvm-svn: 335676
2018-06-27 06:20:04 +08:00
// REQUIRES: arm
[LLD][ELF][ARM] Implement Thumb pc-relative relocations for adr and ldr MC will now output the R_ARM_THM_PC8, R_ARM_THM_PC12 and R_ARM_THM_PREL_11_0 relocations. These are short-ranged relocations that are used to implement the adr rd, literal and ldr rd, literal pseudo instructions. The instructions use a new RelExpr called R_ARM_PCA in order to calculate the required S + A - Pa expression, where Pa is AlignDown(P, 4) as the instructions add their immediate to AlignDown(PC, 4). We also do not want these relocations to generate or resolve against a PLT entry as the range of these relocations is so short they would never reach. The R_ARM_THM_PC8 has a special encoding convention for the relocation addend, the immediate field is unsigned, yet the addend must be -4 to account for the Thumb PC bias. The ABI (not the architecture) uses the convention that the 8-byte immediate of 0xff represents -4. Differential Revision: https://reviews.llvm.org/D75042
2020-02-24 03:46:46 +08:00
// RUN: llvm-mc --arm-add-build-attributes -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
[ARM][test] Improve tests Delete trailing 2>&1 that is not piped to another command. Add --no-show-raw-insn to objdump -d commands. llvm-svn: 366676
2019-07-22 19:37:03 +08:00
// RUN: ld.lld %t -o %t2
[ELF] ARM and AArch64 undefined weak reference values The ARM 32 and 64-bit ABI does not use 0 for undefined weak references that are used in PC relative relocations. In particular: - A branch relocation to an undefined weak resolves to the next instruction. Effectively making the branch a no-op - In all other cases the symbol resolves to the place so that S + A - P resolves to A. Differential Revision: https://reviews.llvm.org/D26240 llvm-svn: 286353
2016-11-09 18:22:29 +08:00
// RUN: llvm-objdump -triple=thumbv7a-none-linux-gnueabi -d %t2 | FileCheck %s
// Check that the ARM ABI rules for undefined weak symbols are applied.
// Branch instructions are resolved to the next instruction. Relative
// relocations are resolved to the place.
.syntax unified
.weak target
[LLD][ELF][ARM] Do not substitute BL/BLX for non STT_FUNC symbols. Recommit of 0b4a047bfbd11fe1f5abda8da0e2391c1918162a (reverted in c29003813ab9bd6ea7b6de40ea8f1fe21979f13f) to incorporate subsequent fix and add a warning when LLD's interworking behavior has changed. D73474 disabled the generation of interworking thunks for branch relocations to non STT_FUNC symbols. This patch handles the case of BL and BLX instructions to non STT_FUNC symbols. LLD would normally look at the state of the caller and the callee and write a BL if the states are the same and a BLX if the states are different. This patch disables BL/BLX substitution when the destination symbol does not have type STT_FUNC. This brings our behavior in line with GNU ld which may prevent difficult to diagnose runtime errors when switching to lld. This change does change how LLD handles interworking of symbols that do not have type STT_FUNC from previous versions including the 10.0 release. This brings LLD in line with ld.bfd but there may be programs that have not been linked with ld.bfd that depend on LLD's previous behavior. We emit a warning when the behavior changes. A summary of the difference between 10.0 and 11.0 is that for symbols that do not have a type of STT_FUNC LLD will not change a BL to a BLX or vice versa. The table below enumerates the changes | relocation | STT_FUNC | bit(0) | in | 10.0- out | 11.0+ out | | R_ARM_CALL | no | 1 | BL | BLX | BL | | R_ARM_CALL | no | 0 | BLX | BL | BLX | | R_ARM_THM_CALL | no | 1 | BLX | BL | BLX | | R_ARM_THM_CALL | no | 0 | BL | BLX | BL | Differential Revision: https://reviews.llvm.org/D73542
2020-02-13 16:42:17 +08:00
.type target, %function
[ELF] ARM and AArch64 undefined weak reference values The ARM 32 and 64-bit ABI does not use 0 for undefined weak references that are used in PC relative relocations. In particular: - A branch relocation to an undefined weak resolves to the next instruction. Effectively making the branch a no-op - In all other cases the symbol resolves to the place so that S + A - P resolves to A. Differential Revision: https://reviews.llvm.org/D26240 llvm-svn: 286353
2016-11-09 18:22:29 +08:00
.text
.global _start
_start:
// R_ARM_THM_JUMP19
beq.w target
// R_ARM_THM_JUMP24
b.w target
// R_ARM_THM_CALL
bl target
// R_ARM_THM_CALL with exchange
blx target
// R_ARM_THM_MOVT_PREL
movt r0, :upper16:target - .
// R_ARM_THM_MOVW_PREL_NC
movw r0, :lower16:target - .
[LLD][ELF][ARM] Implement Thumb pc-relative relocations for adr and ldr MC will now output the R_ARM_THM_PC8, R_ARM_THM_PC12 and R_ARM_THM_PREL_11_0 relocations. These are short-ranged relocations that are used to implement the adr rd, literal and ldr rd, literal pseudo instructions. The instructions use a new RelExpr called R_ARM_PCA in order to calculate the required S + A - Pa expression, where Pa is AlignDown(P, 4) as the instructions add their immediate to AlignDown(PC, 4). We also do not want these relocations to generate or resolve against a PLT entry as the range of these relocations is so short they would never reach. The R_ARM_THM_PC8 has a special encoding convention for the relocation addend, the immediate field is unsigned, yet the addend must be -4 to account for the Thumb PC bias. The ABI (not the architecture) uses the convention that the 8-byte immediate of 0xff represents -4. Differential Revision: https://reviews.llvm.org/D75042
2020-02-24 03:46:46 +08:00
// R_ARM_THM_ALU_PREL_11_0
adr r0, target
// R_ARM_THM_PC12
ldr r0, target
[ELF] ARM and AArch64 undefined weak reference values The ARM 32 and 64-bit ABI does not use 0 for undefined weak references that are used in PC relative relocations. In particular: - A branch relocation to an undefined weak resolves to the next instruction. Effectively making the branch a no-op - In all other cases the symbol resolves to the place so that S + A - P resolves to A. Differential Revision: https://reviews.llvm.org/D26240 llvm-svn: 286353
2016-11-09 18:22:29 +08:00
// CHECK: Disassembly of section .text:
[llvm-objdump] Print newlines before and after "Disassembly of section ...:" This improves readability and the behavior is consistent with GNU objdump. The new test test/tools/llvm-objdump/X86/disassemble-section-name.s checks we print newlines before and after "Disassembly of section ...:" Differential Revision: https://reviews.llvm.org/D61127 llvm-svn: 359668
2019-05-01 18:40:48 +08:00
// CHECK-EMPTY:
[ELF][ARM] Allow PT_LOAD to have overlapping p_offset ranges on EM_ARM Port the D64906 technique to ARM. It deletes 3 alignments at PT_LOAD boundaries for the default case: the size of an arm binary decreases by at most 12kb. Reviewed By: grimar Differential Revision: https://reviews.llvm.org/D66749 llvm-svn: 370049
2019-08-27 19:52:36 +08:00
// CHECK: 110b4: {{.*}} beq.w #0 <_start+0x4>
// CHECK-NEXT: 110b8: {{.*}} b.w #0 <_start+0x8>
// CHECK-NEXT: 110bc: {{.*}} bl #0
[ELF] ARM and AArch64 undefined weak reference values The ARM 32 and 64-bit ABI does not use 0 for undefined weak references that are used in PC relative relocations. In particular: - A branch relocation to an undefined weak resolves to the next instruction. Effectively making the branch a no-op - In all other cases the symbol resolves to the place so that S + A - P resolves to A. Differential Revision: https://reviews.llvm.org/D26240 llvm-svn: 286353
2016-11-09 18:22:29 +08:00
// blx is transformed into bl so we don't change state
[ELF][ARM] Allow PT_LOAD to have overlapping p_offset ranges on EM_ARM Port the D64906 technique to ARM. It deletes 3 alignments at PT_LOAD boundaries for the default case: the size of an arm binary decreases by at most 12kb. Reviewed By: grimar Differential Revision: https://reviews.llvm.org/D66749 llvm-svn: 370049
2019-08-27 19:52:36 +08:00
// CHECK-NEXT: 110c0: {{.*}} bl #0
// CHECK-NEXT: 110c4: {{.*}} movt r0, #0
// CHECK-NEXT: 110c8: {{.*}} movw r0, #0
[LLD][ELF][ARM] Implement Thumb pc-relative relocations for adr and ldr MC will now output the R_ARM_THM_PC8, R_ARM_THM_PC12 and R_ARM_THM_PREL_11_0 relocations. These are short-ranged relocations that are used to implement the adr rd, literal and ldr rd, literal pseudo instructions. The instructions use a new RelExpr called R_ARM_PCA in order to calculate the required S + A - Pa expression, where Pa is AlignDown(P, 4) as the instructions add their immediate to AlignDown(PC, 4). We also do not want these relocations to generate or resolve against a PLT entry as the range of these relocations is so short they would never reach. The R_ARM_THM_PC8 has a special encoding convention for the relocation addend, the immediate field is unsigned, yet the addend must be -4 to account for the Thumb PC bias. The ABI (not the architecture) uses the convention that the 8-byte immediate of 0xff represents -4. Differential Revision: https://reviews.llvm.org/D75042
2020-02-24 03:46:46 +08:00
// CHECK-NEXT: 110cc: {{.*}} adr.w r0, #-4
// CHECK-NEXT: 110d0: {{.*}} ldr.w r0, [pc, #-4]