2015-09-11 00:49:58 +08:00
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//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===//
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2005-04-22 08:00:37 +08:00
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//
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2003-10-21 04:20:30 +08:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:37:13 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 08:00:37 +08:00
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//
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2003-10-21 04:20:30 +08:00
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//===----------------------------------------------------------------------===//
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2003-10-06 03:27:59 +08:00
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//
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// This tablegen backend is responsible for emitting a description of the target
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// instruction set for the code generator.
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//
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//===----------------------------------------------------------------------===//
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2012-06-11 23:37:55 +08:00
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#include "CodeGenDAGPatterns.h"
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2016-12-13 06:23:53 +08:00
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#include "CodeGenInstruction.h"
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2012-07-07 12:00:00 +08:00
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#include "CodeGenSchedule.h"
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2004-08-01 12:04:35 +08:00
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#include "CodeGenTarget.h"
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2012-04-02 02:14:14 +08:00
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#include "SequenceToOffsetTable.h"
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2012-12-04 18:37:14 +08:00
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#include "TableGenBackends.h"
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2016-12-13 06:23:53 +08:00
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#include "llvm/ADT/ArrayRef.h"
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2009-08-24 11:52:50 +08:00
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#include "llvm/ADT/StringExtras.h"
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2016-12-13 06:23:53 +08:00
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/raw_ostream.h"
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2012-10-26 04:33:17 +08:00
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#include "llvm/TableGen/Error.h"
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2012-06-11 23:37:55 +08:00
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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2016-12-13 06:23:53 +08:00
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#include <cassert>
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#include <cstdint>
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2012-06-11 23:37:55 +08:00
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#include <map>
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2016-12-13 06:23:53 +08:00
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#include <string>
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#include <utility>
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2012-06-11 23:37:55 +08:00
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#include <vector>
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2015-09-11 00:49:58 +08:00
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2004-08-01 11:55:39 +08:00
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using namespace llvm;
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2003-11-12 06:41:34 +08:00
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2012-06-11 23:37:55 +08:00
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namespace {
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2016-12-13 06:23:53 +08:00
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2012-06-11 23:37:55 +08:00
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class InstrInfoEmitter {
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RecordKeeper &Records;
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CodeGenDAGPatterns CDP;
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2012-07-07 12:00:00 +08:00
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const CodeGenSchedModels &SchedModels;
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2012-06-11 23:37:55 +08:00
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public:
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2012-07-07 12:00:00 +08:00
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InstrInfoEmitter(RecordKeeper &R):
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Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
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2012-06-11 23:37:55 +08:00
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// run - Output the instruction set description.
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void run(raw_ostream &OS);
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private:
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void emitEnums(raw_ostream &OS);
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typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
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TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
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/// The keys of this map are maps which have OpName enum values as their keys
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/// and instruction operand indices as their values. The values of this map
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/// are lists of instruction names.
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typedef std::map<std::map<unsigned, unsigned>,
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2016-12-13 06:23:53 +08:00
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std::vector<std::string>> OpNameMapTy;
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TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
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typedef std::map<std::string, unsigned>::iterator StrUintMapIter;
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2012-06-11 23:37:55 +08:00
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void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EL,
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const OperandInfoMapTy &OpInfo,
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raw_ostream &OS);
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2013-11-18 05:24:41 +08:00
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void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target);
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
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void initOperandMapData(
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2016-02-01 09:33:42 +08:00
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ArrayRef<const CodeGenInstruction *> NumberedInstructions,
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2017-07-07 14:22:35 +08:00
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StringRef Namespace,
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2014-02-05 15:27:49 +08:00
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std::map<std::string, unsigned> &Operands,
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OpNameMapTy &OperandMap);
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TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
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void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
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2016-02-01 09:33:42 +08:00
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ArrayRef<const CodeGenInstruction*> NumberedInstructions);
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2012-06-11 23:37:55 +08:00
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// Operand information.
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void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
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std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
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};
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2016-12-13 06:23:53 +08:00
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2015-09-11 00:49:58 +08:00
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} // end anonymous namespace
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2012-06-11 23:37:55 +08:00
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2008-01-06 09:21:51 +08:00
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static void PrintDefList(const std::vector<Record*> &Uses,
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2009-07-03 08:10:29 +08:00
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unsigned Num, raw_ostream &OS) {
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2015-12-05 15:13:35 +08:00
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OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
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2016-02-16 10:48:30 +08:00
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for (Record *U : Uses)
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OS << getQualifiedName(U) << ", ";
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2003-10-06 03:27:59 +08:00
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OS << "0 };\n";
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}
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2008-01-06 09:20:13 +08:00
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//===----------------------------------------------------------------------===//
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// Operand Info Emission.
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//===----------------------------------------------------------------------===//
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2006-11-07 07:49:51 +08:00
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std::vector<std::string>
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InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
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std::vector<std::string> Result;
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2011-06-28 05:06:21 +08:00
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2014-04-18 10:09:07 +08:00
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for (auto &Op : Inst.Operands) {
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2006-11-10 10:01:40 +08:00
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// Handle aggregate operands and normal operands the same way by expanding
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// either case into a list of operands for this op.
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2010-11-01 12:03:32 +08:00
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std::vector<CGIOperandList::OperandInfo> OperandList;
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2006-11-10 10:01:40 +08:00
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// This might be a multiple operand thing. Targets like X86 have
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// registers in their multi-operand operands. It may also be an anonymous
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// operand, which has a single operand, but no declared class for the
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// operand.
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2014-04-18 10:09:07 +08:00
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DagInit *MIOI = Op.MIOperandInfo;
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2011-06-28 05:06:21 +08:00
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2006-11-10 10:01:40 +08:00
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if (!MIOI || MIOI->getNumArgs() == 0) {
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// Single, anonymous, operand.
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2014-04-18 10:09:07 +08:00
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OperandList.push_back(Op);
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2005-11-19 15:05:57 +08:00
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} else {
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2014-04-18 10:09:07 +08:00
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for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) {
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OperandList.push_back(Op);
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2006-11-07 07:49:51 +08:00
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2016-12-13 06:23:53 +08:00
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auto *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
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2006-11-10 10:01:40 +08:00
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OperandList.back().Rec = OpR;
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}
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}
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2006-11-07 07:53:31 +08:00
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2006-11-10 10:01:40 +08:00
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for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
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Record *OpR = OperandList[j].Rec;
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std::string Res;
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2011-06-28 05:06:21 +08:00
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if (OpR->isSubClassOf("RegisterOperand"))
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OpR = OpR->getValueAsDef("RegClass");
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2006-11-10 10:01:40 +08:00
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if (OpR->isSubClassOf("RegisterClass"))
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Res += getQualifiedName(OpR) + "RegClassID, ";
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2009-07-30 05:10:12 +08:00
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else if (OpR->isSubClassOf("PointerLikeRegClass"))
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Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
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2006-11-10 10:01:40 +08:00
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else
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2010-06-19 02:13:55 +08:00
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// -1 means the operand does not have a fixed register class.
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Res += "-1, ";
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2011-06-28 05:06:21 +08:00
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2006-11-10 10:01:40 +08:00
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// Fill in applicable flags.
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Res += "0";
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2011-06-28 05:06:21 +08:00
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2006-11-10 10:01:40 +08:00
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// Ptr value whose register class is resolved via callback.
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2009-07-30 04:43:05 +08:00
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if (OpR->isSubClassOf("PointerLikeRegClass"))
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2011-06-29 03:10:37 +08:00
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Res += "|(1<<MCOI::LookupPtrRegClass)";
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2006-11-10 10:01:40 +08:00
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// Predicate operands. Check to see if the original unexpanded operand
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2013-08-22 17:57:11 +08:00
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// was of type PredicateOp.
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2014-04-18 10:09:07 +08:00
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if (Op.Rec->isSubClassOf("PredicateOp"))
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2011-06-29 03:10:37 +08:00
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Res += "|(1<<MCOI::Predicate)";
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2011-06-28 05:06:21 +08:00
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2007-07-11 02:05:01 +08:00
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// Optional def operands. Check to see if the original unexpanded operand
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// was of type OptionalDefOperand.
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2014-04-18 10:09:07 +08:00
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if (Op.Rec->isSubClassOf("OptionalDefOperand"))
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2011-06-29 03:10:37 +08:00
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Res += "|(1<<MCOI::OptionalDef)";
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2007-07-11 02:05:01 +08:00
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2012-03-11 09:57:56 +08:00
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// Fill in operand type.
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2015-01-13 03:33:09 +08:00
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Res += ", ";
|
2014-04-18 10:09:07 +08:00
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assert(!Op.OperandType.empty() && "Invalid operand type.");
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Res += Op.OperandType;
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2012-03-11 09:57:56 +08:00
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2006-11-10 10:01:40 +08:00
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// Fill in constraint info.
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2010-02-10 09:45:28 +08:00
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Res += ", ";
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2011-06-28 05:06:21 +08:00
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2010-11-01 12:03:32 +08:00
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const CGIOperandList::ConstraintInfo &Constraint =
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2014-04-18 10:09:07 +08:00
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Op.Constraints[j];
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2010-02-10 09:45:28 +08:00
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if (Constraint.isNone())
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Res += "0";
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else if (Constraint.isEarlyClobber())
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2011-06-29 03:10:37 +08:00
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Res += "(1 << MCOI::EARLY_CLOBBER)";
|
2010-02-10 09:45:28 +08:00
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else {
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assert(Constraint.isTied());
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Res += "((" + utostr(Constraint.getTiedOperand()) +
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2011-06-29 03:10:37 +08:00
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" << 16) | (1 << MCOI::TIED_TO))";
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2010-02-10 09:45:28 +08:00
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}
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2011-06-28 05:06:21 +08:00
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2006-11-10 10:01:40 +08:00
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Result.push_back(Res);
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2005-08-20 02:46:26 +08:00
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}
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}
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2006-11-01 08:27:05 +08:00
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2005-08-20 02:46:26 +08:00
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return Result;
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}
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2011-06-28 05:06:21 +08:00
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void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
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2008-01-06 09:20:13 +08:00
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OperandInfoMapTy &OperandInfoIDs) {
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// ID #0 is for no operand info.
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unsigned OperandListNum = 0;
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OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
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2011-06-28 05:06:21 +08:00
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2008-01-06 09:20:13 +08:00
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OS << "\n";
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const CodeGenTarget &Target = CDP.getTargetInfo();
|
2016-01-18 04:38:18 +08:00
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for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
|
2014-04-18 10:09:07 +08:00
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std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
|
2008-01-06 09:20:13 +08:00
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unsigned &N = OperandInfoIDs[OperandInfo];
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if (N != 0) continue;
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2011-06-28 05:06:21 +08:00
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2008-01-06 09:20:13 +08:00
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N = ++OperandListNum;
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2011-06-29 03:10:37 +08:00
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OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
|
2014-04-18 10:09:07 +08:00
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for (const std::string &Info : OperandInfo)
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OS << "{ " << Info << " }, ";
|
2008-01-06 09:20:13 +08:00
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OS << "};\n";
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}
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}
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|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
/// Initialize data structures for generating operand name mappings.
|
|
|
|
///
|
|
|
|
/// \param Operands [out] A map used to generate the OpName enum with operand
|
|
|
|
/// names as its keys and operand enum values as its values.
|
|
|
|
/// \param OperandMap [out] A map for representing the operand name mappings for
|
|
|
|
/// each instructions. This is used to generate the OperandMap table as
|
|
|
|
/// well as the getNamedOperandIdx() function.
|
|
|
|
void InstrInfoEmitter::initOperandMapData(
|
2016-02-01 09:33:42 +08:00
|
|
|
ArrayRef<const CodeGenInstruction *> NumberedInstructions,
|
2017-07-07 14:22:35 +08:00
|
|
|
StringRef Namespace,
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
std::map<std::string, unsigned> &Operands,
|
|
|
|
OpNameMapTy &OperandMap) {
|
|
|
|
unsigned NumOperands = 0;
|
2014-04-18 10:09:07 +08:00
|
|
|
for (const CodeGenInstruction *Inst : NumberedInstructions) {
|
|
|
|
if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
continue;
|
|
|
|
std::map<unsigned, unsigned> OpList;
|
2014-04-18 10:09:07 +08:00
|
|
|
for (const auto &Info : Inst->Operands) {
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
StrUintMapIter I = Operands.find(Info.Name);
|
|
|
|
|
|
|
|
if (I == Operands.end()) {
|
|
|
|
I = Operands.insert(Operands.begin(),
|
|
|
|
std::pair<std::string, unsigned>(Info.Name, NumOperands++));
|
|
|
|
}
|
|
|
|
OpList[I->second] = Info.MIOperandNo;
|
|
|
|
}
|
2017-07-07 14:22:35 +08:00
|
|
|
OperandMap[OpList].push_back(Namespace.str() + "::" +
|
2016-12-04 13:48:16 +08:00
|
|
|
Inst->TheDef->getName().str());
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Generate a table and function for looking up the indices of operands by
|
|
|
|
/// name.
|
|
|
|
///
|
|
|
|
/// This code generates:
|
|
|
|
/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
|
|
|
|
/// for each operand name.
|
|
|
|
/// - A 2-dimensional table called OperandMap for mapping OpName enum values to
|
|
|
|
/// operand indices.
|
|
|
|
/// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
|
|
|
|
/// for looking up the operand index for an instruction, given a value from
|
|
|
|
/// OpName enum
|
|
|
|
void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
|
|
|
|
const CodeGenTarget &Target,
|
2016-02-01 09:33:42 +08:00
|
|
|
ArrayRef<const CodeGenInstruction*> NumberedInstructions) {
|
2017-07-07 14:22:35 +08:00
|
|
|
StringRef Namespace = Target.getInstNamespace();
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
std::string OpNameNS = "OpName";
|
|
|
|
// Map of operand names to their enumeration value. This will be used to
|
|
|
|
// generate the OpName enum.
|
|
|
|
std::map<std::string, unsigned> Operands;
|
|
|
|
OpNameMapTy OperandMap;
|
|
|
|
|
|
|
|
initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap);
|
|
|
|
|
|
|
|
OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
|
|
|
|
OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
|
2015-03-13 09:10:08 +08:00
|
|
|
OS << "namespace llvm {\n";
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
OS << "namespace " << Namespace << " {\n";
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "namespace " << OpNameNS << " {\n";
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
OS << "enum {\n";
|
2014-04-18 10:09:07 +08:00
|
|
|
for (const auto &Op : Operands)
|
|
|
|
OS << " " << Op.first << " = " << Op.second << ",\n";
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
|
|
|
|
OS << "OPERAND_LAST";
|
|
|
|
OS << "\n};\n";
|
2015-09-11 00:49:58 +08:00
|
|
|
OS << "} // end namespace OpName\n";
|
|
|
|
OS << "} // end namespace " << Namespace << "\n";
|
|
|
|
OS << "} // end namespace llvm\n";
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n\n";
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
|
|
|
|
OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n";
|
|
|
|
OS << "#undef GET_INSTRINFO_NAMED_OPS\n";
|
2015-03-13 09:10:08 +08:00
|
|
|
OS << "namespace llvm {\n";
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
OS << "namespace " << Namespace << " {\n";
|
2014-08-02 01:00:27 +08:00
|
|
|
OS << "LLVM_READONLY\n";
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n";
|
2013-07-16 00:53:32 +08:00
|
|
|
if (!Operands.empty()) {
|
|
|
|
OS << " static const int16_t OperandMap [][" << Operands.size()
|
|
|
|
<< "] = {\n";
|
2014-04-18 10:09:07 +08:00
|
|
|
for (const auto &Entry : OperandMap) {
|
|
|
|
const std::map<unsigned, unsigned> &OpList = Entry.first;
|
2013-07-16 00:53:32 +08:00
|
|
|
OS << "{";
|
|
|
|
|
|
|
|
// Emit a row of the OperandMap table
|
2014-04-18 10:09:07 +08:00
|
|
|
for (unsigned i = 0, e = Operands.size(); i != e; ++i)
|
|
|
|
OS << (OpList.count(i) == 0 ? -1 : (int)OpList.find(i)->second) << ", ";
|
2013-07-16 00:53:32 +08:00
|
|
|
|
|
|
|
OS << "},\n";
|
|
|
|
}
|
|
|
|
OS << "};\n";
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
|
2013-07-16 00:53:32 +08:00
|
|
|
OS << " switch(Opcode) {\n";
|
|
|
|
unsigned TableIndex = 0;
|
2014-04-18 10:09:07 +08:00
|
|
|
for (const auto &Entry : OperandMap) {
|
|
|
|
for (const std::string &Name : Entry.second)
|
|
|
|
OS << " case " << Name << ":\n";
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
|
2013-07-16 00:53:32 +08:00
|
|
|
OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n";
|
|
|
|
}
|
|
|
|
OS << " default: return -1;\n";
|
|
|
|
OS << " }\n";
|
|
|
|
} else {
|
|
|
|
// There are no operands, so no need to emit anything
|
|
|
|
OS << " return -1;\n";
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
}
|
|
|
|
OS << "}\n";
|
2015-09-11 00:49:58 +08:00
|
|
|
OS << "} // end namespace " << Namespace << "\n";
|
|
|
|
OS << "} // end namespace llvm\n";
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "#endif //GET_INSTRINFO_NAMED_OPS\n\n";
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
}
|
|
|
|
|
2013-11-18 05:24:41 +08:00
|
|
|
/// Generate an enum for all the operand types for this target, under the
|
|
|
|
/// llvm::TargetNamespace::OpTypes namespace.
|
|
|
|
/// Operand types are all definitions derived of the Operand Target.td class.
|
|
|
|
void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS,
|
|
|
|
const CodeGenTarget &Target) {
|
|
|
|
|
2017-07-07 14:22:35 +08:00
|
|
|
StringRef Namespace = Target.getInstNamespace();
|
2013-11-18 05:24:41 +08:00
|
|
|
std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
|
|
|
|
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
|
2013-11-18 05:24:41 +08:00
|
|
|
OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
|
2015-03-13 09:10:08 +08:00
|
|
|
OS << "namespace llvm {\n";
|
2013-11-18 05:24:41 +08:00
|
|
|
OS << "namespace " << Namespace << " {\n";
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "namespace OpTypes {\n";
|
2013-11-18 05:24:41 +08:00
|
|
|
OS << "enum OperandType {\n";
|
|
|
|
|
2014-04-18 10:09:07 +08:00
|
|
|
unsigned EnumVal = 0;
|
|
|
|
for (const Record *Op : Operands) {
|
|
|
|
if (!Op->isAnonymous())
|
|
|
|
OS << " " << Op->getName() << " = " << EnumVal << ",\n";
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|
|
|
++EnumVal;
|
2013-11-18 05:24:41 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
OS << " OPERAND_TYPE_LIST_END" << "\n};\n";
|
2015-09-11 00:49:58 +08:00
|
|
|
OS << "} // end namespace OpTypes\n";
|
|
|
|
OS << "} // end namespace " << Namespace << "\n";
|
|
|
|
OS << "} // end namespace llvm\n";
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
|
2013-11-18 05:24:41 +08:00
|
|
|
}
|
|
|
|
|
2008-01-06 09:20:13 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Main Output.
|
|
|
|
//===----------------------------------------------------------------------===//
|
2003-10-06 03:27:59 +08:00
|
|
|
|
|
|
|
// run - Emit the main instruction description records for the target...
|
2009-07-03 08:10:29 +08:00
|
|
|
void InstrInfoEmitter::run(raw_ostream &OS) {
|
2016-02-11 15:39:27 +08:00
|
|
|
emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
|
2011-06-29 04:07:07 +08:00
|
|
|
emitEnums(OS);
|
|
|
|
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
|
2011-06-29 04:07:07 +08:00
|
|
|
OS << "#undef GET_INSTRINFO_MC_DESC\n";
|
|
|
|
|
2004-08-17 11:08:28 +08:00
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
|
2008-04-03 08:02:49 +08:00
|
|
|
CodeGenTarget &Target = CDP.getTargetInfo();
|
2003-10-06 03:27:59 +08:00
|
|
|
const std::string &TargetName = Target.getName();
|
|
|
|
Record *InstrInfo = Target.getInstructionSet();
|
|
|
|
|
2005-08-19 05:36:47 +08:00
|
|
|
// Keep track of all of the def lists we have emitted already.
|
|
|
|
std::map<std::vector<Record*>, unsigned> EmittedLists;
|
|
|
|
unsigned ListNumber = 0;
|
2011-06-28 05:06:21 +08:00
|
|
|
|
2005-08-19 05:36:47 +08:00
|
|
|
// Emit all of the instruction's implicit uses and defs.
|
2016-01-18 04:38:18 +08:00
|
|
|
for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
|
2014-04-18 10:09:07 +08:00
|
|
|
Record *Inst = II->TheDef;
|
2005-10-29 06:59:53 +08:00
|
|
|
std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
|
|
|
|
if (!Uses.empty()) {
|
2005-08-19 05:36:47 +08:00
|
|
|
unsigned &IL = EmittedLists[Uses];
|
2008-01-06 09:21:51 +08:00
|
|
|
if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
|
2005-08-19 05:36:47 +08:00
|
|
|
}
|
2005-10-29 06:59:53 +08:00
|
|
|
std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
|
|
|
|
if (!Defs.empty()) {
|
|
|
|
unsigned &IL = EmittedLists[Defs];
|
2008-01-06 09:21:51 +08:00
|
|
|
if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
|
2005-08-19 05:36:47 +08:00
|
|
|
}
|
2003-10-06 03:27:59 +08:00
|
|
|
}
|
|
|
|
|
2008-01-06 09:20:13 +08:00
|
|
|
OperandInfoMapTy OperandInfoIDs;
|
2011-06-28 05:06:21 +08:00
|
|
|
|
2005-08-20 00:57:28 +08:00
|
|
|
// Emit all of the operand info records.
|
2008-01-06 09:20:13 +08:00
|
|
|
EmitOperandInfo(OS, OperandInfoIDs);
|
2011-06-28 05:06:21 +08:00
|
|
|
|
2011-06-29 03:10:37 +08:00
|
|
|
// Emit all of the MCInstrDesc records in their ENUM ordering.
|
2005-08-20 00:57:28 +08:00
|
|
|
//
|
2011-10-23 00:50:00 +08:00
|
|
|
OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
|
2016-02-01 09:33:42 +08:00
|
|
|
ArrayRef<const CodeGenInstruction*> NumberedInstructions =
|
2010-03-19 08:34:35 +08:00
|
|
|
Target.getInstructionsByEnumValue();
|
2003-10-06 03:27:59 +08:00
|
|
|
|
2012-04-02 02:14:14 +08:00
|
|
|
SequenceToOffsetTable<std::string> InstrNames;
|
2014-04-18 10:09:07 +08:00
|
|
|
unsigned Num = 0;
|
|
|
|
for (const CodeGenInstruction *Inst : NumberedInstructions) {
|
|
|
|
// Keep a list of the instruction names.
|
|
|
|
InstrNames.add(Inst->TheDef->getName());
|
|
|
|
// Emit the record into the table.
|
|
|
|
emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS);
|
2012-04-02 02:14:14 +08:00
|
|
|
}
|
2014-04-18 10:09:07 +08:00
|
|
|
OS << "};\n\n";
|
2012-04-02 02:14:14 +08:00
|
|
|
|
2014-04-18 10:09:07 +08:00
|
|
|
// Emit the array of instruction names.
|
2012-04-02 02:14:14 +08:00
|
|
|
InstrNames.layout();
|
|
|
|
OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
|
|
|
|
InstrNames.emit(OS, printChar);
|
|
|
|
OS << "};\n\n";
|
|
|
|
|
|
|
|
OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
|
2014-04-18 10:09:07 +08:00
|
|
|
Num = 0;
|
|
|
|
for (const CodeGenInstruction *Inst : NumberedInstructions) {
|
|
|
|
// Newline every eight entries.
|
|
|
|
if (Num % 8 == 0)
|
2012-02-10 21:18:44 +08:00
|
|
|
OS << "\n ";
|
2014-04-18 10:09:07 +08:00
|
|
|
OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
|
|
|
|
++Num;
|
2012-02-10 21:18:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
OS << "\n};\n\n";
|
|
|
|
|
2011-06-29 04:29:03 +08:00
|
|
|
// MCInstrInfo initialization routine.
|
|
|
|
OS << "static inline void Init" << TargetName
|
|
|
|
<< "MCInstrInfo(MCInstrInfo *II) {\n";
|
|
|
|
OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
|
2012-02-10 21:18:44 +08:00
|
|
|
<< TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
|
2011-06-29 04:29:03 +08:00
|
|
|
<< NumberedInstructions.size() << ");\n}\n\n";
|
|
|
|
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "} // end llvm namespace\n";
|
2011-06-29 04:07:07 +08:00
|
|
|
|
|
|
|
OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
|
2011-07-02 01:57:27 +08:00
|
|
|
|
|
|
|
// Create a TargetInstrInfo subclass to hide the MC layer initialization.
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "#ifdef GET_INSTRINFO_HEADER\n";
|
2011-07-02 01:57:27 +08:00
|
|
|
OS << "#undef GET_INSTRINFO_HEADER\n";
|
|
|
|
|
|
|
|
std::string ClassName = TargetName + "GenInstrInfo";
|
2011-07-02 04:45:01 +08:00
|
|
|
OS << "namespace llvm {\n";
|
2012-11-28 10:35:17 +08:00
|
|
|
OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
|
2015-03-13 09:26:39 +08:00
|
|
|
<< " explicit " << ClassName
|
XRay: Add entry and exit sleds
Summary:
In this patch we implement the following parts of XRay:
- Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches.
- Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts).
- X86-specific nop sleds as described in the white paper.
- A machine function pass that adds the different instrumentation marker instructions at a very late stage.
- A way of identifying which return opcode is considered "normal" for each architecture.
There are some caveats here:
1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet.
2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library.
Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk
Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits
Differential Revision: http://reviews.llvm.org/D19904
llvm-svn: 275367
2016-07-14 12:06:33 +08:00
|
|
|
<< "(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);\n"
|
2016-12-13 06:23:53 +08:00
|
|
|
<< " ~" << ClassName << "() override = default;\n"
|
2011-07-02 01:57:27 +08:00
|
|
|
<< "};\n";
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "} // end llvm namespace\n";
|
2011-07-02 01:57:27 +08:00
|
|
|
|
|
|
|
OS << "#endif // GET_INSTRINFO_HEADER\n\n";
|
|
|
|
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "#ifdef GET_INSTRINFO_CTOR_DTOR\n";
|
2013-11-19 08:57:56 +08:00
|
|
|
OS << "#undef GET_INSTRINFO_CTOR_DTOR\n";
|
2011-07-02 01:57:27 +08:00
|
|
|
|
2011-07-02 04:45:01 +08:00
|
|
|
OS << "namespace llvm {\n";
|
2011-10-23 00:50:00 +08:00
|
|
|
OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
|
2012-03-16 02:05:57 +08:00
|
|
|
OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
|
2012-04-02 02:14:14 +08:00
|
|
|
OS << "extern const char " << TargetName << "InstrNameData[];\n";
|
2015-03-13 09:26:39 +08:00
|
|
|
OS << ClassName << "::" << ClassName
|
XRay: Add entry and exit sleds
Summary:
In this patch we implement the following parts of XRay:
- Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches.
- Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts).
- X86-specific nop sleds as described in the white paper.
- A machine function pass that adds the different instrumentation marker instructions at a very late stage.
- A way of identifying which return opcode is considered "normal" for each architecture.
There are some caveats here:
1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet.
2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library.
Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk
Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits
Differential Revision: http://reviews.llvm.org/D19904
llvm-svn: 275367
2016-07-14 12:06:33 +08:00
|
|
|
<< "(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)\n"
|
|
|
|
<< " : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {\n"
|
2015-03-13 09:26:39 +08:00
|
|
|
<< " InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
|
|
|
|
<< "InstrNameIndices, " << TargetName << "InstrNameData, "
|
2015-09-11 00:49:58 +08:00
|
|
|
<< NumberedInstructions.size() << ");\n}\n";
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "} // end llvm namespace\n";
|
2011-07-02 01:57:27 +08:00
|
|
|
|
2013-11-19 08:57:56 +08:00
|
|
|
OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
|
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
llvm-svn: 184879
2013-06-26 05:22:09 +08:00
|
|
|
|
|
|
|
emitOperandNameMappings(OS, Target, NumberedInstructions);
|
2013-11-18 05:24:41 +08:00
|
|
|
|
|
|
|
emitOperandTypesEnum(OS, Target);
|
2003-10-06 03:27:59 +08:00
|
|
|
}
|
|
|
|
|
2004-08-01 13:04:00 +08:00
|
|
|
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
|
2005-08-19 05:36:47 +08:00
|
|
|
Record *InstrInfo,
|
2005-10-29 06:59:53 +08:00
|
|
|
std::map<std::vector<Record*>, unsigned> &EmittedLists,
|
2008-01-06 09:20:13 +08:00
|
|
|
const OperandInfoMapTy &OpInfo,
|
2009-07-03 08:10:29 +08:00
|
|
|
raw_ostream &OS) {
|
2008-01-06 09:53:37 +08:00
|
|
|
int MinOperands = 0;
|
2012-10-13 01:57:35 +08:00
|
|
|
if (!Inst.Operands.empty())
|
2005-08-19 08:59:49 +08:00
|
|
|
// Each logical operand can be multiple MI operands.
|
2010-11-01 12:03:32 +08:00
|
|
|
MinOperands = Inst.Operands.back().MIOperandNo +
|
|
|
|
Inst.Operands.back().MINumOperands;
|
2008-05-30 03:57:41 +08:00
|
|
|
|
2006-11-17 09:46:27 +08:00
|
|
|
OS << " { ";
|
2007-08-02 08:20:17 +08:00
|
|
|
OS << Num << ",\t" << MinOperands << ",\t"
|
2011-07-14 07:22:26 +08:00
|
|
|
<< Inst.Operands.NumDefs << ",\t"
|
2015-05-29 02:03:07 +08:00
|
|
|
<< Inst.TheDef->getValueAsInt("Size") << ",\t"
|
|
|
|
<< SchedModels.getSchedClassIdx(Inst) << ",\t0";
|
2003-10-06 03:27:59 +08:00
|
|
|
|
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers. This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.
Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).
Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.
Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.
Clear the IsRenamable bit when changing an operand's register value.
Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.
Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.
Reviewers: qcolombet, MatzeB
Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D43042
llvm-svn: 325931
2018-02-24 02:25:08 +08:00
|
|
|
CodeGenTarget &Target = CDP.getTargetInfo();
|
|
|
|
|
2015-02-26 08:00:33 +08:00
|
|
|
// Emit all of the target independent flags...
|
2015-05-29 02:33:39 +08:00
|
|
|
if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)";
|
|
|
|
if (Inst.isReturn) OS << "|(1ULL<<MCID::Return)";
|
|
|
|
if (Inst.isBranch) OS << "|(1ULL<<MCID::Branch)";
|
|
|
|
if (Inst.isIndirectBranch) OS << "|(1ULL<<MCID::IndirectBranch)";
|
|
|
|
if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)";
|
|
|
|
if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)";
|
|
|
|
if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)";
|
2016-09-14 16:20:03 +08:00
|
|
|
if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)";
|
2015-05-29 02:33:39 +08:00
|
|
|
if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)";
|
|
|
|
if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)";
|
|
|
|
if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)";
|
|
|
|
if (Inst.isCall) OS << "|(1ULL<<MCID::Call)";
|
|
|
|
if (Inst.canFoldAsLoad) OS << "|(1ULL<<MCID::FoldableAsLoad)";
|
|
|
|
if (Inst.mayLoad) OS << "|(1ULL<<MCID::MayLoad)";
|
|
|
|
if (Inst.mayStore) OS << "|(1ULL<<MCID::MayStore)";
|
|
|
|
if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)";
|
|
|
|
if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
|
|
|
|
if (Inst.isCommutable) OS << "|(1ULL<<MCID::Commutable)";
|
|
|
|
if (Inst.isTerminator) OS << "|(1ULL<<MCID::Terminator)";
|
|
|
|
if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)";
|
|
|
|
if (Inst.isNotDuplicable) OS << "|(1ULL<<MCID::NotDuplicable)";
|
|
|
|
if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)";
|
|
|
|
if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)";
|
|
|
|
if (Inst.hasPostISelHook) OS << "|(1ULL<<MCID::HasPostISelHook)";
|
|
|
|
if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)";
|
|
|
|
if (Inst.hasSideEffects) OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
|
|
|
|
if (Inst.isAsCheapAsAMove) OS << "|(1ULL<<MCID::CheapAsAMove)";
|
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers. This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.
Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).
Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.
Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.
Clear the IsRenamable bit when changing an operand's register value.
Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.
Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.
Reviewers: qcolombet, MatzeB
Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D43042
llvm-svn: 325931
2018-02-24 02:25:08 +08:00
|
|
|
if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq)
|
|
|
|
OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
|
|
|
|
if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq)
|
|
|
|
OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
|
2015-05-29 02:33:39 +08:00
|
|
|
if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
|
|
|
|
if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
|
|
|
|
if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
|
|
|
|
if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
|
2003-10-06 03:27:59 +08:00
|
|
|
|
|
|
|
// Emit all of the target-specific flags...
|
2011-07-30 06:43:06 +08:00
|
|
|
BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
|
2012-10-26 04:33:17 +08:00
|
|
|
if (!TSF)
|
|
|
|
PrintFatalError("no TSFlags?");
|
2010-04-05 11:10:20 +08:00
|
|
|
uint64_t Value = 0;
|
|
|
|
for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
|
2016-12-13 06:23:53 +08:00
|
|
|
if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
|
2010-04-05 11:10:20 +08:00
|
|
|
Value |= uint64_t(Bit->getValue()) << i;
|
|
|
|
else
|
2012-10-26 04:33:17 +08:00
|
|
|
PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName());
|
2010-04-05 11:10:20 +08:00
|
|
|
}
|
|
|
|
OS << ", 0x";
|
|
|
|
OS.write_hex(Value);
|
2010-06-10 00:16:48 +08:00
|
|
|
OS << "ULL, ";
|
2003-10-06 03:27:59 +08:00
|
|
|
|
|
|
|
// Emit the implicit uses and defs lists...
|
2005-10-29 06:59:53 +08:00
|
|
|
std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
|
|
|
|
if (UseList.empty())
|
2014-04-30 13:53:35 +08:00
|
|
|
OS << "nullptr, ";
|
2005-04-22 08:00:37 +08:00
|
|
|
else
|
2005-10-29 06:59:53 +08:00
|
|
|
OS << "ImplicitList" << EmittedLists[UseList] << ", ";
|
2003-10-06 03:27:59 +08:00
|
|
|
|
2005-10-29 06:59:53 +08:00
|
|
|
std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
|
|
|
|
if (DefList.empty())
|
2014-04-30 13:53:35 +08:00
|
|
|
OS << "nullptr, ";
|
2005-04-22 08:00:37 +08:00
|
|
|
else
|
2005-10-29 06:59:53 +08:00
|
|
|
OS << "ImplicitList" << EmittedLists[DefList] << ", ";
|
2003-10-06 03:27:59 +08:00
|
|
|
|
2005-08-20 00:57:28 +08:00
|
|
|
// Emit the operand info.
|
2006-11-07 07:49:51 +08:00
|
|
|
std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
|
2005-08-20 02:46:26 +08:00
|
|
|
if (OperandInfo.empty())
|
2014-04-30 13:53:35 +08:00
|
|
|
OS << "nullptr";
|
2005-08-20 00:57:28 +08:00
|
|
|
else
|
2008-01-06 09:20:13 +08:00
|
|
|
OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
|
2003-10-06 03:27:59 +08:00
|
|
|
|
2013-09-12 18:28:05 +08:00
|
|
|
if (Inst.HasComplexDeprecationPredicate)
|
|
|
|
// Emit a function pointer to the complex predicate method.
|
2015-05-26 18:47:10 +08:00
|
|
|
OS << ", -1 "
|
2013-09-12 18:28:05 +08:00
|
|
|
<< ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
|
|
|
|
else if (!Inst.DeprecatedReason.empty())
|
|
|
|
// Emit the Subtarget feature.
|
2015-05-26 18:47:10 +08:00
|
|
|
OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
|
|
|
|
<< " ,nullptr";
|
2013-09-12 18:28:05 +08:00
|
|
|
else
|
|
|
|
// Instruction isn't deprecated.
|
2015-05-26 18:47:10 +08:00
|
|
|
OS << ", -1 ,nullptr";
|
2013-09-12 18:28:05 +08:00
|
|
|
|
2010-04-05 11:10:20 +08:00
|
|
|
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
|
2003-10-06 03:27:59 +08:00
|
|
|
}
|
2011-06-29 04:07:07 +08:00
|
|
|
|
|
|
|
// emitEnums - Print out enum values for all of the instructions.
|
|
|
|
void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "#ifdef GET_INSTRINFO_ENUM\n";
|
2011-06-29 04:07:07 +08:00
|
|
|
OS << "#undef GET_INSTRINFO_ENUM\n";
|
|
|
|
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
|
|
|
|
CodeGenTarget Target(Records);
|
|
|
|
|
|
|
|
// We must emit the PHI opcode first...
|
2017-07-07 14:22:35 +08:00
|
|
|
StringRef Namespace = Target.getInstNamespace();
|
2012-04-12 05:02:30 +08:00
|
|
|
|
2015-05-12 06:17:13 +08:00
|
|
|
if (Namespace.empty())
|
|
|
|
PrintFatalError("No instructions defined!");
|
2011-06-29 04:07:07 +08:00
|
|
|
|
|
|
|
OS << "namespace " << Namespace << " {\n";
|
|
|
|
OS << " enum {\n";
|
2014-04-18 10:09:07 +08:00
|
|
|
unsigned Num = 0;
|
2016-02-11 15:39:22 +08:00
|
|
|
for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue())
|
2014-04-18 10:09:07 +08:00
|
|
|
OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n";
|
2016-02-11 15:39:22 +08:00
|
|
|
OS << " INSTRUCTION_LIST_END = " << Num << "\n";
|
2014-11-23 17:40:10 +08:00
|
|
|
OS << " };\n\n";
|
2017-12-13 15:26:17 +08:00
|
|
|
OS << "} // end " << Namespace << " namespace\n";
|
|
|
|
OS << "} // end llvm namespace\n";
|
|
|
|
OS << "#endif // GET_INSTRINFO_ENUM\n\n";
|
|
|
|
|
|
|
|
OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n";
|
|
|
|
OS << "#undef GET_INSTRINFO_SCHED_ENUM\n";
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
OS << "namespace " << Namespace << " {\n";
|
2013-09-04 03:43:28 +08:00
|
|
|
OS << "namespace Sched {\n";
|
|
|
|
OS << " enum {\n";
|
2014-04-18 10:09:07 +08:00
|
|
|
Num = 0;
|
|
|
|
for (const auto &Class : SchedModels.explicit_classes())
|
|
|
|
OS << " " << Class.Name << "\t= " << Num++ << ",\n";
|
2016-02-11 15:39:22 +08:00
|
|
|
OS << " SCHED_LIST_END = " << Num << "\n";
|
2014-11-23 17:40:10 +08:00
|
|
|
OS << " };\n";
|
2015-09-11 00:49:58 +08:00
|
|
|
OS << "} // end Sched namespace\n";
|
|
|
|
OS << "} // end " << Namespace << " namespace\n";
|
2016-02-11 15:39:25 +08:00
|
|
|
OS << "} // end llvm namespace\n";
|
2011-06-29 04:07:07 +08:00
|
|
|
|
2017-12-13 15:26:17 +08:00
|
|
|
OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n";
|
2011-06-29 04:07:07 +08:00
|
|
|
}
|
2012-06-11 23:37:55 +08:00
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
|
|
|
|
void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
|
|
|
|
InstrInfoEmitter(RK).run(OS);
|
2012-10-25 23:54:06 +08:00
|
|
|
EmitMapTable(RK, OS);
|
2012-06-11 23:37:55 +08:00
|
|
|
}
|
|
|
|
|
2015-09-11 00:49:58 +08:00
|
|
|
} // end llvm namespace
|