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llvm-project/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll

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Enable FeatureFlatForGlobal on Volcanic Islands This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> llvm-svn: 292982
2017-01-25 06:02:15 +08:00
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
R600/SI: Enable all tests that pass on VI without changes llvm-svn: 227214
2015-01-28 01:27:15 +08:00
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
R600/SI: Add another failing testcase for i1 copies It's not handling phis. llvm-svn: 220371
2014-10-22 13:30:42 +08:00
R600/SI: Move SIFixSGPRCopies to inst selector passes This should expose more of the actually used VALU instructions to the machine optimization passes. This also should help getting i1 handling into a better state. For not entirly understood reasons, this fixes the split-scalar-i64-add.ll test where a 64-bit add would only partially be moved to the VALU resulting in use of undefined VCC. llvm-svn: 222256
2014-11-19 05:06:58 +08:00
; SI-LABEL: {{^}}br_i1_phi:
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
; SI: s_and_saveexec_b64
; SI: s_xor_b64
; SI: v_mov_b32_e32 [[REG]], -1{{$}}
AMDGPU: Use unsigned compare for eq/ne For some reason there are both of these available, except for scalar 64-bit compares which only has u64. I'm not sure why there are both (I'm guessing it's for the one bit inputs we don't use), but for consistency always using the unsigned one. llvm-svn: 282832
2016-09-30 09:50:20 +08:00
; SI: v_cmp_ne_u32_e32 vcc, 0, [[REG]]
R600/SI: Move SIFixSGPRCopies to inst selector passes This should expose more of the actually used VALU instructions to the machine optimization passes. This also should help getting i1 handling into a better state. For not entirly understood reasons, this fixes the split-scalar-i64-add.ll test where a 64-bit add would only partially be moved to the VALU resulting in use of undefined VCC. llvm-svn: 222256
2014-11-19 05:06:58 +08:00
; SI: s_and_saveexec_b64
; SI: s_xor_b64
; SI: s_endpgm
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions Reviewers: arsenm Subscribers: mareko, MatzeB, qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16603 llvm-svn: 260765
2016-02-13 07:45:29 +08:00
define void @br_i1_phi(i32 %arg) {
R600/SI: Add another failing testcase for i1 copies It's not handling phis. llvm-svn: 220371
2014-10-22 13:30:42 +08:00
bb:
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions Reviewers: arsenm Subscribers: mareko, MatzeB, qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16603 llvm-svn: 260765
2016-02-13 07:45:29 +08:00
%tidig = call i32 @llvm.r600.read.tidig.x() #0
%cmp = trunc i32 %tidig to i1
br i1 %cmp, label %bb2, label %bb3
R600/SI: Add another failing testcase for i1 copies It's not handling phis. llvm-svn: 220371
2014-10-22 13:30:42 +08:00
bb2: ; preds = %bb
br label %bb3
bb3: ; preds = %bb2, %bb
%tmp = phi i1 [ true, %bb2 ], [ false, %bb ]
br i1 %tmp, label %bb4, label %bb6
bb4: ; preds = %bb3
AMDGPU: Fix a few slightly broken tests Fix minor bugs and uses of undef which break when pointer related optimization passes are run. llvm-svn: 269944
2016-05-18 23:48:44 +08:00
%val = load volatile i32, i32 addrspace(1)* undef
%tmp5 = mul i32 %val, %arg
R600/SI: Add another failing testcase for i1 copies It's not handling phis. llvm-svn: 220371
2014-10-22 13:30:42 +08:00
br label %bb6
bb6: ; preds = %bb4, %bb3
ret void
}
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions Reviewers: arsenm Subscribers: mareko, MatzeB, qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16603 llvm-svn: 260765
2016-02-13 07:45:29 +08:00
declare i32 @llvm.r600.read.tidig.x() #0
attributes #0 = { readnone }