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llvm-project/llvm/test/CodeGen/X86/vector-shift-ashr-128.ll

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Make utils/update_llc_test_checks.py note that the assertions are autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917
2015-11-24 05:33:58 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][SSE] shift/rotate tests - remove unnecessary mcpu arguments and regenerate/cleanup llvm-svn: 251232
2015-10-25 20:07:45 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX2
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512DQ
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL --check-prefix=AVX512DQVL
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL --check-prefix=AVX512BWVL
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
; Just one 32-bit run to make sure we do reasonable things for i64 shifts.
[X86][SSE] shift/rotate tests - remove unnecessary mcpu arguments and regenerate/cleanup llvm-svn: 251232
2015-10-25 20:07:45 +08:00
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=X32-SSE --check-prefix=X32-SSE2
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
;
; Variable Shifts
;
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: var_shift_v2i64:
; SSE2: # BB#0:
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: psrlq %xmm3, %xmm4
; SSE2-NEXT: psrlq %xmm1, %xmm2
; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm2[0],xmm4[1]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psrlq %xmm3, %xmm2
; SSE2-NEXT: psrlq %xmm1, %xmm0
; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
; SSE2-NEXT: xorpd %xmm4, %xmm2
; SSE2-NEXT: psubq %xmm4, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: movdqa %xmm2, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: var_shift_v2i64:
; SSE41: # BB#0:
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psrlq %xmm1, %xmm3
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,0,1]
; SSE41-NEXT: psrlq %xmm4, %xmm2
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: psrlq %xmm1, %xmm3
; SSE41-NEXT: psrlq %xmm4, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]
; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: psubq %xmm2, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; AVX1-LABEL: var_shift_v2i64:
; AVX1: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; AVX1-NEXT: vpsrlq %xmm1, %xmm2, %xmm3
; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm1[2,3,0,1]
; AVX1-NEXT: vpsrlq %xmm4, %xmm2, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm1
; AVX1-NEXT: vpsrlq %xmm4, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpsubq %xmm2, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: var_shift_v2i64:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpsrlvq %xmm1, %xmm2, %xmm3
; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsubq %xmm3, %xmm0, %xmm0
; AVX2-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: var_shift_v2i64:
; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOP-NEXT: vpsubq %xmm1, %xmm2, %xmm1
; XOP-NEXT: vpshaq %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: var_shift_v2i64:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
[X86][AVX512] Add support for variable ASHR v2i64/v4i64 support without VLX Use v8i64 variable ASHR instructions if we don't have VLX. This is a reduced version of D28537 that just adds support for variable shifts - I'll continue with that patch (for just constant/uniform shifts) once I've fixed the type legalization issue in avx512-cvt.ll. Differential Revision: https://reviews.llvm.org/D28604 llvm-svn: 291901
2017-01-13 21:16:19 +08:00
; AVX512-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def>
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512-NEXT: vpsravq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512-NEXT: vzeroupper
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: var_shift_v2i64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpsravq %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: var_shift_v2i64:
; X32-SSE: # BB#0:
[X86] Optimize vector shifts with variable but uniform shift amounts Summary: For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register. The lower 64-bits of the register are evaluated to determine the shift amount. This patch improves the construction of the vector containing the shift amount. Reviewers: craig.topper, delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28353 llvm-svn: 291120
2017-01-05 23:11:43 +08:00
; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648]
; X32-SSE-NEXT: movdqa %xmm2, %xmm4
; X32-SSE-NEXT: psrlq %xmm3, %xmm4
; X32-SSE-NEXT: psrlq %xmm1, %xmm2
; X32-SSE-NEXT: movsd {{.*#+}} xmm4 = xmm2[0],xmm4[1]
; X32-SSE-NEXT: movdqa %xmm0, %xmm2
; X32-SSE-NEXT: psrlq %xmm3, %xmm2
; X32-SSE-NEXT: psrlq %xmm1, %xmm0
; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
; X32-SSE-NEXT: xorpd %xmm4, %xmm2
; X32-SSE-NEXT: psubq %xmm4, %xmm2
; X32-SSE-NEXT: movdqa %xmm2, %xmm0
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <2 x i64> %a, %b
ret <2 x i64> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: var_shift_v4i32:
; SSE2: # BB#0:
[X86][SSE] Vectorized v4i32 non-uniform shifts. While the v4i32 shl operation is already vectorized using a cvttps2dq/pmulld pattern, the lshr/ashr opeations are still scalarized. This patch adds vectorization support for non-uniform v4i32 shift operations - it splats constant shift amounts to allow them to use the immediate sse shift instructions, or extracts/zero-extends non-constant shift amounts. The individual results are then blended together. Differential Revision: http://reviews.llvm.org/D11063 llvm-svn: 241989
2015-07-12 19:15:19 +08:00
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrad %xmm2, %xmm3
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrlq $32, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: psrad %xmm2, %xmm4
; SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm4[0],xmm3[1]
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3]
; SSE2-NEXT: pxor %xmm3, %xmm3
; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm3[2],xmm4[3],xmm3[3]
; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: psrad %xmm4, %xmm5
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; SSE2-NEXT: psrad %xmm1, %xmm0
; SSE2-NEXT: movsd {{.*#+}} xmm5 = xmm0[0],xmm5[1]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm5[0,2,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: var_shift_v4i32:
; SSE41: # BB#0:
[X86][SSE] Vectorized v4i32 non-uniform shifts. While the v4i32 shl operation is already vectorized using a cvttps2dq/pmulld pattern, the lshr/ashr opeations are still scalarized. This patch adds vectorization support for non-uniform v4i32 shift operations - it splats constant shift amounts to allow them to use the immediate sse shift instructions, or extracts/zero-extends non-constant shift amounts. The individual results are then blended together. Differential Revision: http://reviews.llvm.org/D11063 llvm-svn: 241989
2015-07-12 19:15:19 +08:00
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: psrad %xmm2, %xmm3
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrlq $32, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm4
; SSE41-NEXT: psrad %xmm2, %xmm4
; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm3[4,5,6,7]
; SSE41-NEXT: pxor %xmm2, %xmm2
; SSE41-NEXT: pmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero
; SSE41-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: psrad %xmm1, %xmm2
; SSE41-NEXT: psrad %xmm3, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3],xmm0[4,5],xmm4[6,7]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
; AVX1-LABEL: var_shift_v4i32:
; AVX1: # BB#0:
[X86][SSE] Vectorized v4i32 non-uniform shifts. While the v4i32 shl operation is already vectorized using a cvttps2dq/pmulld pattern, the lshr/ashr opeations are still scalarized. This patch adds vectorization support for non-uniform v4i32 shift operations - it splats constant shift amounts to allow them to use the immediate sse shift instructions, or extracts/zero-extends non-constant shift amounts. The individual results are then blended together. Differential Revision: http://reviews.llvm.org/D11063 llvm-svn: 241989
2015-07-12 19:15:19 +08:00
; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: vpsrad %xmm2, %xmm0, %xmm2
; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
; AVX1-NEXT: vpsrad %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
; AVX1-NEXT: vpsrad %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX1-NEXT: retq
;
; AVX2-LABEL: var_shift_v4i32:
; AVX2: # BB#0:
; AVX2-NEXT: vpsravd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOPAVX1-LABEL: var_shift_v4i32:
; XOPAVX1: # BB#0:
; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOPAVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm1
; XOPAVX1-NEXT: vpshad %xmm1, %xmm0, %xmm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: var_shift_v4i32:
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpsravd %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: var_shift_v4i32:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: vpsravd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: var_shift_v4i32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpsravd %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: var_shift_v4i32:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
; X32-SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; X32-SSE-NEXT: movdqa %xmm0, %xmm3
; X32-SSE-NEXT: psrad %xmm2, %xmm3
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
; X32-SSE-NEXT: psrlq $32, %xmm2
; X32-SSE-NEXT: movdqa %xmm0, %xmm4
; X32-SSE-NEXT: psrad %xmm2, %xmm4
; X32-SSE-NEXT: movsd {{.*#+}} xmm3 = xmm4[0],xmm3[1]
; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3]
; X32-SSE-NEXT: pxor %xmm3, %xmm3
; X32-SSE-NEXT: movdqa %xmm1, %xmm4
; X32-SSE-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm3[2],xmm4[3],xmm3[3]
; X32-SSE-NEXT: movdqa %xmm0, %xmm5
; X32-SSE-NEXT: psrad %xmm4, %xmm5
; X32-SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; X32-SSE-NEXT: psrad %xmm1, %xmm0
; X32-SSE-NEXT: movsd {{.*#+}} xmm5 = xmm0[0],xmm5[1]
; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm5[0,2,2,3]
; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <4 x i32> %a, %b
ret <4 x i32> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: var_shift_v8i16:
; SSE2: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: psllw $12, %xmm1
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: movdqa %xmm1, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: psraw $15, %xmm2
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: movdqa %xmm2, %xmm3
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: pandn %xmm0, %xmm3
; SSE2-NEXT: psraw $8, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: paddw %xmm1, %xmm1
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: movdqa %xmm1, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: psraw $15, %xmm2
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: movdqa %xmm2, %xmm3
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: pandn %xmm0, %xmm3
; SSE2-NEXT: psraw $4, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: paddw %xmm1, %xmm1
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: movdqa %xmm1, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: psraw $15, %xmm2
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: movdqa %xmm2, %xmm3
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: pandn %xmm0, %xmm3
; SSE2-NEXT: psraw $2, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: paddw %xmm1, %xmm1
; SSE2-NEXT: psraw $15, %xmm1
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: movdqa %xmm1, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: psraw $1, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: var_shift_v8i16:
; SSE41: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: psllw $12, %xmm0
; SSE41-NEXT: psllw $4, %xmm1
; SSE41-NEXT: por %xmm0, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm3
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"" This crashes on boringSSL on PPC (will send reduced testcase) This reverts commit r312328. llvm-svn: 312490
2017-09-04 23:47:00 +08:00
; SSE41-NEXT: paddw %xmm3, %xmm3
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: psraw $8, %xmm4
; SSE41-NEXT: movdqa %xmm1, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm2, %xmm1
; SSE41-NEXT: psraw $4, %xmm1
; SSE41-NEXT: movdqa %xmm3, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm2, %xmm1
; SSE41-NEXT: psraw $2, %xmm1
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm2, %xmm1
; SSE41-NEXT: psraw $1, %xmm1
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm2, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
; AVX1-LABEL: var_shift_v8i16:
; AVX1: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2
; AVX1-NEXT: vpsraw $8, %xmm0, %xmm3
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX1-NEXT: vpsraw $4, %xmm0, %xmm1
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX1-NEXT: vpsraw $2, %xmm0, %xmm1
; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX1-NEXT: vpsraw $1, %xmm0, %xmm1
; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: var_shift_v8i16:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0
[X86] In LowerTRUNCATE, create an ISD::VECTOR_SHUFFLE instead of explicitly creating a PSHUFB. This will be lowered by regular shuffle lowering to a PSHUFB later. Similar was already done for several other shuffles in this function. The test changes are because the old code used explicity zeroing for elements that could have been undef. While I was here I also changed other shuffle vectors in the same function to use the same input twice instead of creating UNDEF nodes. getVectorShuffle can create the UNDEF for us. llvm-svn: 294130
2017-02-06 02:33:14 +08:00
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
VirtRegMap: Replace some identity copies with KILL instructions. An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
2016-07-09 08:19:07 +08:00
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: var_shift_v8i16:
; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOP-NEXT: vpsubw %xmm1, %xmm2, %xmm1
; XOP-NEXT: vpshaw %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
;
[X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift tests llvm-svn: 291444
2017-01-09 22:36:09 +08:00
; AVX512DQ-LABEL: var_shift_v8i16:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX512DQ-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX512DQ-NEXT: vpsravd %ymm1, %ymm0, %ymm0
; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512DQ-NEXT: vzeroupper
[X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift tests llvm-svn: 291444
2017-01-09 22:36:09 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512BW-LABEL: var_shift_v8i16:
; AVX512BW: # BB#0:
; AVX512BW-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def>
; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512BW-NEXT: vzeroupper
[X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift tests llvm-svn: 291444
2017-01-09 22:36:09 +08:00
; AVX512BW-NEXT: retq
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512DQVL-LABEL: var_shift_v8i16:
; AVX512DQVL: # BB#0:
; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX512DQVL-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX512DQVL-NEXT: vpsravd %ymm1, %ymm0, %ymm0
; AVX512DQVL-NEXT: vpmovdw %ymm0, %xmm0
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512DQVL-NEXT: vzeroupper
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512DQVL-NEXT: retq
;
; AVX512BWVL-LABEL: var_shift_v8i16:
; AVX512BWVL: # BB#0:
; AVX512BWVL-NEXT: vpsravw %xmm1, %xmm0, %xmm0
; AVX512BWVL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: var_shift_v8i16:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: psllw $12, %xmm1
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
; X32-SSE-NEXT: psraw $15, %xmm2
; X32-SSE-NEXT: movdqa %xmm2, %xmm3
; X32-SSE-NEXT: pandn %xmm0, %xmm3
; X32-SSE-NEXT: psraw $8, %xmm0
; X32-SSE-NEXT: pand %xmm2, %xmm0
; X32-SSE-NEXT: por %xmm3, %xmm0
; X32-SSE-NEXT: paddw %xmm1, %xmm1
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
; X32-SSE-NEXT: psraw $15, %xmm2
; X32-SSE-NEXT: movdqa %xmm2, %xmm3
; X32-SSE-NEXT: pandn %xmm0, %xmm3
; X32-SSE-NEXT: psraw $4, %xmm0
; X32-SSE-NEXT: pand %xmm2, %xmm0
; X32-SSE-NEXT: por %xmm3, %xmm0
; X32-SSE-NEXT: paddw %xmm1, %xmm1
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
; X32-SSE-NEXT: psraw $15, %xmm2
; X32-SSE-NEXT: movdqa %xmm2, %xmm3
; X32-SSE-NEXT: pandn %xmm0, %xmm3
; X32-SSE-NEXT: psraw $2, %xmm0
; X32-SSE-NEXT: pand %xmm2, %xmm0
; X32-SSE-NEXT: por %xmm3, %xmm0
; X32-SSE-NEXT: paddw %xmm1, %xmm1
; X32-SSE-NEXT: psraw $15, %xmm1
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
; X32-SSE-NEXT: pandn %xmm0, %xmm2
; X32-SSE-NEXT: psraw $1, %xmm0
; X32-SSE-NEXT: pand %xmm1, %xmm0
; X32-SSE-NEXT: por %xmm2, %xmm0
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <8 x i16> %a, %b
ret <8 x i16> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: var_shift_v16i8:
; SSE2: # BB#0:
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: psllw $5, %xmm1
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm1[8],xmm4[9],xmm1[9],xmm4[10],xmm1[10],xmm4[11],xmm1[11],xmm4[12],xmm1[12],xmm4[13],xmm1[13],xmm4[14],xmm1[14],xmm4[15],xmm1[15]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: pxor %xmm3, %xmm3
; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtw %xmm4, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pandn %xmm2, %xmm6
; SSE2-NEXT: psraw $4, %xmm2
; SSE2-NEXT: pand %xmm5, %xmm2
; SSE2-NEXT: por %xmm6, %xmm2
; SSE2-NEXT: paddw %xmm4, %xmm4
; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtw %xmm4, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pandn %xmm2, %xmm6
; SSE2-NEXT: psraw $2, %xmm2
; SSE2-NEXT: pand %xmm5, %xmm2
; SSE2-NEXT: por %xmm6, %xmm2
; SSE2-NEXT: paddw %xmm4, %xmm4
; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtw %xmm4, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm4
; SSE2-NEXT: pandn %xmm2, %xmm4
; SSE2-NEXT: psraw $1, %xmm2
; SSE2-NEXT: pand %xmm5, %xmm2
; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: psrlw $8, %xmm2
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpgtw %xmm1, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: pandn %xmm0, %xmm5
; SSE2-NEXT: psraw $4, %xmm0
; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: paddw %xmm1, %xmm1
; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpgtw %xmm1, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: pandn %xmm0, %xmm5
; SSE2-NEXT: psraw $2, %xmm0
; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: paddw %xmm1, %xmm1
; SSE2-NEXT: pcmpgtw %xmm1, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm1
; SSE2-NEXT: pandn %xmm0, %xmm1
; SSE2-NEXT: psraw $1, %xmm0
; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: var_shift_v16i8:
; SSE41: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: psllw $5, %xmm1
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; SSE41-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm3, %xmm4
; SSE41-NEXT: psraw $4, %xmm4
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm3
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm3, %xmm4
; SSE41-NEXT: psraw $2, %xmm4
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm3
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm3, %xmm4
; SSE41-NEXT: psraw $1, %xmm4
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm3
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: psrlw $8, %xmm3
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE41-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $4, %xmm2
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $2, %xmm2
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $1, %xmm2
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: psrlw $8, %xmm1
; SSE41-NEXT: packuswb %xmm3, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
; AVX-LABEL: var_shift_v16i8:
; AVX: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX-NEXT: vpsllw $5, %xmm1, %xmm1
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; AVX-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX-NEXT: vpsraw $4, %xmm3, %xmm4
; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3
; AVX-NEXT: vpsraw $2, %xmm3, %xmm4
; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2
; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3
; AVX-NEXT: vpsraw $1, %xmm3, %xmm4
; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2
; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm2
; AVX-NEXT: vpsrlw $8, %xmm2, %xmm2
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX-NEXT: vpsraw $4, %xmm0, %xmm3
; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX-NEXT: vpsraw $2, %xmm0, %xmm3
; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm1
; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX-NEXT: vpsraw $1, %xmm0, %xmm3
; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm1
; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX-NEXT: vpsrlw $8, %xmm0, %xmm0
; AVX-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: var_shift_v16i8:
; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOP-NEXT: vpsubb %xmm1, %xmm2, %xmm1
; XOP-NEXT: vpshab %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: var_shift_v16i8:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
[X86][AVX512] Enable v16i8/v32i8 vector shifts to use an extend+shift+truncate pattern. Use the existing AVX2 v8i16 vector shift lowering for v16i8 (extending to v16i32) on AVX512 targets and v32i8 (extending to v32i16) on AVX512BW targets. Cost model updates to follow. llvm-svn: 291451
2017-01-10 01:20:03 +08:00
; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512-NEXT: vpsravd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpmovdb %zmm0, %xmm0
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512-NEXT: vzeroupper
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: var_shift_v16i8:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
; AVX512VL-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512VL-NEXT: vpsravd %zmm1, %zmm0, %zmm0
; AVX512VL-NEXT: vpmovdb %zmm0, %xmm0
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512VL-NEXT: vzeroupper
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: var_shift_v16i8:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
; X32-SSE-NEXT: psllw $5, %xmm1
; X32-SSE-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm1[8],xmm4[9],xmm1[9],xmm4[10],xmm1[10],xmm4[11],xmm1[11],xmm4[12],xmm1[12],xmm4[13],xmm1[13],xmm4[14],xmm1[14],xmm4[15],xmm1[15]
; X32-SSE-NEXT: pxor %xmm3, %xmm3
; X32-SSE-NEXT: pxor %xmm5, %xmm5
; X32-SSE-NEXT: pcmpgtw %xmm4, %xmm5
; X32-SSE-NEXT: movdqa %xmm5, %xmm6
; X32-SSE-NEXT: pandn %xmm2, %xmm6
; X32-SSE-NEXT: psraw $4, %xmm2
; X32-SSE-NEXT: pand %xmm5, %xmm2
; X32-SSE-NEXT: por %xmm6, %xmm2
; X32-SSE-NEXT: paddw %xmm4, %xmm4
; X32-SSE-NEXT: pxor %xmm5, %xmm5
; X32-SSE-NEXT: pcmpgtw %xmm4, %xmm5
; X32-SSE-NEXT: movdqa %xmm5, %xmm6
; X32-SSE-NEXT: pandn %xmm2, %xmm6
; X32-SSE-NEXT: psraw $2, %xmm2
; X32-SSE-NEXT: pand %xmm5, %xmm2
; X32-SSE-NEXT: por %xmm6, %xmm2
; X32-SSE-NEXT: paddw %xmm4, %xmm4
; X32-SSE-NEXT: pxor %xmm5, %xmm5
; X32-SSE-NEXT: pcmpgtw %xmm4, %xmm5
; X32-SSE-NEXT: movdqa %xmm5, %xmm4
; X32-SSE-NEXT: pandn %xmm2, %xmm4
; X32-SSE-NEXT: psraw $1, %xmm2
; X32-SSE-NEXT: pand %xmm5, %xmm2
; X32-SSE-NEXT: por %xmm4, %xmm2
; X32-SSE-NEXT: psrlw $8, %xmm2
; X32-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X32-SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pcmpgtw %xmm1, %xmm4
; X32-SSE-NEXT: movdqa %xmm4, %xmm5
; X32-SSE-NEXT: pandn %xmm0, %xmm5
; X32-SSE-NEXT: psraw $4, %xmm0
; X32-SSE-NEXT: pand %xmm4, %xmm0
; X32-SSE-NEXT: por %xmm5, %xmm0
; X32-SSE-NEXT: paddw %xmm1, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pcmpgtw %xmm1, %xmm4
; X32-SSE-NEXT: movdqa %xmm4, %xmm5
; X32-SSE-NEXT: pandn %xmm0, %xmm5
; X32-SSE-NEXT: psraw $2, %xmm0
; X32-SSE-NEXT: pand %xmm4, %xmm0
; X32-SSE-NEXT: por %xmm5, %xmm0
; X32-SSE-NEXT: paddw %xmm1, %xmm1
; X32-SSE-NEXT: pcmpgtw %xmm1, %xmm3
; X32-SSE-NEXT: movdqa %xmm3, %xmm1
; X32-SSE-NEXT: pandn %xmm0, %xmm1
; X32-SSE-NEXT: psraw $1, %xmm0
; X32-SSE-NEXT: pand %xmm3, %xmm0
; X32-SSE-NEXT: por %xmm1, %xmm0
; X32-SSE-NEXT: psrlw $8, %xmm0
; X32-SSE-NEXT: packuswb %xmm2, %xmm0
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <16 x i8> %a, %b
ret <16 x i8> %shift
}
;
; Uniform Variable Shifts
;
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; SSE-LABEL: splatvar_shift_v2i64:
; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; SSE-NEXT: psrlq %xmm1, %xmm2
; SSE-NEXT: psrlq %xmm1, %xmm0
; SSE-NEXT: pxor %xmm2, %xmm0
; SSE-NEXT: psubq %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: splatvar_shift_v2i64:
; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; AVX-NEXT: vpsrlq %xmm1, %xmm2, %xmm2
; AVX-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; AVX-NEXT: vpsubq %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOPAVX1-LABEL: splatvar_shift_v2i64:
; XOPAVX1: # BB#0:
; XOPAVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOPAVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm1
; XOPAVX1-NEXT: vpshaq %xmm1, %xmm0, %xmm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: splatvar_shift_v2i64:
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpbroadcastq %xmm1, %xmm1
; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOPAVX2-NEXT: vpsubq %xmm1, %xmm2, %xmm1
; XOPAVX2-NEXT: vpshaq %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: splatvar_shift_v2i64:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
[X86][AVX512] Add support for variable ASHR v2i64/v4i64 support without VLX Use v8i64 variable ASHR instructions if we don't have VLX. This is a reduced version of D28537 that just adds support for variable shifts - I'll continue with that patch (for just constant/uniform shifts) once I've fixed the type legalization issue in avx512-cvt.ll. Differential Revision: https://reviews.llvm.org/D28604 llvm-svn: 291901
2017-01-13 21:16:19 +08:00
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
[X86][AVX512] Add support for ASHR v2i64/v4i64 support without VLX Use v8i64 ASHR instructions if we don't have VLX. Differential Revision: https://reviews.llvm.org/D28537 llvm-svn: 295656
2017-02-20 20:16:38 +08:00
; AVX512-NEXT: vpsraq %xmm1, %zmm0, %zmm0
[X86][AVX512] Add support for variable ASHR v2i64/v4i64 support without VLX Use v8i64 variable ASHR instructions if we don't have VLX. This is a reduced version of D28537 that just adds support for variable shifts - I'll continue with that patch (for just constant/uniform shifts) once I've fixed the type legalization issue in avx512-cvt.ll. Differential Revision: https://reviews.llvm.org/D28604 llvm-svn: 291901
2017-01-13 21:16:19 +08:00
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512-NEXT: vzeroupper
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: splatvar_shift_v2i64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpsraq %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: splatvar_shift_v2i64:
; X32-SSE: # BB#0:
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648]
; X32-SSE-NEXT: psrlq %xmm1, %xmm2
; X32-SSE-NEXT: psrlq %xmm1, %xmm0
; X32-SSE-NEXT: pxor %xmm2, %xmm0
; X32-SSE-NEXT: psubq %xmm2, %xmm0
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer
%shift = ashr <2 x i64> %a, %splat
ret <2 x i64> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: splatvar_shift_v4i32:
; SSE2: # BB#0:
; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; SSE2-NEXT: psrad %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: splatvar_shift_v4i32:
; SSE41: # BB#0:
[X86] Optimize vector shifts with variable but uniform shift amounts Summary: For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register. The lower 64-bits of the register are evaluated to determine the shift amount. This patch improves the construction of the vector containing the shift amount. Reviewers: craig.topper, delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28353 llvm-svn: 291120
2017-01-05 23:11:43 +08:00
; SSE41-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; SSE41-NEXT: psrad %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
; AVX-LABEL: splatvar_shift_v4i32:
; AVX: # BB#0:
[X86] Optimize vector shifts with variable but uniform shift amounts Summary: For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register. The lower 64-bits of the register are evaluated to determine the shift amount. This patch improves the construction of the vector containing the shift amount. Reviewers: craig.topper, delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28353 llvm-svn: 291120
2017-01-05 23:11:43 +08:00
; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: splatvar_shift_v4i32:
; XOP: # BB#0:
[X86] Optimize vector shifts with variable but uniform shift amounts Summary: For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register. The lower 64-bits of the register are evaluated to determine the shift amount. This patch improves the construction of the vector containing the shift amount. Reviewers: craig.topper, delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28353 llvm-svn: 291120
2017-01-05 23:11:43 +08:00
; XOP-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: splatvar_shift_v4i32:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
[X86] Optimize vector shifts with variable but uniform shift amounts Summary: For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register. The lower 64-bits of the register are evaluated to determine the shift amount. This patch improves the construction of the vector containing the shift amount. Reviewers: craig.topper, delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28353 llvm-svn: 291120
2017-01-05 23:11:43 +08:00
; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: splatvar_shift_v4i32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX512VL-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: splatvar_shift_v4i32:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: xorps %xmm2, %xmm2
; X32-SSE-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; X32-SSE-NEXT: psrad %xmm2, %xmm0
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
%shift = ashr <4 x i32> %a, %splat
ret <4 x i32> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: splatvar_shift_v8i16:
; SSE2: # BB#0:
[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW. But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register. This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41). Fix for PR27265. Differential Revision: https://reviews.llvm.org/D22509 llvm-svn: 276289
2016-07-21 22:54:17 +08:00
; SSE2-NEXT: pextrw $0, %xmm1, %eax
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: psraw %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: splatvar_shift_v8i16:
; SSE41: # BB#0:
[X86] Optimize vector shifts with variable but uniform shift amounts Summary: For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register. The lower 64-bits of the register are evaluated to determine the shift amount. This patch improves the construction of the vector containing the shift amount. Reviewers: craig.topper, delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28353 llvm-svn: 291120
2017-01-05 23:11:43 +08:00
; SSE41-NEXT: pmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; SSE41-NEXT: psraw %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
; AVX-LABEL: splatvar_shift_v8i16:
; AVX: # BB#0:
[X86] Optimize vector shifts with variable but uniform shift amounts Summary: For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register. The lower 64-bits of the register are evaluated to determine the shift amount. This patch improves the construction of the vector containing the shift amount. Reviewers: craig.topper, delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28353 llvm-svn: 291120
2017-01-05 23:11:43 +08:00
; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: splatvar_shift_v8i16:
; XOP: # BB#0:
[X86] Optimize vector shifts with variable but uniform shift amounts Summary: For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register. The lower 64-bits of the register are evaluated to determine the shift amount. This patch improves the construction of the vector containing the shift amount. Reviewers: craig.topper, delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28353 llvm-svn: 291120
2017-01-05 23:11:43 +08:00
; XOP-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-NEXT: vpsraw %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: splatvar_shift_v8i16:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
[X86] Optimize vector shifts with variable but uniform shift amounts Summary: For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register. The lower 64-bits of the register are evaluated to determine the shift amount. This patch improves the construction of the vector containing the shift amount. Reviewers: craig.topper, delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28353 llvm-svn: 291120
2017-01-05 23:11:43 +08:00
; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: vpsraw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: splatvar_shift_v8i16:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512VL-NEXT: vpsraw %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: splatvar_shift_v8i16:
; X32-SSE: # BB#0:
[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW. But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register. This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41). Fix for PR27265. Differential Revision: https://reviews.llvm.org/D22509 llvm-svn: 276289
2016-07-21 22:54:17 +08:00
; X32-SSE-NEXT: pextrw $0, %xmm1, %eax
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-NEXT: movd %eax, %xmm1
; X32-SSE-NEXT: psraw %xmm1, %xmm0
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%splat = shufflevector <8 x i16> %b, <8 x i16> undef, <8 x i32> zeroinitializer
%shift = ashr <8 x i16> %a, %splat
ret <8 x i16> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: splatvar_shift_v16i8:
; SSE2: # BB#0:
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
[X86][SSE] Improve i16 splatting shuffles Better handling of the annoying pshuflw/pshufhw ops which only shuffle lower/upper halves of a vector. Added vXi16 unary shuffle support for cases where i16 elements (from the same half of the source) are being splatted to the whole of one of the halves. This avoids the general lowering case which must shuffle the 32-bit elements first - meaning that we used to end up with unnecessary duplicate pshuflw/pshufhw shuffles. Note this has the side effect of a lot of SSSE3 test cases no longer needing to use PSHUFB, as it falls below the 3 op combine threshold for when PSHUFB is typically worth it. I've raised PR26183 to discuss if the threshold should be changed and whether we need to make it more specific to the target CPU. Differential Revision: http://reviews.llvm.org/D14901 llvm-svn: 258440
2016-01-22 06:07:41 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[0,0,1,1]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: psllw $5, %xmm3
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtw %xmm4, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pandn %xmm1, %xmm6
; SSE2-NEXT: psraw $4, %xmm1
; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1
; SSE2-NEXT: paddw %xmm4, %xmm4
; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtw %xmm4, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pandn %xmm1, %xmm6
; SSE2-NEXT: psraw $2, %xmm1
; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1
; SSE2-NEXT: paddw %xmm4, %xmm4
; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtw %xmm4, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm4
; SSE2-NEXT: pandn %xmm1, %xmm4
; SSE2-NEXT: psraw $1, %xmm1
; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: psrlw $8, %xmm1
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpgtw %xmm3, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: pandn %xmm0, %xmm5
; SSE2-NEXT: psraw $4, %xmm0
; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: paddw %xmm3, %xmm3
; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpgtw %xmm3, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: pandn %xmm0, %xmm5
; SSE2-NEXT: psraw $2, %xmm0
; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: paddw %xmm3, %xmm3
; SSE2-NEXT: pcmpgtw %xmm3, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: pandn %xmm0, %xmm3
; SSE2-NEXT: psraw $1, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: packuswb %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: splatvar_shift_v16i8:
; SSE41: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: pshufb %xmm0, %xmm1
; SSE41-NEXT: psllw $5, %xmm1
; SSE41-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; SSE41-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
; SSE41-NEXT: movdqa %xmm3, %xmm4
; SSE41-NEXT: psraw $4, %xmm4
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm3
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm3, %xmm4
; SSE41-NEXT: psraw $2, %xmm4
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm3
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm3, %xmm4
; SSE41-NEXT: psraw $1, %xmm4
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm3
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: psrlw $8, %xmm3
; SSE41-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE41-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $4, %xmm2
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $2, %xmm2
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $1, %xmm2
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: psrlw $8, %xmm1
; SSE41-NEXT: packuswb %xmm3, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
; AVX1-LABEL: splatvar_shift_v16i8:
; AVX1: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX1-NEXT: vpsraw $4, %xmm3, %xmm4
; AVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpsraw $2, %xmm3, %xmm4
; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpsraw $1, %xmm3, %xmm4
; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX1-NEXT: vpsraw $4, %xmm0, %xmm3
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpsraw $2, %xmm0, %xmm3
; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpsraw $1, %xmm0, %xmm3
; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX1-NEXT: retq
;
; AVX2-LABEL: splatvar_shift_v16i8:
; AVX2: # BB#0:
; AVX2-NEXT: vpbroadcastb %xmm1, %xmm1
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX2-NEXT: vpsllw $5, %xmm1, %xmm1
; AVX2-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; AVX2-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX2-NEXT: vpsraw $4, %xmm3, %xmm4
; AVX2-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vpsraw $2, %xmm3, %xmm4
; AVX2-NEXT: vpaddw %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vpsraw $1, %xmm3, %xmm4
; AVX2-NEXT: vpaddw %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm2
; AVX2-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; AVX2-NEXT: vpsraw $4, %xmm0, %xmm3
; AVX2-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX2-NEXT: vpsraw $2, %xmm0, %xmm3
; AVX2-NEXT: vpaddw %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX2-NEXT: vpsraw $1, %xmm0, %xmm3
; AVX2-NEXT: vpaddw %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0
; AVX2-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX2-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOPAVX1-LABEL: splatvar_shift_v16i8:
; XOPAVX1: # BB#0:
; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOPAVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; XOPAVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1
; XOPAVX1-NEXT: vpshab %xmm1, %xmm0, %xmm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: splatvar_shift_v16i8:
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpbroadcastb %xmm1, %xmm1
; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOPAVX2-NEXT: vpsubb %xmm1, %xmm2, %xmm1
; XOPAVX2-NEXT: vpshab %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: splatvar_shift_v16i8:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: vpbroadcastb %xmm1, %xmm1
[X86][AVX512] Enable v16i8/v32i8 vector shifts to use an extend+shift+truncate pattern. Use the existing AVX2 v8i16 vector shift lowering for v16i8 (extending to v16i32) on AVX512 targets and v32i8 (extending to v32i16) on AVX512BW targets. Cost model updates to follow. llvm-svn: 291451
2017-01-10 01:20:03 +08:00
; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
; AVX512-NEXT: vpsravd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpmovdb %zmm0, %xmm0
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512-NEXT: vzeroupper
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: splatvar_shift_v16i8:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpbroadcastb %xmm1, %xmm1
; AVX512VL-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512VL-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
; AVX512VL-NEXT: vpsravd %zmm1, %zmm0, %zmm0
; AVX512VL-NEXT: vpmovdb %zmm0, %xmm0
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512VL-NEXT: vzeroupper
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: splatvar_shift_v16i8:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X32-SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
[X86][SSE] Improve i16 splatting shuffles Better handling of the annoying pshuflw/pshufhw ops which only shuffle lower/upper halves of a vector. Added vXi16 unary shuffle support for cases where i16 elements (from the same half of the source) are being splatted to the whole of one of the halves. This avoids the general lowering case which must shuffle the 32-bit elements first - meaning that we used to end up with unnecessary duplicate pshuflw/pshufhw shuffles. Note this has the side effect of a lot of SSSE3 test cases no longer needing to use PSHUFB, as it falls below the 3 op combine threshold for when PSHUFB is typically worth it. I've raised PR26183 to discuss if the threshold should be changed and whether we need to make it more specific to the target CPU. Differential Revision: http://reviews.llvm.org/D14901 llvm-svn: 258440
2016-01-22 06:07:41 +08:00
; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[0,0,1,1]
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
; X32-SSE-NEXT: psllw $5, %xmm3
; X32-SSE-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15]
; X32-SSE-NEXT: pxor %xmm2, %xmm2
; X32-SSE-NEXT: pxor %xmm5, %xmm5
; X32-SSE-NEXT: pcmpgtw %xmm4, %xmm5
; X32-SSE-NEXT: movdqa %xmm5, %xmm6
; X32-SSE-NEXT: pandn %xmm1, %xmm6
; X32-SSE-NEXT: psraw $4, %xmm1
; X32-SSE-NEXT: pand %xmm5, %xmm1
; X32-SSE-NEXT: por %xmm6, %xmm1
; X32-SSE-NEXT: paddw %xmm4, %xmm4
; X32-SSE-NEXT: pxor %xmm5, %xmm5
; X32-SSE-NEXT: pcmpgtw %xmm4, %xmm5
; X32-SSE-NEXT: movdqa %xmm5, %xmm6
; X32-SSE-NEXT: pandn %xmm1, %xmm6
; X32-SSE-NEXT: psraw $2, %xmm1
; X32-SSE-NEXT: pand %xmm5, %xmm1
; X32-SSE-NEXT: por %xmm6, %xmm1
; X32-SSE-NEXT: paddw %xmm4, %xmm4
; X32-SSE-NEXT: pxor %xmm5, %xmm5
; X32-SSE-NEXT: pcmpgtw %xmm4, %xmm5
; X32-SSE-NEXT: movdqa %xmm5, %xmm4
; X32-SSE-NEXT: pandn %xmm1, %xmm4
; X32-SSE-NEXT: psraw $1, %xmm1
; X32-SSE-NEXT: pand %xmm5, %xmm1
; X32-SSE-NEXT: por %xmm4, %xmm1
; X32-SSE-NEXT: psrlw $8, %xmm1
; X32-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X32-SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pcmpgtw %xmm3, %xmm4
; X32-SSE-NEXT: movdqa %xmm4, %xmm5
; X32-SSE-NEXT: pandn %xmm0, %xmm5
; X32-SSE-NEXT: psraw $4, %xmm0
; X32-SSE-NEXT: pand %xmm4, %xmm0
; X32-SSE-NEXT: por %xmm5, %xmm0
; X32-SSE-NEXT: paddw %xmm3, %xmm3
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pcmpgtw %xmm3, %xmm4
; X32-SSE-NEXT: movdqa %xmm4, %xmm5
; X32-SSE-NEXT: pandn %xmm0, %xmm5
; X32-SSE-NEXT: psraw $2, %xmm0
; X32-SSE-NEXT: pand %xmm4, %xmm0
; X32-SSE-NEXT: por %xmm5, %xmm0
; X32-SSE-NEXT: paddw %xmm3, %xmm3
; X32-SSE-NEXT: pcmpgtw %xmm3, %xmm2
; X32-SSE-NEXT: movdqa %xmm2, %xmm3
; X32-SSE-NEXT: pandn %xmm0, %xmm3
; X32-SSE-NEXT: psraw $1, %xmm0
; X32-SSE-NEXT: pand %xmm2, %xmm0
; X32-SSE-NEXT: por %xmm3, %xmm0
; X32-SSE-NEXT: psrlw $8, %xmm0
; X32-SSE-NEXT: packuswb %xmm1, %xmm0
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%splat = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
%shift = ashr <16 x i8> %a, %splat
ret <16 x i8> %shift
}
;
; Constant Shifts
;
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: constant_shift_v2i64:
; SSE2: # BB#0:
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $7, %xmm1
; SSE2-NEXT: psrlq $1, %xmm0
; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
; SSE2-NEXT: movapd {{.*#+}} xmm0 = [4611686018427387904,72057594037927936]
; SSE2-NEXT: xorpd %xmm0, %xmm1
; SSE2-NEXT: psubq %xmm0, %xmm1
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: movdqa %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: constant_shift_v2i64:
; SSE41: # BB#0:
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrlq $7, %xmm1
; SSE41-NEXT: psrlq $1, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4611686018427387904,72057594037927936]
; SSE41-NEXT: pxor %xmm1, %xmm0
; SSE41-NEXT: psubq %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; AVX1-LABEL: constant_shift_v2i64:
; AVX1: # BB#0:
; AVX1-NEXT: vpsrlq $7, %xmm0, %xmm1
; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [4611686018427387904,72057594037927936]
; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: constant_shift_v2i64:
; AVX2: # BB#0:
; AVX2-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [4611686018427387904,72057594037927936]
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: constant_shift_v2i64:
; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm1, %xmm1, %xmm1
; XOP-NEXT: vpsubq {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpshaq %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: constant_shift_v2i64:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
[X86][AVX512] Add support for variable ASHR v2i64/v4i64 support without VLX Use v8i64 variable ASHR instructions if we don't have VLX. This is a reduced version of D28537 that just adds support for variable shifts - I'll continue with that patch (for just constant/uniform shifts) once I've fixed the type legalization issue in avx512-cvt.ll. Differential Revision: https://reviews.llvm.org/D28604 llvm-svn: 291901
2017-01-13 21:16:19 +08:00
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512-NEXT: vmovdqa {{.*#+}} xmm1 = [1,7]
; AVX512-NEXT: vpsravq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512-NEXT: vzeroupper
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: constant_shift_v2i64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpsravq {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: constant_shift_v2i64:
; X32-SSE: # BB#0:
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [0,2147483648,0,2147483648]
[X86][SSE] Keep 32-bit target i64 vector shifts on SSE unit. This patch improves the 32-bit target i64 constant matching to detect the shuffle vector splats that are introduced by i64 vector shift vectorization (D8416). Differential Revision: http://reviews.llvm.org/D11327 llvm-svn: 243577
2015-07-30 05:44:27 +08:00
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
; X32-SSE-NEXT: psrlq $7, %xmm2
; X32-SSE-NEXT: psrlq $1, %xmm1
; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; X32-SSE-NEXT: movdqa %xmm0, %xmm1
[X86][SSE] Keep 32-bit target i64 vector shifts on SSE unit. This patch improves the 32-bit target i64 constant matching to detect the shuffle vector splats that are introduced by i64 vector shift vectorization (D8416). Differential Revision: http://reviews.llvm.org/D11327 llvm-svn: 243577
2015-07-30 05:44:27 +08:00
; X32-SSE-NEXT: psrlq $7, %xmm1
; X32-SSE-NEXT: psrlq $1, %xmm0
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
[X86][SSE] Keep 32-bit target i64 vector shifts on SSE unit. This patch improves the 32-bit target i64 constant matching to detect the shuffle vector splats that are introduced by i64 vector shift vectorization (D8416). Differential Revision: http://reviews.llvm.org/D11327 llvm-svn: 243577
2015-07-30 05:44:27 +08:00
; X32-SSE-NEXT: xorpd %xmm2, %xmm1
; X32-SSE-NEXT: psubq %xmm2, %xmm1
[X86][SSE] Vectorize i64 ASHR operations This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed. Differential Revision: http://reviews.llvm.org/D11439 llvm-svn: 243569
2015-07-30 04:31:45 +08:00
; X32-SSE-NEXT: movdqa %xmm1, %xmm0
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <2 x i64> %a, <i64 1, i64 7>
ret <2 x i64> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: constant_shift_v4i32:
; SSE2: # BB#0:
[X86][SSE] Vectorized v4i32 non-uniform shifts. While the v4i32 shl operation is already vectorized using a cvttps2dq/pmulld pattern, the lshr/ashr opeations are still scalarized. This patch adds vectorization support for non-uniform v4i32 shift operations - it splats constant shift amounts to allow them to use the immediate sse shift instructions, or extracts/zero-extends non-constant shift amounts. The individual results are then blended together. Differential Revision: http://reviews.llvm.org/D11063 llvm-svn: 241989
2015-07-12 19:15:19 +08:00
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrad $7, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psrad $5, %xmm2
; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psrad $6, %xmm2
; SSE2-NEXT: psrad $4, %xmm0
; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: constant_shift_v4i32:
; SSE41: # BB#0:
[X86][SSE] Vectorized v4i32 non-uniform shifts. While the v4i32 shl operation is already vectorized using a cvttps2dq/pmulld pattern, the lshr/ashr opeations are still scalarized. This patch adds vectorization support for non-uniform v4i32 shift operations - it splats constant shift amounts to allow them to use the immediate sse shift instructions, or extracts/zero-extends non-constant shift amounts. The individual results are then blended together. Differential Revision: http://reviews.llvm.org/D11063 llvm-svn: 241989
2015-07-12 19:15:19 +08:00
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrad $7, %xmm1
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: psrad $5, %xmm2
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrad $6, %xmm1
; SSE41-NEXT: psrad $4, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
; AVX1-LABEL: constant_shift_v4i32:
; AVX1: # BB#0:
[X86][SSE] Vectorized v4i32 non-uniform shifts. While the v4i32 shl operation is already vectorized using a cvttps2dq/pmulld pattern, the lshr/ashr opeations are still scalarized. This patch adds vectorization support for non-uniform v4i32 shift operations - it splats constant shift amounts to allow them to use the immediate sse shift instructions, or extracts/zero-extends non-constant shift amounts. The individual results are then blended together. Differential Revision: http://reviews.llvm.org/D11063 llvm-svn: 241989
2015-07-12 19:15:19 +08:00
; AVX1-NEXT: vpsrad $7, %xmm0, %xmm1
; AVX1-NEXT: vpsrad $5, %xmm0, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; AVX1-NEXT: vpsrad $6, %xmm0, %xmm2
; AVX1-NEXT: vpsrad $4, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX1-NEXT: retq
;
; AVX2-LABEL: constant_shift_v4i32:
; AVX2: # BB#0:
; AVX2-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOPAVX1-LABEL: constant_shift_v4i32:
; XOPAVX1: # BB#0:
; XOPAVX1-NEXT: vpshad {{.*}}(%rip), %xmm0, %xmm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: constant_shift_v4i32:
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
; XOPAVX2-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: constant_shift_v4i32:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: constant_shift_v4i32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: constant_shift_v4i32:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrad $7, %xmm1
; X32-SSE-NEXT: movdqa %xmm0, %xmm2
; X32-SSE-NEXT: psrad $5, %xmm2
; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; X32-SSE-NEXT: movdqa %xmm0, %xmm2
; X32-SSE-NEXT: psrad $6, %xmm2
; X32-SSE-NEXT: psrad $4, %xmm0
; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
ret <4 x i32> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: constant_shift_v8i16:
; SSE2: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psraw $4, %xmm1
; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,2,2,3]
; SSE2-NEXT: psraw $2, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,3,2,3]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [65535,0,65535,0,65535,0,65535,0]
; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psraw $1, %xmm2
; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: constant_shift_v8i16:
; SSE41: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm0, %xmm1
[X86][SSE41] Avoid variable blend for constant v8i16 shifts The SSE41 v8i16 shift lowering using (v)pblendvb is great for non-constant shift amounts, but if it is constant then we can efficiently reduce the VSELECT to shuffles with the pre-SSE41 lowering. llvm-svn: 263383
2016-03-14 02:35:59 +08:00
; SSE41-NEXT: psraw $4, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $2, %xmm2
[X86][SSE41] Avoid variable blend for constant v8i16 shifts The SSE41 v8i16 shift lowering using (v)pblendvb is great for non-constant shift amounts, but if it is constant then we can efficiently reduce the VSELECT to shuffles with the pre-SSE41 lowering. llvm-svn: 263383
2016-03-14 02:35:59 +08:00
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: psraw $1, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3],xmm2[4],xmm0[5],xmm2[6],xmm0[7]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
; AVX1-LABEL: constant_shift_v8i16:
; AVX1: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX1-NEXT: vpsraw $4, %xmm0, %xmm1
[X86][SSE41] Avoid variable blend for constant v8i16 shifts The SSE41 v8i16 shift lowering using (v)pblendvb is great for non-constant shift amounts, but if it is constant then we can efficiently reduce the VSELECT to shuffles with the pre-SSE41 lowering. llvm-svn: 263383
2016-03-14 02:35:59 +08:00
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX1-NEXT: vpsraw $2, %xmm0, %xmm1
[X86][SSE41] Avoid variable blend for constant v8i16 shifts The SSE41 v8i16 shift lowering using (v)pblendvb is great for non-constant shift amounts, but if it is constant then we can efficiently reduce the VSELECT to shuffles with the pre-SSE41 lowering. llvm-svn: 263383
2016-03-14 02:35:59 +08:00
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX1-NEXT: vpsraw $1, %xmm0, %xmm1
[X86][SSE41] Avoid variable blend for constant v8i16 shifts The SSE41 v8i16 shift lowering using (v)pblendvb is great for non-constant shift amounts, but if it is constant then we can efficiently reduce the VSELECT to shuffles with the pre-SSE41 lowering. llvm-svn: 263383
2016-03-14 02:35:59 +08:00
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX1-NEXT: retq
;
; AVX2-LABEL: constant_shift_v8i16:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
[X86][SSE] Add support for VZEXT constant folding llvm-svn: 265646
2016-04-07 15:52:45 +08:00
; AVX2-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0
[X86] In LowerTRUNCATE, create an ISD::VECTOR_SHUFFLE instead of explicitly creating a PSHUFB. This will be lowered by regular shuffle lowering to a PSHUFB later. Similar was already done for several other shuffles in this function. The test changes are because the old code used explicity zeroing for elements that could have been undef. While I was here I also changed other shuffle vectors in the same function to use the same input twice instead of creating UNDEF nodes. getVectorShuffle can create the UNDEF for us. llvm-svn: 294130
2017-02-06 02:33:14 +08:00
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
VirtRegMap: Replace some identity copies with KILL instructions. An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
2016-07-09 08:19:07 +08:00
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: constant_shift_v8i16:
; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm1, %xmm1, %xmm1
; XOP-NEXT: vpsubw {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpshaw %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
;
[X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift tests llvm-svn: 291444
2017-01-09 22:36:09 +08:00
; AVX512DQ-LABEL: constant_shift_v8i16:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX512DQ-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0
; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512DQ-NEXT: vzeroupper
[X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift tests llvm-svn: 291444
2017-01-09 22:36:09 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512BW-LABEL: constant_shift_v8i16:
; AVX512BW: # BB#0:
; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7]
; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512BW-NEXT: vzeroupper
[X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift tests llvm-svn: 291444
2017-01-09 22:36:09 +08:00
; AVX512BW-NEXT: retq
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512DQVL-LABEL: constant_shift_v8i16:
; AVX512DQVL: # BB#0:
; AVX512DQVL-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX512DQVL-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0
; AVX512DQVL-NEXT: vpmovdw %ymm0, %xmm0
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512DQVL-NEXT: vzeroupper
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512DQVL-NEXT: retq
;
; AVX512BWVL-LABEL: constant_shift_v8i16:
; AVX512BWVL: # BB#0:
; AVX512BWVL-NEXT: vpsravw {{.*}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: constant_shift_v8i16:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psraw $4, %xmm1
; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,2,2,3]
; X32-SSE-NEXT: psraw $2, %xmm1
; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,3,2,3]
; X32-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; X32-SSE-NEXT: movdqa {{.*#+}} xmm0 = [65535,0,65535,0,65535,0,65535,0]
; X32-SSE-NEXT: movdqa %xmm2, %xmm1
; X32-SSE-NEXT: pand %xmm0, %xmm1
; X32-SSE-NEXT: psraw $1, %xmm2
; X32-SSE-NEXT: pandn %xmm2, %xmm0
; X32-SSE-NEXT: por %xmm1, %xmm0
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
ret <8 x i16> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: constant_shift_v16i8:
; SSE2: # BB#0:
; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
[X86][SSE] Add support for constant folding vector logical shift by immediates llvm-svn: 292915
2017-01-24 19:21:57 +08:00
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [8192,24640,41088,57536,49376,32928,16480,32]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtw %xmm4, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pandn %xmm1, %xmm6
; SSE2-NEXT: psraw $4, %xmm1
; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1
; SSE2-NEXT: paddw %xmm4, %xmm4
; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtw %xmm4, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pandn %xmm1, %xmm6
; SSE2-NEXT: psraw $2, %xmm1
; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1
; SSE2-NEXT: paddw %xmm4, %xmm4
; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtw %xmm4, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm4
; SSE2-NEXT: pandn %xmm1, %xmm4
; SSE2-NEXT: psraw $1, %xmm1
; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: psrlw $8, %xmm1
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpgtw %xmm3, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: pandn %xmm0, %xmm5
; SSE2-NEXT: psraw $4, %xmm0
; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: paddw %xmm3, %xmm3
; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpgtw %xmm3, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: pandn %xmm0, %xmm5
; SSE2-NEXT: psraw $2, %xmm0
; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: paddw %xmm3, %xmm3
; SSE2-NEXT: pcmpgtw %xmm3, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: pandn %xmm0, %xmm3
; SSE2-NEXT: psraw $1, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: packuswb %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: constant_shift_v16i8:
; SSE41: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm0, %xmm1
[X86][SSE] Add support for constant folding vector logical shift by immediates llvm-svn: 292915
2017-01-24 19:21:57 +08:00
; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [8192,24640,41088,57536,49376,32928,16480,32]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm3[8],xmm0[9],xmm3[9],xmm0[10],xmm3[10],xmm0[11],xmm3[11],xmm0[12],xmm3[12],xmm0[13],xmm3[13],xmm0[14],xmm3[14],xmm0[15],xmm3[15]
; SSE41-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: psraw $4, %xmm4
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: psraw $2, %xmm4
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: psraw $1, %xmm4
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm2
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: psrlw $8, %xmm2
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]
; SSE41-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm1, %xmm3
; SSE41-NEXT: psraw $4, %xmm3
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm1
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm1, %xmm3
; SSE41-NEXT: psraw $2, %xmm3
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm1
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm1, %xmm3
; SSE41-NEXT: psraw $1, %xmm3
; SSE41-NEXT: paddw %xmm0, %xmm0
[X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
2017-02-06 02:33:24 +08:00
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm1
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: psrlw $8, %xmm1
; SSE41-NEXT: packuswb %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
; AVX-LABEL: constant_shift_v16i8:
; AVX: # BB#0:
[X86][SSE] Add support for constant folding vector logical shift by immediates llvm-svn: 292915
2017-01-24 19:21:57 +08:00
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [8192,24640,41088,57536,49376,32928,16480,32]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; AVX-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX-NEXT: vpsraw $4, %xmm3, %xmm4
; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3
; AVX-NEXT: vpsraw $2, %xmm3, %xmm4
; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2
; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3
; AVX-NEXT: vpsraw $1, %xmm3, %xmm4
; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2
; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm2
; AVX-NEXT: vpsrlw $8, %xmm2, %xmm2
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX-NEXT: vpsraw $4, %xmm0, %xmm3
; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX-NEXT: vpsraw $2, %xmm0, %xmm3
; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm1
; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX-NEXT: vpsraw $1, %xmm0, %xmm3
; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm1
; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX-NEXT: vpsrlw $8, %xmm0, %xmm0
; AVX-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: constant_shift_v16i8:
; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm1, %xmm1, %xmm1
; XOP-NEXT: vpsubb {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpshab %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: constant_shift_v16i8:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
[X86][AVX512] Enable v16i8/v32i8 vector shifts to use an extend+shift+truncate pattern. Use the existing AVX2 v8i16 vector shift lowering for v16i8 (extending to v16i32) on AVX512 targets and v32i8 (extending to v32i16) on AVX512BW targets. Cost model updates to follow. llvm-svn: 291451
2017-01-10 01:20:03 +08:00
; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512-NEXT: vpsravd {{.*}}(%rip), %zmm0, %zmm0
; AVX512-NEXT: vpmovdb %zmm0, %xmm0
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512-NEXT: vzeroupper
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: constant_shift_v16i8:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512VL-NEXT: vpsravd {{.*}}(%rip), %zmm0, %zmm0
; AVX512VL-NEXT: vpmovdb %zmm0, %xmm0
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512VL-NEXT: vzeroupper
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: constant_shift_v16i8:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
[X86][SSE] Add support for constant folding vector logical shift by immediates llvm-svn: 292915
2017-01-24 19:21:57 +08:00
; X32-SSE-NEXT: movdqa {{.*#+}} xmm3 = [8192,24640,41088,57536,49376,32928,16480,32]
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15]
; X32-SSE-NEXT: pxor %xmm2, %xmm2
; X32-SSE-NEXT: pxor %xmm5, %xmm5
; X32-SSE-NEXT: pcmpgtw %xmm4, %xmm5
; X32-SSE-NEXT: movdqa %xmm5, %xmm6
; X32-SSE-NEXT: pandn %xmm1, %xmm6
; X32-SSE-NEXT: psraw $4, %xmm1
; X32-SSE-NEXT: pand %xmm5, %xmm1
; X32-SSE-NEXT: por %xmm6, %xmm1
; X32-SSE-NEXT: paddw %xmm4, %xmm4
; X32-SSE-NEXT: pxor %xmm5, %xmm5
; X32-SSE-NEXT: pcmpgtw %xmm4, %xmm5
; X32-SSE-NEXT: movdqa %xmm5, %xmm6
; X32-SSE-NEXT: pandn %xmm1, %xmm6
; X32-SSE-NEXT: psraw $2, %xmm1
; X32-SSE-NEXT: pand %xmm5, %xmm1
; X32-SSE-NEXT: por %xmm6, %xmm1
; X32-SSE-NEXT: paddw %xmm4, %xmm4
; X32-SSE-NEXT: pxor %xmm5, %xmm5
; X32-SSE-NEXT: pcmpgtw %xmm4, %xmm5
; X32-SSE-NEXT: movdqa %xmm5, %xmm4
; X32-SSE-NEXT: pandn %xmm1, %xmm4
; X32-SSE-NEXT: psraw $1, %xmm1
; X32-SSE-NEXT: pand %xmm5, %xmm1
; X32-SSE-NEXT: por %xmm4, %xmm1
; X32-SSE-NEXT: psrlw $8, %xmm1
; X32-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X32-SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pcmpgtw %xmm3, %xmm4
; X32-SSE-NEXT: movdqa %xmm4, %xmm5
; X32-SSE-NEXT: pandn %xmm0, %xmm5
; X32-SSE-NEXT: psraw $4, %xmm0
; X32-SSE-NEXT: pand %xmm4, %xmm0
; X32-SSE-NEXT: por %xmm5, %xmm0
; X32-SSE-NEXT: paddw %xmm3, %xmm3
; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pcmpgtw %xmm3, %xmm4
; X32-SSE-NEXT: movdqa %xmm4, %xmm5
; X32-SSE-NEXT: pandn %xmm0, %xmm5
; X32-SSE-NEXT: psraw $2, %xmm0
; X32-SSE-NEXT: pand %xmm4, %xmm0
; X32-SSE-NEXT: por %xmm5, %xmm0
; X32-SSE-NEXT: paddw %xmm3, %xmm3
; X32-SSE-NEXT: pcmpgtw %xmm3, %xmm2
; X32-SSE-NEXT: movdqa %xmm2, %xmm3
; X32-SSE-NEXT: pandn %xmm0, %xmm3
; X32-SSE-NEXT: psraw $1, %xmm0
; X32-SSE-NEXT: pand %xmm2, %xmm0
; X32-SSE-NEXT: por %xmm3, %xmm0
; X32-SSE-NEXT: psrlw $8, %xmm0
; X32-SSE-NEXT: packuswb %xmm1, %xmm0
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
ret <16 x i8> %shift
}
;
; Uniform Constant Shifts
;
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-LABEL: splatconstant_shift_v2i64:
; SSE2: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrad $7, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; SSE2-NEXT: psrlq $7, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
[X86][SSE] Vectorized i64 uniform constant SRA shifts This patch adds vectorization support for uniform constant i64 arithmetic shift right operators. Differential Revision: http://reviews.llvm.org/D9645 llvm-svn: 241514
2015-07-07 06:35:19 +08:00
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE2-NEXT: retq
;
; SSE41-LABEL: splatconstant_shift_v2i64:
; SSE41: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrad $7, %xmm1
; SSE41-NEXT: psrlq $7, %xmm0
[X86][SSE] Vectorized i64 uniform constant SRA shifts This patch adds vectorization support for uniform constant i64 arithmetic shift right operators. Differential Revision: http://reviews.llvm.org/D9645 llvm-svn: 241514
2015-07-07 06:35:19 +08:00
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE41-NEXT: retq
;
[X86][SSE] Vectorized i64 uniform constant SRA shifts This patch adds vectorization support for uniform constant i64 arithmetic shift right operators. Differential Revision: http://reviews.llvm.org/D9645 llvm-svn: 241514
2015-07-07 06:35:19 +08:00
; AVX1-LABEL: splatconstant_shift_v2i64:
; AVX1: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX1-NEXT: vpsrad $7, %xmm0, %xmm1
; AVX1-NEXT: vpsrlq $7, %xmm0, %xmm0
[X86][SSE] Vectorized i64 uniform constant SRA shifts This patch adds vectorization support for uniform constant i64 arithmetic shift right operators. Differential Revision: http://reviews.llvm.org/D9645 llvm-svn: 241514
2015-07-07 06:35:19 +08:00
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; AVX1-NEXT: retq
;
; AVX2-LABEL: splatconstant_shift_v2i64:
; AVX2: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX2-NEXT: vpsrad $7, %xmm0, %xmm1
; AVX2-NEXT: vpsrlq $7, %xmm0, %xmm0
[X86][SSE] Vectorized i64 uniform constant SRA shifts This patch adds vectorization support for uniform constant i64 arithmetic shift right operators. Differential Revision: http://reviews.llvm.org/D9645 llvm-svn: 241514
2015-07-07 06:35:19 +08:00
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
; AVX2-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: splatconstant_shift_v2i64:
; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm1, %xmm1, %xmm1
; XOP-NEXT: vpsubq {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpshaq %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: splatconstant_shift_v2i64:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
[X86][AVX512] Add support for ASHR v2i64/v4i64 support without VLX Use v8i64 ASHR instructions if we don't have VLX. Differential Revision: https://reviews.llvm.org/D28537 llvm-svn: 295656
2017-02-20 20:16:38 +08:00
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512-NEXT: vpsraq $7, %zmm0, %zmm0
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests llvm-svn: 312529
2017-09-05 20:23:45 +08:00
; AVX512-NEXT: vzeroupper
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: splatconstant_shift_v2i64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpsraq $7, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: splatconstant_shift_v2i64:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrad $7, %xmm1
; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; X32-SSE-NEXT: psrlq $7, %xmm0
; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <2 x i64> %a, <i64 7, i64 7>
ret <2 x i64> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE-LABEL: splatconstant_shift_v4i32:
; SSE: # BB#0:
; SSE-NEXT: psrad $5, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: splatconstant_shift_v4i32:
; AVX: # BB#0:
; AVX-NEXT: vpsrad $5, %xmm0, %xmm0
; AVX-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: splatconstant_shift_v4i32:
; XOP: # BB#0:
; XOP-NEXT: vpsrad $5, %xmm0, %xmm0
; XOP-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: splatconstant_shift_v4i32:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: vpsrad $5, %xmm0, %xmm0
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: splatconstant_shift_v4i32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpsrad $5, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: splatconstant_shift_v4i32:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: psrad $5, %xmm0
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
ret <4 x i32> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE-LABEL: splatconstant_shift_v8i16:
; SSE: # BB#0:
; SSE-NEXT: psraw $3, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: splatconstant_shift_v8i16:
; AVX: # BB#0:
; AVX-NEXT: vpsraw $3, %xmm0, %xmm0
; AVX-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: splatconstant_shift_v8i16:
; XOP: # BB#0:
; XOP-NEXT: vpsraw $3, %xmm0, %xmm0
; XOP-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: splatconstant_shift_v8i16:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: vpsraw $3, %xmm0, %xmm0
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: splatconstant_shift_v8i16:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpsraw $3, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: splatconstant_shift_v8i16:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: psraw $3, %xmm0
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
ret <8 x i16> %shift
}
[X86][SSE] Added nounwind attribute to vector shift tests. Stop i686 codegen from generating cfi directives. llvm-svn: 242443
2015-07-17 05:14:26 +08:00
define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) nounwind {
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE-LABEL: splatconstant_shift_v16i8:
; SSE: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE-NEXT: psrlw $3, %xmm0
; SSE-NEXT: pand {{.*}}(%rip), %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: psubb %xmm1, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: splatconstant_shift_v16i8:
; AVX: # BB#0:
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX-NEXT: vpsrlw $3, %xmm0, %xmm0
; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
[X86][SSE] Vector shift test cleanup. NFC. llvm-svn: 241730
2015-07-09 05:11:17 +08:00
; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsubb %xmm1, %xmm0, %xmm0
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
; AVX-NEXT: retq
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
;
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
2015-09-30 16:17:50 +08:00
; XOP-LABEL: splatconstant_shift_v16i8:
; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm1, %xmm1, %xmm1
; XOP-NEXT: vpsubb {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpshab %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
;
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-LABEL: splatconstant_shift_v16i8:
[X86][SSE] Standardized triples in vector shift tests Made no sense for them to be different and caused useless diffs in assembly remarks. llvm-svn: 291274
2017-01-07 03:56:57 +08:00
; AVX512: # BB#0:
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. Differential Revision: http://reviews.llvm.org/D15713 llvm-svn: 256324
2015-12-23 16:06:50 +08:00
; AVX512-NEXT: vpsrlw $3, %xmm0, %xmm0
; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
;
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests llvm-svn: 291488
2017-01-10 06:13:51 +08:00
; AVX512VL-LABEL: splatconstant_shift_v16i8:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpsrlw $3, %xmm0, %xmm0
; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; AVX512VL-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-LABEL: splatconstant_shift_v16i8:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: psrlw $3, %xmm0
[X86] Updated test checks script to generalise LCPI symbol refs The script now replace '.LCPI888_8' style asm symbols with the {{\.LCPI.*}} re pattern - this helps stop hardcoded symbols in 32-bit x86 tests changing with every edit of the file Refreshed some tests to demonstrate the new check llvm-svn: 272488
2016-06-12 04:39:21 +08:00
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
[X86][SSE] Added i686/SSE2 vector shift tests. We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
2015-07-15 16:04:07 +08:00
; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; X32-SSE-NEXT: pxor %xmm1, %xmm0
; X32-SSE-NEXT: psubb %xmm1, %xmm0
; X32-SSE-NEXT: retl
[X86][SSE] Added full set of 128-bit vector shift tests. Removed some old duplicate tests. llvm-svn: 240465
2015-06-24 05:18:15 +08:00
%shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %shift
}