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llvm-project/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll

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[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
;
; udiv by 7
;
define <8 x i64> @test_div7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_div7_8i64:
; AVX: # BB#0:
; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
; AVX-NEXT: vpextrq $1, %xmm1, %rcx
; AVX-NEXT: movabsq $2635249153387078803, %rsi # imm = 0x2492492492492493
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: shrq %rcx
; AVX-NEXT: addq %rdx, %rcx
; AVX-NEXT: shrq $2, %rcx
; AVX-NEXT: vmovq %rcx, %xmm2
; AVX-NEXT: vmovq %xmm1, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: shrq %rcx
; AVX-NEXT: addq %rdx, %rcx
; AVX-NEXT: shrq $2, %rcx
; AVX-NEXT: vmovq %rcx, %xmm1
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX-NEXT: vpextrq $1, %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: shrq %rcx
; AVX-NEXT: addq %rdx, %rcx
; AVX-NEXT: shrq $2, %rcx
; AVX-NEXT: vmovq %rcx, %xmm3
; AVX-NEXT: vmovq %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: shrq %rcx
; AVX-NEXT: addq %rdx, %rcx
; AVX-NEXT: shrq $2, %rcx
; AVX-NEXT: vmovq %rcx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
[AVX512] Use 256-bit extract instructions for extracting bits [255:128] from a 512-bit register This enables the use of a smaller encoding by using a VEX instruction when possible. Differential Revision: https://reviews.llvm.org/D37092 llvm-svn: 312100
2017-08-30 15:26:12 +08:00
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX-NEXT: vpextrq $1, %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: shrq %rcx
; AVX-NEXT: addq %rdx, %rcx
; AVX-NEXT: shrq $2, %rcx
; AVX-NEXT: vmovq %rcx, %xmm3
; AVX-NEXT: vmovq %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: shrq %rcx
; AVX-NEXT: addq %rdx, %rcx
; AVX-NEXT: shrq $2, %rcx
; AVX-NEXT: vmovq %rcx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX-NEXT: vpextrq $1, %xmm0, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: shrq %rcx
; AVX-NEXT: addq %rdx, %rcx
; AVX-NEXT: shrq $2, %rcx
; AVX-NEXT: vmovq %rcx, %xmm3
; AVX-NEXT: vmovq %xmm0, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: shrq %rcx
; AVX-NEXT: addq %rdx, %rcx
; AVX-NEXT: shrq $2, %rcx
; AVX-NEXT: vmovq %rcx, %xmm0
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = udiv <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
}
define <16 x i32> @test_div7_16i32(<16 x i32> %a) nounwind {
; AVX-LABEL: test_div7_16i32:
; AVX: # BB#0:
[X86] Add support for v16i32 UMUL_LOHI/SMUL_LOHI Summary: This patch extends the v8i32/v4i32 custom lowering to support v16i32 Reviewers: zvi, RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38274 llvm-svn: 314221
2017-09-27 00:43:57 +08:00
; AVX-NEXT: vpbroadcastd {{.*#+}} zmm1 = [613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757]
; AVX-NEXT: vpmuludq %zmm1, %zmm0, %zmm2
; AVX-NEXT: vpshufd {{.*#+}} zmm1 = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: vpshufd {{.*#+}} zmm3 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: vpmuludq %zmm1, %zmm3, %zmm1
; AVX-NEXT: vmovdqa32 {{.*#+}} zmm3 = [1,17,3,19,5,21,7,23,9,25,11,27,13,29,15,31]
; AVX-NEXT: vpermi2d %zmm1, %zmm2, %zmm3
; AVX-NEXT: vpsubd %zmm3, %zmm0, %zmm0
; AVX-NEXT: vpsrld $1, %zmm0, %zmm0
; AVX-NEXT: vpaddd %zmm3, %zmm0, %zmm0
; AVX-NEXT: vpsrld $2, %zmm0, %zmm0
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX-NEXT: retq
%res = udiv <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
ret <16 x i32> %res
}
define <32 x i16> @test_div7_32i16(<32 x i16> %a) nounwind {
; AVX512F-LABEL: test_div7_32i16:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363]
; AVX512F-NEXT: vpmulhuw %ymm2, %ymm0, %ymm3
; AVX512F-NEXT: vpsubw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm0
; AVX512F-NEXT: vpaddw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $2, %ymm0, %ymm0
; AVX512F-NEXT: vpmulhuw %ymm2, %ymm1, %ymm2
; AVX512F-NEXT: vpsubw %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
; AVX512F-NEXT: vpaddw %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $2, %ymm1, %ymm1
; AVX512F-NEXT: retq
;
; AVX512BW-LABEL: test_div7_32i16:
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vpmulhuw {{.*}}(%rip), %zmm0, %zmm1
; AVX512BW-NEXT: vpsubw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $1, %zmm0, %zmm0
; AVX512BW-NEXT: vpaddw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: vpsrlw $2, %zmm0, %zmm0
; AVX512BW-NEXT: retq
%res = udiv <32 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <32 x i16> %res
}
define <64 x i8> @test_div7_64i8(<64 x i8> %a) nounwind {
; AVX512F-LABEL: test_div7_64i8:
; AVX512F: # BB#0:
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37]
; AVX512F-NEXT: vpmullw %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm4 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpmullw %ymm3, %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm5 = ymm4[2,3],ymm2[2,3]
; AVX512F-NEXT: vinserti128 $1, %xmm2, %ymm4, %ymm2
; AVX512F-NEXT: vpackuswb %ymm5, %ymm2, %ymm2
; AVX512F-NEXT: vpsubb %ymm2, %ymm0, %ymm0
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm0
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpand %ymm4, %ymm0, %ymm0
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $2, %ymm0, %ymm0
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm5
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm5 = xmm5[0],zero,xmm5[1],zero,xmm5[2],zero,xmm5[3],zero,xmm5[4],zero,xmm5[5],zero,xmm5[6],zero,xmm5[7],zero,xmm5[8],zero,xmm5[9],zero,xmm5[10],zero,xmm5[11],zero,xmm5[12],zero,xmm5[13],zero,xmm5[14],zero,xmm5[15],zero
; AVX512F-NEXT: vpmullw %ymm3, %ymm5, %ymm5
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm6 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpmullw %ymm3, %ymm6, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm6 = ymm3[2,3],ymm5[2,3]
; AVX512F-NEXT: vinserti128 $1, %xmm5, %ymm3, %ymm3
; AVX512F-NEXT: vpackuswb %ymm6, %ymm3, %ymm3
; AVX512F-NEXT: vpsubb %ymm3, %ymm1, %ymm1
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $2, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm1
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: retq
;
; AVX512BW-LABEL: test_div7_64i8:
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vextracti32x4 $3, %zmm0, %xmm1
; AVX512BW-NEXT: vpextrb $1, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpextrb $0, %xmm1, %ecx
; AVX512BW-NEXT: imull $37, %ecx, %edx
; AVX512BW-NEXT: shrl $8, %edx
; AVX512BW-NEXT: subb %dl, %cl
; AVX512BW-NEXT: shrb %cl
; AVX512BW-NEXT: addb %dl, %cl
; AVX512BW-NEXT: shrb $2, %cl
; AVX512BW-NEXT: movzbl %cl, %ecx
; AVX512BW-NEXT: vmovd %ecx, %xmm2
; AVX512BW-NEXT: vpinsrb $1, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $2, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $2, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $3, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $3, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $4, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $4, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $5, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $5, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $6, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $6, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $7, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $7, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $8, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $8, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $9, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $9, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $10, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $10, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $11, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $11, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $12, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $12, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $13, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $13, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $14, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $14, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $15, %xmm1, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm2, %xmm1
; AVX512BW-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX512BW-NEXT: vpextrb $1, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpextrb $0, %xmm2, %ecx
; AVX512BW-NEXT: imull $37, %ecx, %edx
; AVX512BW-NEXT: shrl $8, %edx
; AVX512BW-NEXT: subb %dl, %cl
; AVX512BW-NEXT: shrb %cl
; AVX512BW-NEXT: addb %dl, %cl
; AVX512BW-NEXT: shrb $2, %cl
; AVX512BW-NEXT: movzbl %cl, %ecx
; AVX512BW-NEXT: vmovd %ecx, %xmm3
; AVX512BW-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $2, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $3, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $4, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $5, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $6, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $7, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $8, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $9, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $10, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $11, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $12, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $13, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $14, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $15, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm3, %xmm2
; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
[AVX512] Use 256-bit extract instructions for extracting bits [255:128] from a 512-bit register This enables the use of a smaller encoding by using a VEX instruction when possible. Differential Revision: https://reviews.llvm.org/D37092 llvm-svn: 312100
2017-08-30 15:26:12 +08:00
; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm2
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: vpextrb $1, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpextrb $0, %xmm2, %ecx
; AVX512BW-NEXT: imull $37, %ecx, %edx
; AVX512BW-NEXT: shrl $8, %edx
; AVX512BW-NEXT: subb %dl, %cl
; AVX512BW-NEXT: shrb %cl
; AVX512BW-NEXT: addb %dl, %cl
; AVX512BW-NEXT: shrb $2, %cl
; AVX512BW-NEXT: movzbl %cl, %ecx
; AVX512BW-NEXT: vmovd %ecx, %xmm3
; AVX512BW-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $2, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $3, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $4, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $5, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $6, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $7, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $8, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $9, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $10, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $11, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $12, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $13, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $14, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $15, %xmm2, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm3, %xmm2
; AVX512BW-NEXT: vpextrb $1, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpextrb $0, %xmm0, %ecx
; AVX512BW-NEXT: imull $37, %ecx, %edx
; AVX512BW-NEXT: shrl $8, %edx
; AVX512BW-NEXT: subb %dl, %cl
; AVX512BW-NEXT: shrb %cl
; AVX512BW-NEXT: addb %dl, %cl
; AVX512BW-NEXT: shrb $2, %cl
; AVX512BW-NEXT: movzbl %cl, %ecx
; AVX512BW-NEXT: vmovd %ecx, %xmm3
; AVX512BW-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $2, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $3, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $4, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $5, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $6, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $7, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $8, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $9, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $10, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $11, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $12, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $13, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $14, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $15, %xmm0, %eax
; AVX512BW-NEXT: imull $37, %eax, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movzbl %al, %eax
; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm3, %xmm0
; AVX512BW-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq
%res = udiv <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
ret <64 x i8> %res
}
;
; urem by 7
;
define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_rem7_8i64:
; AVX: # BB#0:
; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
; AVX-NEXT: vpextrq $1, %xmm1, %rcx
; AVX-NEXT: movabsq $2635249153387078803, %rsi # imm = 0x2492492492492493
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: subq %rdx, %rax
; AVX-NEXT: shrq %rax
; AVX-NEXT: addq %rdx, %rax
; AVX-NEXT: shrq $2, %rax
; AVX-NEXT: leaq (,%rax,8), %rdx
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: vmovq %rcx, %xmm2
; AVX-NEXT: vmovq %xmm1, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: subq %rdx, %rax
; AVX-NEXT: shrq %rax
; AVX-NEXT: addq %rdx, %rax
; AVX-NEXT: shrq $2, %rax
; AVX-NEXT: leaq (,%rax,8), %rdx
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: vmovq %rcx, %xmm1
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX-NEXT: vpextrq $1, %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: subq %rdx, %rax
; AVX-NEXT: shrq %rax
; AVX-NEXT: addq %rdx, %rax
; AVX-NEXT: shrq $2, %rax
; AVX-NEXT: leaq (,%rax,8), %rdx
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: vmovq %rcx, %xmm3
; AVX-NEXT: vmovq %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: subq %rdx, %rax
; AVX-NEXT: shrq %rax
; AVX-NEXT: addq %rdx, %rax
; AVX-NEXT: shrq $2, %rax
; AVX-NEXT: leaq (,%rax,8), %rdx
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: vmovq %rcx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
[AVX512] Use 256-bit extract instructions for extracting bits [255:128] from a 512-bit register This enables the use of a smaller encoding by using a VEX instruction when possible. Differential Revision: https://reviews.llvm.org/D37092 llvm-svn: 312100
2017-08-30 15:26:12 +08:00
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX-NEXT: vpextrq $1, %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: subq %rdx, %rax
; AVX-NEXT: shrq %rax
; AVX-NEXT: addq %rdx, %rax
; AVX-NEXT: shrq $2, %rax
; AVX-NEXT: leaq (,%rax,8), %rdx
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: vmovq %rcx, %xmm3
; AVX-NEXT: vmovq %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: subq %rdx, %rax
; AVX-NEXT: shrq %rax
; AVX-NEXT: addq %rdx, %rax
; AVX-NEXT: shrq $2, %rax
; AVX-NEXT: leaq (,%rax,8), %rdx
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: vmovq %rcx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX-NEXT: vpextrq $1, %xmm0, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: subq %rdx, %rax
; AVX-NEXT: shrq %rax
; AVX-NEXT: addq %rdx, %rax
; AVX-NEXT: shrq $2, %rax
; AVX-NEXT: leaq (,%rax,8), %rdx
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: vmovq %rcx, %xmm3
; AVX-NEXT: vmovq %xmm0, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: mulq %rsi
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: subq %rdx, %rax
; AVX-NEXT: shrq %rax
; AVX-NEXT: addq %rdx, %rax
; AVX-NEXT: shrq $2, %rax
; AVX-NEXT: leaq (,%rax,8), %rdx
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: subq %rdx, %rcx
; AVX-NEXT: vmovq %rcx, %xmm0
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = urem <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
}
define <16 x i32> @test_rem7_16i32(<16 x i32> %a) nounwind {
; AVX-LABEL: test_rem7_16i32:
; AVX: # BB#0:
[X86] Add support for v16i32 UMUL_LOHI/SMUL_LOHI Summary: This patch extends the v8i32/v4i32 custom lowering to support v16i32 Reviewers: zvi, RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38274 llvm-svn: 314221
2017-09-27 00:43:57 +08:00
; AVX-NEXT: vpbroadcastd {{.*#+}} zmm1 = [613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757]
; AVX-NEXT: vpmuludq %zmm1, %zmm0, %zmm2
; AVX-NEXT: vpshufd {{.*#+}} zmm1 = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: vpshufd {{.*#+}} zmm3 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: vpmuludq %zmm1, %zmm3, %zmm1
; AVX-NEXT: vmovdqa32 {{.*#+}} zmm3 = [1,17,3,19,5,21,7,23,9,25,11,27,13,29,15,31]
; AVX-NEXT: vpermi2d %zmm1, %zmm2, %zmm3
; AVX-NEXT: vpsubd %zmm3, %zmm0, %zmm1
; AVX-NEXT: vpsrld $1, %zmm1, %zmm1
; AVX-NEXT: vpaddd %zmm3, %zmm1, %zmm1
; AVX-NEXT: vpsrld $2, %zmm1, %zmm1
; AVX-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm1, %zmm1
; AVX-NEXT: vpsubd %zmm1, %zmm0, %zmm0
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX-NEXT: retq
%res = urem <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
ret <16 x i32> %res
}
define <32 x i16> @test_rem7_32i16(<32 x i16> %a) nounwind {
; AVX512F-LABEL: test_rem7_32i16:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363,9363]
; AVX512F-NEXT: vpmulhuw %ymm2, %ymm0, %ymm3
; AVX512F-NEXT: vpsubw %ymm3, %ymm0, %ymm4
; AVX512F-NEXT: vpsrlw $1, %ymm4, %ymm4
; AVX512F-NEXT: vpaddw %ymm3, %ymm4, %ymm3
; AVX512F-NEXT: vpsrlw $2, %ymm3, %ymm3
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; AVX512F-NEXT: vpmullw %ymm4, %ymm3, %ymm3
; AVX512F-NEXT: vpsubw %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpmulhuw %ymm2, %ymm1, %ymm2
; AVX512F-NEXT: vpsubw %ymm2, %ymm1, %ymm3
; AVX512F-NEXT: vpsrlw $1, %ymm3, %ymm3
; AVX512F-NEXT: vpaddw %ymm2, %ymm3, %ymm2
; AVX512F-NEXT: vpsrlw $2, %ymm2, %ymm2
; AVX512F-NEXT: vpmullw %ymm4, %ymm2, %ymm2
; AVX512F-NEXT: vpsubw %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: retq
;
; AVX512BW-LABEL: test_rem7_32i16:
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vpmulhuw {{.*}}(%rip), %zmm0, %zmm1
; AVX512BW-NEXT: vpsubw %zmm1, %zmm0, %zmm2
; AVX512BW-NEXT: vpsrlw $1, %zmm2, %zmm2
; AVX512BW-NEXT: vpaddw %zmm1, %zmm2, %zmm1
; AVX512BW-NEXT: vpsrlw $2, %zmm1, %zmm1
; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsubw %zmm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq
%res = urem <32 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <32 x i16> %res
}
define <64 x i8> @test_rem7_64i8(<64 x i8> %a) nounwind {
; AVX512F-LABEL: test_rem7_64i8:
; AVX512F: # BB#0:
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm3 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37]
; AVX512F-NEXT: vpmullw %ymm2, %ymm3, %ymm3
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm4 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; AVX512F-NEXT: vpmullw %ymm2, %ymm4, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm5 = ymm4[2,3],ymm3[2,3]
; AVX512F-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm3
; AVX512F-NEXT: vpackuswb %ymm5, %ymm3, %ymm3
; AVX512F-NEXT: vpsubb %ymm3, %ymm0, %ymm4
; AVX512F-NEXT: vpsrlw $1, %ymm4, %ymm5
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; AVX512F-NEXT: vpand %ymm4, %ymm5, %ymm5
; AVX512F-NEXT: vpaddb %ymm3, %ymm5, %ymm3
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpsrlw $2, %ymm3, %ymm3
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; AVX512F-NEXT: vpand %ymm5, %ymm3, %ymm6
; AVX512F-NEXT: vpmovsxbw %xmm6, %ymm7
[X86][SSE] Add support for (V)PMOVSX* constant folding We already have (V)PMOVZX* combining support, this is the beginning of handling (V)PMOVSX* similarly - other combines in combineVSZext can be generalized in future patches. This unearthed an interesting bug in that we were generating illegal build vectors on 32-bit targets - it was proving difficult to create a test for it from PMOVZX, but it fired immediately with PMOVSX. I've created a more general form of the existing getConstVector to handle these cases - ideally this should be handled in non-target-specific code but I couldn't find an equivalent. Differential Revision: https://reviews.llvm.org/D25874 llvm-svn: 285072
2016-10-25 22:29:25 +08:00
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpmullw %ymm3, %ymm7, %ymm7
; AVX512F-NEXT: vpmovsxwd %ymm7, %zmm7
; AVX512F-NEXT: vpmovdb %zmm7, %xmm7
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vextracti128 $1, %ymm6, %xmm6
; AVX512F-NEXT: vpmovsxbw %xmm6, %ymm6
; AVX512F-NEXT: vpmullw %ymm3, %ymm6, %ymm6
; AVX512F-NEXT: vpmovsxwd %ymm6, %zmm6
; AVX512F-NEXT: vpmovdb %zmm6, %xmm6
; AVX512F-NEXT: vinserti128 $1, %xmm6, %ymm7, %ymm6
; AVX512F-NEXT: vpsubb %ymm6, %ymm0, %ymm0
; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm6
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm6 = xmm6[0],zero,xmm6[1],zero,xmm6[2],zero,xmm6[3],zero,xmm6[4],zero,xmm6[5],zero,xmm6[6],zero,xmm6[7],zero,xmm6[8],zero,xmm6[9],zero,xmm6[10],zero,xmm6[11],zero,xmm6[12],zero,xmm6[13],zero,xmm6[14],zero,xmm6[15],zero
; AVX512F-NEXT: vpmullw %ymm2, %ymm6, %ymm6
; AVX512F-NEXT: vpsrlw $8, %ymm6, %ymm6
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm7 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpmullw %ymm2, %ymm7, %ymm2
; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vperm2i128 {{.*#+}} ymm7 = ymm2[2,3],ymm6[2,3]
; AVX512F-NEXT: vinserti128 $1, %xmm6, %ymm2, %ymm2
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpackuswb %ymm7, %ymm2, %ymm2
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vpsubb %ymm2, %ymm1, %ymm6
; AVX512F-NEXT: vpsrlw $1, %ymm6, %ymm6
; AVX512F-NEXT: vpand %ymm4, %ymm6, %ymm4
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpaddb %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpsrlw $2, %ymm2, %ymm2
[X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. llvm-svn: 314274
2017-09-27 14:04:55 +08:00
; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512F-NEXT: vpmovsxbw %xmm2, %ymm4
; AVX512F-NEXT: vpmullw %ymm3, %ymm4, %ymm4
; AVX512F-NEXT: vpmovsxwd %ymm4, %zmm4
; AVX512F-NEXT: vpmovdb %zmm4, %xmm4
; AVX512F-NEXT: vextracti128 $1, %ymm2, %xmm2
; AVX512F-NEXT: vpmovsxbw %xmm2, %ymm2
; AVX512F-NEXT: vpmullw %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpmovsxwd %ymm2, %zmm2
; AVX512F-NEXT: vpmovdb %zmm2, %xmm2
; AVX512F-NEXT: vinserti128 $1, %xmm2, %ymm4, %ymm2
; AVX512F-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: retq
;
; AVX512BW-LABEL: test_rem7_64i8:
; AVX512BW: # BB#0:
; AVX512BW-NEXT: vextracti32x4 $3, %zmm0, %xmm1
; AVX512BW-NEXT: vpextrb $1, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %ecx
; AVX512BW-NEXT: shrl $8, %ecx
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %cl, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %cl, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: movb $7, %cl
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %edx
; AVX512BW-NEXT: vpextrb $0, %xmm1, %esi
; AVX512BW-NEXT: imull $37, %esi, %edi
; AVX512BW-NEXT: shrl $8, %edi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %esi, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %dil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %dil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %sil
; AVX512BW-NEXT: movzbl %sil, %eax
; AVX512BW-NEXT: vmovd %eax, %xmm2
; AVX512BW-NEXT: vpinsrb $1, %edx, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $2, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $2, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $3, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $3, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $4, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $4, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $5, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $5, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $6, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $6, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $7, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $7, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $8, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $8, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $9, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $9, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $10, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $10, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $11, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $11, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $12, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $12, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $13, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $13, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $14, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $14, %eax, %xmm2, %xmm2
; AVX512BW-NEXT: vpextrb $15, %xmm1, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm2, %xmm1
; AVX512BW-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX512BW-NEXT: vpextrb $1, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %edx
; AVX512BW-NEXT: vpextrb $0, %xmm2, %esi
; AVX512BW-NEXT: imull $37, %esi, %edi
; AVX512BW-NEXT: shrl $8, %edi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %esi, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %dil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %dil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %sil
; AVX512BW-NEXT: movzbl %sil, %eax
; AVX512BW-NEXT: vmovd %eax, %xmm3
; AVX512BW-NEXT: vpinsrb $1, %edx, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $2, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $3, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $4, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $5, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $6, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $7, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $8, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $9, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $10, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $11, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $12, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $13, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $14, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $15, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm3, %xmm2
; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
[AVX512] Use 256-bit extract instructions for extracting bits [255:128] from a 512-bit register This enables the use of a smaller encoding by using a VEX instruction when possible. Differential Revision: https://reviews.llvm.org/D37092 llvm-svn: 312100
2017-08-30 15:26:12 +08:00
; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm2
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: vpextrb $1, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %edx
; AVX512BW-NEXT: vpextrb $0, %xmm2, %esi
; AVX512BW-NEXT: imull $37, %esi, %edi
; AVX512BW-NEXT: shrl $8, %edi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %esi, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %dil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %dil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %sil
; AVX512BW-NEXT: movzbl %sil, %eax
; AVX512BW-NEXT: vmovd %eax, %xmm3
; AVX512BW-NEXT: vpinsrb $1, %edx, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $2, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $3, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $4, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $5, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $6, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $7, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $8, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $9, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $10, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $11, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $12, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $13, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $14, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $15, %xmm2, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm3, %xmm2
; AVX512BW-NEXT: vpextrb $1, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %edx
; AVX512BW-NEXT: vpextrb $0, %xmm0, %esi
; AVX512BW-NEXT: imull $37, %esi, %edi
; AVX512BW-NEXT: shrl $8, %edi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %esi, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %dil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %dil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %sil
; AVX512BW-NEXT: movzbl %sil, %eax
; AVX512BW-NEXT: vmovd %eax, %xmm3
; AVX512BW-NEXT: vpinsrb $1, %edx, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $2, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $3, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $4, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $5, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $6, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $7, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $8, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $9, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $10, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $11, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $12, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $13, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $14, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
; AVX512BW-NEXT: vpextrb $15, %xmm0, %edx
; AVX512BW-NEXT: imull $37, %edx, %esi
; AVX512BW-NEXT: shrl $8, %esi
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 09:11:17 +08:00
; AVX512BW-NEXT: movl %edx, %eax
[X86][AVX512] Add vector integer division by constant tests Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
2016-04-11 01:14:26 +08:00
; AVX512BW-NEXT: subb %sil, %al
; AVX512BW-NEXT: shrb %al
; AVX512BW-NEXT: addb %sil, %al
; AVX512BW-NEXT: shrb $2, %al
; AVX512BW-NEXT: mulb %cl
; AVX512BW-NEXT: subb %al, %dl
; AVX512BW-NEXT: movzbl %dl, %eax
; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm3, %xmm0
; AVX512BW-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq
%res = urem <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
ret <64 x i8> %res
}