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llvm-project/llvm/test/CodeGen/X86/bitreverse.ll

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[X86] Regenerated bitreverse tests to demonstrate what is going on. llvm-svn: 274915
2016-07-09 03:51:08 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
[SDAG] Introduce a new BITREVERSE node along with a corresponding LLVM intrinsic Several backends have instructions to reverse the order of bits in an integer. Conceptually matching such patterns is similar to @llvm.bswap, and it was mentioned in http://reviews.llvm.org/D14234 that it would be best if these patterns were matched in InstCombine instead of reimplemented in every different target. This patch introduces an intrinsic @llvm.bitreverse.i* that operates similarly to @llvm.bswap. For plumbing purposes there is also a new ISD node ISD::BITREVERSE, with simple expansion and promotion support. The intention is that InstCombine's BSWAP detection logic will be extended to support BITREVERSE too, and @llvm.bitreverse intrinsics emitted (if the backend supports lowering it efficiently). llvm-svn: 252878
2015-11-12 20:29:09 +08:00
; These tests just check that the plumbing is in place for @llvm.bitreverse. The
; actual output is massive at the moment as llvm.bitreverse is not yet legal.
declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
[X86] Regenerated bitreverse tests to demonstrate what is going on. llvm-svn: 274915
2016-07-09 03:51:08 +08:00
define <2 x i16> @test_bitreverse_v2i16(<2 x i16> %a) nounwind {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: test_bitreverse_v2i16:
; X86: # BB#0:
[X86FixupBWInsts] More precise register liveness if no <imp-use> on MOVs. Summary: Subregister liveness tracking is not implemented for X86 backend, so sometimes the whole super register is said to be live, when only a subregister is really live. That might happen if the def and the use are located in different MBBs, see added fixup-bw-isnt.mir test. However, using knowledge of the specific instructions handled by the bw-fixup-pass we can get more precise liveness information which this change does. Reviewers: MatzeB, DavidKreitzer, ab, andrew.w.kaylor, craig.topper Reviewed By: craig.topper Subscribers: n.bozhenov, myatsina, llvm-commits, hiraditya Patch by Andrei Elovikov <andrei.elovikov@intel.com> Differential Revision: https://reviews.llvm.org/D37559 llvm-svn: 313524
2017-09-18 18:17:59 +08:00
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-NEXT: rolw $8, %ax
; X86-NEXT: movl %eax, %edx
; X86-NEXT: andl $3855, %edx # imm = 0xF0F
; X86-NEXT: shll $4, %edx
; X86-NEXT: andl $61680, %eax # imm = 0xF0F0
; X86-NEXT: shrl $4, %eax
; X86-NEXT: orl %edx, %eax
; X86-NEXT: movl %eax, %edx
; X86-NEXT: andl $13107, %edx # imm = 0x3333
; X86-NEXT: andl $52428, %eax # imm = 0xCCCC
; X86-NEXT: shrl $2, %eax
; X86-NEXT: leal (%eax,%edx,4), %eax
; X86-NEXT: movl %eax, %edx
; X86-NEXT: andl $21845, %edx # imm = 0x5555
; X86-NEXT: andl $43690, %eax # imm = 0xAAAA
; X86-NEXT: shrl %eax
; X86-NEXT: leal (%eax,%edx,2), %eax
; X86-NEXT: rolw $8, %cx
; X86-NEXT: movl %ecx, %edx
; X86-NEXT: andl $3855, %edx # imm = 0xF0F
; X86-NEXT: shll $4, %edx
; X86-NEXT: andl $61680, %ecx # imm = 0xF0F0
; X86-NEXT: shrl $4, %ecx
; X86-NEXT: orl %edx, %ecx
; X86-NEXT: movl %ecx, %edx
; X86-NEXT: andl $13107, %edx # imm = 0x3333
; X86-NEXT: andl $52428, %ecx # imm = 0xCCCC
; X86-NEXT: shrl $2, %ecx
; X86-NEXT: leal (%ecx,%edx,4), %ecx
; X86-NEXT: movl %ecx, %edx
; X86-NEXT: andl $21845, %edx # imm = 0x5555
; X86-NEXT: andl $43690, %ecx # imm = 0xAAAA
; X86-NEXT: shrl %ecx
; X86-NEXT: leal (%ecx,%edx,2), %edx
; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X86-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill>
; X86-NEXT: retl
;
; X64-LABEL: test_bitreverse_v2i16:
; X64: # BB#0:
; X64-NEXT: pxor %xmm1, %xmm1
; X64-NEXT: movdqa %xmm0, %xmm2
; X64-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; X64-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
; X64-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
; X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
; X64-NEXT: packuswb %xmm2, %xmm0
; X64-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X64-NEXT: movdqa %xmm0, %xmm2
; X64-NEXT: pand %xmm1, %xmm2
; X64-NEXT: psllw $4, %xmm2
; X64-NEXT: movdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; X64-NEXT: pand %xmm3, %xmm2
; X64-NEXT: pand %xmm3, %xmm0
; X64-NEXT: psrlw $4, %xmm0
; X64-NEXT: pand %xmm1, %xmm0
; X64-NEXT: por %xmm2, %xmm0
; X64-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; X64-NEXT: pand %xmm0, %xmm1
; X64-NEXT: psllw $2, %xmm1
; X64-NEXT: pand {{.*}}(%rip), %xmm1
; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: psrlw $2, %xmm0
; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: por %xmm1, %xmm0
; X64-NEXT: movdqa {{.*#+}} xmm1 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; X64-NEXT: pand %xmm0, %xmm1
; X64-NEXT: paddb %xmm1, %xmm1
; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: psrlw $1, %xmm0
; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: por %xmm1, %xmm0
; X64-NEXT: psrlq $48, %xmm0
; X64-NEXT: retq
[SDAG] Introduce a new BITREVERSE node along with a corresponding LLVM intrinsic Several backends have instructions to reverse the order of bits in an integer. Conceptually matching such patterns is similar to @llvm.bswap, and it was mentioned in http://reviews.llvm.org/D14234 that it would be best if these patterns were matched in InstCombine instead of reimplemented in every different target. This patch introduces an intrinsic @llvm.bitreverse.i* that operates similarly to @llvm.bswap. For plumbing purposes there is also a new ISD node ISD::BITREVERSE, with simple expansion and promotion support. The intention is that InstCombine's BSWAP detection logic will be extended to support BITREVERSE too, and @llvm.bitreverse intrinsics emitted (if the backend supports lowering it efficiently). llvm-svn: 252878
2015-11-12 20:29:09 +08:00
%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
ret <2 x i16> %b
}
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
declare i64 @llvm.bitreverse.i64(i64) readnone
define i64 @test_bitreverse_i64(i64 %a) nounwind {
; X86-LABEL: test_bitreverse_i64:
; X86: # BB#0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bswapl %eax
; X86-NEXT: movl %eax, %edx
; X86-NEXT: andl $252645135, %edx # imm = 0xF0F0F0F
; X86-NEXT: shll $4, %edx
; X86-NEXT: andl $-252645136, %eax # imm = 0xF0F0F0F0
; X86-NEXT: shrl $4, %eax
; X86-NEXT: orl %edx, %eax
; X86-NEXT: movl %eax, %edx
; X86-NEXT: andl $858993459, %edx # imm = 0x33333333
; X86-NEXT: andl $-858993460, %eax # imm = 0xCCCCCCCC
; X86-NEXT: shrl $2, %eax
; X86-NEXT: leal (%eax,%edx,4), %eax
; X86-NEXT: movl %eax, %edx
; X86-NEXT: andl $1431655765, %edx # imm = 0x55555555
; X86-NEXT: andl $-1431655766, %eax # imm = 0xAAAAAAAA
; X86-NEXT: shrl %eax
; X86-NEXT: leal (%eax,%edx,2), %eax
; X86-NEXT: bswapl %ecx
; X86-NEXT: movl %ecx, %edx
; X86-NEXT: andl $252645135, %edx # imm = 0xF0F0F0F
; X86-NEXT: shll $4, %edx
; X86-NEXT: andl $-252645136, %ecx # imm = 0xF0F0F0F0
; X86-NEXT: shrl $4, %ecx
; X86-NEXT: orl %edx, %ecx
; X86-NEXT: movl %ecx, %edx
; X86-NEXT: andl $858993459, %edx # imm = 0x33333333
; X86-NEXT: andl $-858993460, %ecx # imm = 0xCCCCCCCC
; X86-NEXT: shrl $2, %ecx
; X86-NEXT: leal (%ecx,%edx,4), %ecx
; X86-NEXT: movl %ecx, %edx
; X86-NEXT: andl $1431655765, %edx # imm = 0x55555555
; X86-NEXT: andl $-1431655766, %ecx # imm = 0xAAAAAAAA
; X86-NEXT: shrl %ecx
; X86-NEXT: leal (%ecx,%edx,2), %edx
; X86-NEXT: retl
;
; X64-LABEL: test_bitreverse_i64:
; X64: # BB#0:
; X64-NEXT: bswapq %rdi
; X64-NEXT: movabsq $1085102592571150095, %rax # imm = 0xF0F0F0F0F0F0F0F
; X64-NEXT: andq %rdi, %rax
; X64-NEXT: shlq $4, %rax
; X64-NEXT: movabsq $-1085102592571150096, %rcx # imm = 0xF0F0F0F0F0F0F0F0
; X64-NEXT: andq %rdi, %rcx
; X64-NEXT: shrq $4, %rcx
; X64-NEXT: orq %rax, %rcx
; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333
; X64-NEXT: andq %rcx, %rax
; X64-NEXT: movabsq $-3689348814741910324, %rdx # imm = 0xCCCCCCCCCCCCCCCC
; X64-NEXT: andq %rcx, %rdx
; X64-NEXT: shrq $2, %rdx
; X64-NEXT: leaq (%rdx,%rax,4), %rax
; X64-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NEXT: andq %rax, %rcx
; X64-NEXT: movabsq $-6148914691236517206, %rdx # imm = 0xAAAAAAAAAAAAAAAA
; X64-NEXT: andq %rax, %rdx
; X64-NEXT: shrq %rdx
; X64-NEXT: leaq (%rdx,%rcx,2), %rax
; X64-NEXT: retq
%b = call i64 @llvm.bitreverse.i64(i64 %a)
ret i64 %b
}
declare i32 @llvm.bitreverse.i32(i32) readnone
define i32 @test_bitreverse_i32(i32 %a) nounwind {
; X86-LABEL: test_bitreverse_i32:
; X86: # BB#0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bswapl %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andl $252645135, %ecx # imm = 0xF0F0F0F
; X86-NEXT: shll $4, %ecx
; X86-NEXT: andl $-252645136, %eax # imm = 0xF0F0F0F0
; X86-NEXT: shrl $4, %eax
; X86-NEXT: orl %ecx, %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andl $858993459, %ecx # imm = 0x33333333
; X86-NEXT: andl $-858993460, %eax # imm = 0xCCCCCCCC
; X86-NEXT: shrl $2, %eax
; X86-NEXT: leal (%eax,%ecx,4), %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andl $1431655765, %ecx # imm = 0x55555555
; X86-NEXT: andl $-1431655766, %eax # imm = 0xAAAAAAAA
; X86-NEXT: shrl %eax
; X86-NEXT: leal (%eax,%ecx,2), %eax
; X86-NEXT: retl
;
; X64-LABEL: test_bitreverse_i32:
; X64: # BB#0:
; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; X64-NEXT: bswapl %edi
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F
; X64-NEXT: shll $4, %eax
; X64-NEXT: andl $-252645136, %edi # imm = 0xF0F0F0F0
; X64-NEXT: shrl $4, %edi
; X64-NEXT: orl %eax, %edi
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andl $858993459, %eax # imm = 0x33333333
; X64-NEXT: andl $-858993460, %edi # imm = 0xCCCCCCCC
; X64-NEXT: shrl $2, %edi
; X64-NEXT: leal (%rdi,%rax,4), %eax
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: andl $1431655765, %ecx # imm = 0x55555555
; X64-NEXT: andl $-1431655766, %eax # imm = 0xAAAAAAAA
; X64-NEXT: shrl %eax
; X64-NEXT: leal (%rax,%rcx,2), %eax
; X64-NEXT: retq
%b = call i32 @llvm.bitreverse.i32(i32 %a)
ret i32 %b
}
[X86] Added bitreverse tests for non-legal types Requested on D21578 llvm-svn: 274914
2016-07-09 03:48:33 +08:00
declare i24 @llvm.bitreverse.i24(i24) readnone
[X86] Regenerated bitreverse tests to demonstrate what is going on. llvm-svn: 274915
2016-07-09 03:51:08 +08:00
define i24 @test_bitreverse_i24(i24 %a) nounwind {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: test_bitreverse_i24:
; X86: # BB#0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bswapl %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andl $252645135, %ecx # imm = 0xF0F0F0F
; X86-NEXT: shll $4, %ecx
; X86-NEXT: andl $-252645136, %eax # imm = 0xF0F0F0F0
; X86-NEXT: shrl $4, %eax
; X86-NEXT: orl %ecx, %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andl $858993459, %ecx # imm = 0x33333333
; X86-NEXT: andl $-858993460, %eax # imm = 0xCCCCCCCC
; X86-NEXT: shrl $2, %eax
; X86-NEXT: leal (%eax,%ecx,4), %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andl $1431655680, %ecx # imm = 0x55555500
; X86-NEXT: andl $-1431655936, %eax # imm = 0xAAAAAA00
; X86-NEXT: shrl %eax
; X86-NEXT: leal (%eax,%ecx,2), %eax
; X86-NEXT: shrl $8, %eax
; X86-NEXT: retl
;
; X64-LABEL: test_bitreverse_i24:
; X64: # BB#0:
; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; X64-NEXT: bswapl %edi
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F
; X64-NEXT: shll $4, %eax
; X64-NEXT: andl $-252645136, %edi # imm = 0xF0F0F0F0
; X64-NEXT: shrl $4, %edi
; X64-NEXT: orl %eax, %edi
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andl $858993459, %eax # imm = 0x33333333
; X64-NEXT: andl $-858993460, %edi # imm = 0xCCCCCCCC
; X64-NEXT: shrl $2, %edi
; X64-NEXT: leal (%rdi,%rax,4), %eax
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: andl $1431655680, %ecx # imm = 0x55555500
; X64-NEXT: andl $-1431655936, %eax # imm = 0xAAAAAA00
; X64-NEXT: shrl %eax
; X64-NEXT: leal (%rax,%rcx,2), %eax
; X64-NEXT: shrl $8, %eax
; X64-NEXT: retq
[X86] Added bitreverse tests for non-legal types Requested on D21578 llvm-svn: 274914
2016-07-09 03:48:33 +08:00
%b = call i24 @llvm.bitreverse.i24(i24 %a)
ret i24 %b
}
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
declare i16 @llvm.bitreverse.i16(i16) readnone
define i16 @test_bitreverse_i16(i16 %a) nounwind {
; X86-LABEL: test_bitreverse_i16:
; X86: # BB#0:
[X86FixupBWInsts] More precise register liveness if no <imp-use> on MOVs. Summary: Subregister liveness tracking is not implemented for X86 backend, so sometimes the whole super register is said to be live, when only a subregister is really live. That might happen if the def and the use are located in different MBBs, see added fixup-bw-isnt.mir test. However, using knowledge of the specific instructions handled by the bw-fixup-pass we can get more precise liveness information which this change does. Reviewers: MatzeB, DavidKreitzer, ab, andrew.w.kaylor, craig.topper Reviewed By: craig.topper Subscribers: n.bozhenov, myatsina, llvm-commits, hiraditya Patch by Andrei Elovikov <andrei.elovikov@intel.com> Differential Revision: https://reviews.llvm.org/D37559 llvm-svn: 313524
2017-09-18 18:17:59 +08:00
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-NEXT: rolw $8, %ax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andl $3855, %ecx # imm = 0xF0F
; X86-NEXT: shll $4, %ecx
; X86-NEXT: andl $61680, %eax # imm = 0xF0F0
; X86-NEXT: shrl $4, %eax
; X86-NEXT: orl %ecx, %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andl $13107, %ecx # imm = 0x3333
; X86-NEXT: andl $52428, %eax # imm = 0xCCCC
; X86-NEXT: shrl $2, %eax
; X86-NEXT: leal (%eax,%ecx,4), %eax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andl $21845, %ecx # imm = 0x5555
; X86-NEXT: andl $43690, %eax # imm = 0xAAAA
; X86-NEXT: shrl %eax
; X86-NEXT: leal (%eax,%ecx,2), %eax
; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X86-NEXT: retl
;
; X64-LABEL: test_bitreverse_i16:
; X64: # BB#0:
; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; X64-NEXT: rolw $8, %di
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andl $3855, %eax # imm = 0xF0F
; X64-NEXT: shll $4, %eax
; X64-NEXT: andl $61680, %edi # imm = 0xF0F0
; X64-NEXT: shrl $4, %edi
; X64-NEXT: orl %eax, %edi
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andl $13107, %eax # imm = 0x3333
; X64-NEXT: andl $52428, %edi # imm = 0xCCCC
; X64-NEXT: shrl $2, %edi
; X64-NEXT: leal (%rdi,%rax,4), %eax
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: andl $21845, %ecx # imm = 0x5555
; X64-NEXT: andl $43690, %eax # imm = 0xAAAA
; X64-NEXT: shrl %eax
; X64-NEXT: leal (%rax,%rcx,2), %eax
; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X64-NEXT: retq
%b = call i16 @llvm.bitreverse.i16(i16 %a)
ret i16 %b
}
[SDAG] Introduce a new BITREVERSE node along with a corresponding LLVM intrinsic Several backends have instructions to reverse the order of bits in an integer. Conceptually matching such patterns is similar to @llvm.bswap, and it was mentioned in http://reviews.llvm.org/D14234 that it would be best if these patterns were matched in InstCombine instead of reimplemented in every different target. This patch introduces an intrinsic @llvm.bitreverse.i* that operates similarly to @llvm.bswap. For plumbing purposes there is also a new ISD node ISD::BITREVERSE, with simple expansion and promotion support. The intention is that InstCombine's BSWAP detection logic will be extended to support BITREVERSE too, and @llvm.bitreverse intrinsics emitted (if the backend supports lowering it efficiently). llvm-svn: 252878
2015-11-12 20:29:09 +08:00
declare i8 @llvm.bitreverse.i8(i8) readnone
[X86] Added bitreverse tests for non-legal types Requested on D21578 llvm-svn: 274914
2016-07-09 03:48:33 +08:00
define i8 @test_bitreverse_i8(i8 %a) {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: test_bitreverse_i8:
; X86: # BB#0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: rolb $4, %al
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andb $51, %cl
; X86-NEXT: shlb $2, %cl
; X86-NEXT: andb $-52, %al
; X86-NEXT: shrb $2, %al
; X86-NEXT: orb %cl, %al
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andb $85, %cl
; X86-NEXT: addb %cl, %cl
; X86-NEXT: andb $-86, %al
; X86-NEXT: shrb %al
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
; X64-LABEL: test_bitreverse_i8:
; X64: # BB#0:
; X64-NEXT: rolb $4, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $51, %al
; X64-NEXT: shlb $2, %al
; X64-NEXT: andb $-52, %dil
; X64-NEXT: shrb $2, %dil
; X64-NEXT: orb %al, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $85, %al
; X64-NEXT: addb %al, %al
; X64-NEXT: andb $-86, %dil
; X64-NEXT: shrb %dil
; X64-NEXT: orb %al, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: retq
[SDAG] Introduce a new BITREVERSE node along with a corresponding LLVM intrinsic Several backends have instructions to reverse the order of bits in an integer. Conceptually matching such patterns is similar to @llvm.bswap, and it was mentioned in http://reviews.llvm.org/D14234 that it would be best if these patterns were matched in InstCombine instead of reimplemented in every different target. This patch introduces an intrinsic @llvm.bitreverse.i* that operates similarly to @llvm.bswap. For plumbing purposes there is also a new ISD node ISD::BITREVERSE, with simple expansion and promotion support. The intention is that InstCombine's BSWAP detection logic will be extended to support BITREVERSE too, and @llvm.bitreverse intrinsics emitted (if the backend supports lowering it efficiently). llvm-svn: 252878
2015-11-12 20:29:09 +08:00
%b = call i8 @llvm.bitreverse.i8(i8 %a)
ret i8 %b
}
[X86] Added BITREVERSE constant folding and identity tests Identity tests are currently failing - this will be fixed soon llvm-svn: 268862
2016-05-08 03:04:00 +08:00
[X86] Added bitreverse tests for non-legal types Requested on D21578 llvm-svn: 274914
2016-07-09 03:48:33 +08:00
declare i4 @llvm.bitreverse.i4(i4) readnone
define i4 @test_bitreverse_i4(i4 %a) {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: test_bitreverse_i4:
; X86: # BB#0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: rolb $4, %al
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andb $51, %cl
; X86-NEXT: shlb $2, %cl
; X86-NEXT: andb $-52, %al
; X86-NEXT: shrb $2, %al
; X86-NEXT: orb %cl, %al
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andb $80, %cl
; X86-NEXT: addb %cl, %cl
; X86-NEXT: andb $-96, %al
; X86-NEXT: shrb %al
; X86-NEXT: orb %cl, %al
; X86-NEXT: shrb $4, %al
; X86-NEXT: retl
;
; X64-LABEL: test_bitreverse_i4:
; X64: # BB#0:
; X64-NEXT: rolb $4, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $51, %al
; X64-NEXT: shlb $2, %al
; X64-NEXT: andb $-52, %dil
; X64-NEXT: shrb $2, %dil
; X64-NEXT: orb %al, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $80, %al
; X64-NEXT: addb %al, %al
; X64-NEXT: andb $-96, %dil
; X64-NEXT: shrb %dil
; X64-NEXT: orb %al, %dil
; X64-NEXT: shrb $4, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: retq
[X86] Added bitreverse tests for non-legal types Requested on D21578 llvm-svn: 274914
2016-07-09 03:48:33 +08:00
%b = call i4 @llvm.bitreverse.i4(i4 %a)
ret i4 %b
}
[X86] Added BITREVERSE constant folding and identity tests Identity tests are currently failing - this will be fixed soon llvm-svn: 268862
2016-05-08 03:04:00 +08:00
; These tests check that bitreverse(constant) calls are folded
define <2 x i16> @fold_v2i16() {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: fold_v2i16:
; X86: # BB#0:
; X86-NEXT: movw $-4096, %ax # imm = 0xF000
; X86-NEXT: movw $240, %dx
; X86-NEXT: retl
;
; X64-LABEL: fold_v2i16:
; X64: # BB#0:
; X64-NEXT: movaps {{.*#+}} xmm0 = [61440,240]
; X64-NEXT: retq
[X86] Added BITREVERSE constant folding and identity tests Identity tests are currently failing - this will be fixed soon llvm-svn: 268862
2016-05-08 03:04:00 +08:00
%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> <i16 15, i16 3840>)
ret <2 x i16> %b
}
[X86] Added bitreverse tests for non-legal types Requested on D21578 llvm-svn: 274914
2016-07-09 03:48:33 +08:00
define i24 @fold_i24() {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: fold_i24:
; X86: # BB#0:
; X86-NEXT: movl $2048, %eax # imm = 0x800
; X86-NEXT: retl
;
; X64-LABEL: fold_i24:
; X64: # BB#0:
; X64-NEXT: movl $2048, %eax # imm = 0x800
; X64-NEXT: retq
[X86] Added bitreverse tests for non-legal types Requested on D21578 llvm-svn: 274914
2016-07-09 03:48:33 +08:00
%b = call i24 @llvm.bitreverse.i24(i24 4096)
ret i24 %b
}
[X86] Added BITREVERSE constant folding and identity tests Identity tests are currently failing - this will be fixed soon llvm-svn: 268862
2016-05-08 03:04:00 +08:00
define i8 @fold_i8() {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: fold_i8:
; X86: # BB#0:
; X86-NEXT: movb $-16, %al
; X86-NEXT: retl
;
; X64-LABEL: fold_i8:
; X64: # BB#0:
; X64-NEXT: movb $-16, %al
; X64-NEXT: retq
[X86] Added BITREVERSE constant folding and identity tests Identity tests are currently failing - this will be fixed soon llvm-svn: 268862
2016-05-08 03:04:00 +08:00
%b = call i8 @llvm.bitreverse.i8(i8 15)
ret i8 %b
}
[X86] Added bitreverse tests for non-legal types Requested on D21578 llvm-svn: 274914
2016-07-09 03:48:33 +08:00
define i4 @fold_i4() {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: fold_i4:
; X86: # BB#0:
; X86-NEXT: movb $1, %al
; X86-NEXT: retl
;
; X64-LABEL: fold_i4:
; X64: # BB#0:
; X64-NEXT: movb $1, %al
; X64-NEXT: retq
[X86] Added bitreverse tests for non-legal types Requested on D21578 llvm-svn: 274914
2016-07-09 03:48:33 +08:00
%b = call i4 @llvm.bitreverse.i4(i4 8)
ret i4 %b
}
[X86] Added BITREVERSE constant folding and identity tests Identity tests are currently failing - this will be fixed soon llvm-svn: 268862
2016-05-08 03:04:00 +08:00
; These tests check that bitreverse(bitreverse()) calls are removed
define i8 @identity_i8(i8 %a) {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: identity_i8:
; X86: # BB#0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: retl
;
; X64-LABEL: identity_i8:
; X64: # BB#0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: retq
[X86] Added BITREVERSE constant folding and identity tests Identity tests are currently failing - this will be fixed soon llvm-svn: 268862
2016-05-08 03:04:00 +08:00
%b = call i8 @llvm.bitreverse.i8(i8 %a)
%c = call i8 @llvm.bitreverse.i8(i8 %b)
ret i8 %c
}
define <2 x i16> @identity_v2i16(<2 x i16> %a) {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: identity_v2i16:
; X86: # BB#0:
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
; X86-NEXT: retl
;
; X64-LABEL: identity_v2i16:
; X64: # BB#0:
; X64-NEXT: retq
[X86] Added BITREVERSE constant folding and identity tests Identity tests are currently failing - this will be fixed soon llvm-svn: 268862
2016-05-08 03:04:00 +08:00
%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
%c = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %b)
ret <2 x i16> %c
}
[SelectionDAG] Added bitreverse(bitreverse(v)) --> v Added bitreverse creation testing llvm-svn: 268865
2016-05-08 04:12:36 +08:00
; These tests check that bitreverse(undef) calls are removed
define i8 @undef_i8() {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: undef_i8:
; X86: # BB#0:
; X86-NEXT: retl
;
; X64-LABEL: undef_i8:
; X64: # BB#0:
; X64-NEXT: retq
[SelectionDAG] Added bitreverse(bitreverse(v)) --> v Added bitreverse creation testing llvm-svn: 268865
2016-05-08 04:12:36 +08:00
%b = call i8 @llvm.bitreverse.i8(i8 undef)
ret i8 %b
}
define <2 x i16> @undef_v2i16() {
[X86] Add extra BITREVERSE tests Test on 32-bit and 64-bit targets. Add bitreverse tests for i64, i32 and i16 llvm-svn: 297741
2017-03-14 22:03:16 +08:00
; X86-LABEL: undef_v2i16:
; X86: # BB#0:
; X86-NEXT: retl
;
; X64-LABEL: undef_v2i16:
; X64: # BB#0:
; X64-NEXT: retq
[SelectionDAG] Added bitreverse(bitreverse(v)) --> v Added bitreverse creation testing llvm-svn: 268865
2016-05-08 04:12:36 +08:00
%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> undef)
ret <2 x i16> %b
}