llvm-project/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir

# RUN: llc -march=amdgcn -run-pass si-fix-sgpr-copies %s -o - | FileCheck %s -check-prefixes=GCN

--- |
  define amdgpu_kernel void @phi_visit_order() { ret void }

name: phi_visit_order
tracksRegLiveness: true
registers:
  - { id: 0, class: sreg_32_xm0 }
  - { id: 1, class: sreg_64 }
  - { id: 2, class: sreg_32_xm0 }
  - { id: 7, class: vgpr_32 }
  - { id: 8, class: sreg_32_xm0 }
  - { id: 9, class: vgpr_32 }
  - { id: 10, class: sreg_64 }
  - { id: 11, class: sreg_32_xm0 }

body: |
  ; GCN-LABEL: name: phi_visit_order
  ; GCN: V_ADD_I32
  bb.0:
    liveins: %vgpr0
    %7 = COPY %vgpr0
    %8 = S_MOV_B32 0

  bb.1:
    %0 = PHI %8, %bb.0, %0, %bb.1, %2, %bb.2
    %9 = V_MOV_B32_e32 9, implicit %exec
    %10 = V_CMP_EQ_U32_e64 %7, %9, implicit %exec
    %1 = SI_IF %10, %bb.2, implicit-def %exec, implicit-def %scc, implicit %exec
    S_BRANCH %bb.1

  bb.2:
    SI_END_CF %1, implicit-def %exec, implicit-def %scc, implicit %exec
    %11 = S_MOV_B32 1
    %2 = S_ADD_I32 %0, %11, implicit-def %scc
    S_BRANCH %bb.1

...
---